commit 9f94778c1603420e48d779a495e84eb82945cc75
author Artyom Tarasenko <atar4qemu@gmail.com> Mon Jul 25 19:22:38 2011 +0200
committer Blue Swirl <blauwirbel@gmail.com> Sun Aug 28 11:38:13 2011 +0000
tree 735f2ae72f858c7a223b5c34c95578817eb25532
parent 010f3f5fbd5f8edc1a584b5388f8ea2ad518a439

Fix disabling interrupts in sun4u

clear interrupt request if the interrupt priority < CPU pil
clear hardware interrupt request if interrupts are disabled

Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
[blauwirbel@gmail.com: added a comment about magic 2]
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>

hw/sun4u.c

diff --git a/hw/sun4u.c b/hw/sun4u.c
index 1b60e4e..32e6ab9 100644
--- a/hw/sun4u.c
+++ b/hw/sun4u.c
@@ -261,7 +261,9 @@
         pil |= 1 << 14;
     }
 
-    if (!pil) {
+    /* The bit corresponding to psrpil is (1<< psrpil), the next bit
+       is (2 << psrpil). */
+    if (pil < (2 << env->psrpil)){
         if (env->interrupt_request & CPU_INTERRUPT_HARD) {
             CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
                            env->interrupt_index);
@@ -293,10 +295,12 @@
                 break;
             }
         }
-    } else {
+    } else if (env->interrupt_request & CPU_INTERRUPT_HARD) {
         CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
                        "current interrupt %x\n",
                        pil, env->pil_in, env->softint, env->interrupt_index);
+        env->interrupt_index = 0;
+        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
     }
 }