)]}'
{
  "commit": "9ff9dd3c875956523bb4c19ca712e5d05aab3c65",
  "tree": "ba0b94ea33a9cf9a88468518c33c9cc106ba8612",
  "parents": [
    "b4d3978c2fdf944e428a46d2850dbd950b6fbe78"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Thu Aug 13 11:26:22 2015 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Thu Aug 13 11:26:22 2015 +0100"
  },
  "message": "target-arm: Add AArch32 banked register access to secure physical timer\n\nIf EL3 is AArch32, then the secure physical timer is accessed via\nbanking of the registers used for the non-secure physical timer.\nImplement this banking.\n\nNote that the access controls for the AArch32 banked registers\nremain the same as the physical-timer checks; they are not the\nsame as the controls on the AArch64 secure timer registers.\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 1437047249-2357-3-git-send-email-peter.maydell@linaro.org\nReviewed-by: Edgar E. Iglesias \u003cedgar.iglesias@xilinx.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "7cf6ffd340a0167d91558a934d7b38edfd7670bc",
      "old_mode": 33188,
      "old_path": "target-arm/helper.c",
      "new_id": "1568aa6617ef659c9ee6ec9ffe3e7b9354313271",
      "new_mode": 33188,
      "new_path": "target-arm/helper.c"
    }
  ]
}