)]}'
{
  "commit": "a1bc20dfbb012ea2a5fb1228cb77abd04490fd79",
  "tree": "9ef704599b65f54a1e7e9703b2dab16f08f470c0",
  "parents": [
    "626c7a171e644fbe1579516b8b794d611c295d2f"
  ],
  "author": {
    "name": "Alexander Graf",
    "email": "agraf@suse.de",
    "time": "Mon Oct 08 12:21:30 2012 +0200"
  },
  "committer": {
    "name": "Alexander Graf",
    "email": "agraf@suse.de",
    "time": "Mon Oct 29 11:45:56 2012 +0100"
  },
  "message": "PPC: e500: Map PIO space into core memory region\n\nOn PPC, we don\u0027t have PIO. So usually PIO space behind a PCI bridge is\naccessible via MMIO. Do this mapping explicitly by mapping the PIO space\nof our PCI bus into a memory region that lives in memory space.\n\nSigned-off-by: Alexander Graf \u003cagraf@suse.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "90d88ebc74a2822633fa1d14ddc41d692a189c2e",
      "old_mode": 33188,
      "old_path": "hw/ppc/e500.c",
      "new_id": "6749ffffb3e176bf52d90626c20295e299aefde9",
      "new_mode": 33188,
      "new_path": "hw/ppc/e500.c"
    },
    {
      "type": "modify",
      "old_id": "332748a6de137439db819eb8df3c12be4e22a66f",
      "old_mode": 33188,
      "old_path": "hw/ppce500_pci.c",
      "new_id": "2ff7438d09e2065166be33ea98ee8a1bc4b80aad",
      "new_mode": 33188,
      "new_path": "hw/ppce500_pci.c"
    }
  ]
}