)]}'
{
  "commit": "a9d477c4e3d614409a48d12f34624c2dd9f1ec2d",
  "tree": "71fe4a9c627ea3e375b1c428a527b9bf61ee2ea6",
  "parents": [
    "a1b1d277cdaac98f25be249e7819aac781a35530"
  ],
  "author": {
    "name": "Christoffer Dall",
    "email": "christoffer.dall@linaro.org",
    "time": "Mon Nov 18 19:26:33 2013 -0800"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Sat Feb 08 14:50:48 2014 +0000"
  },
  "message": "arm_gic: Add GICC_APRn state to the GICState\n\nThe GICC_APRn registers are not currently supported by the ARM GIC v2.0\nemulation.  This patch adds the missing state.\n\nNote that we also change the number of APRs to use a define GIC_NR_APRS\nbased on the maximum number of preemption levels.  This patch also adds\nRAZ/WI accessors for the four registers on the emulated CPU interface.\n\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nSigned-off-by: Christoffer Dall \u003cchristoffer.dall@linaro.org\u003e\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "5413a2482a1856f3adb5c5d1e3d3016e28fd9d32",
      "old_mode": 33188,
      "old_path": "hw/intc/arm_gic.c",
      "new_id": "93eaa6b2fa73d75fa3266c37110c6d409d8255e5",
      "new_mode": 33188,
      "new_path": "hw/intc/arm_gic.c"
    },
    {
      "type": "modify",
      "old_id": "d2d8ce1bb40ac2d679b5da9ff062568b6cd39cbc",
      "old_mode": 33188,
      "old_path": "hw/intc/arm_gic_common.c",
      "new_id": "6d884eca3b50b295f9ab25745a9603c521cd6057",
      "new_mode": 33188,
      "new_path": "hw/intc/arm_gic_common.c"
    },
    {
      "type": "modify",
      "old_id": "983c3cfa93953e438ae01fe643c308ddef7cec1c",
      "old_mode": 33188,
      "old_path": "include/hw/intc/arm_gic_common.h",
      "new_id": "89384c2bb4eceff64cb364cc1c333b4596b0859d",
      "new_mode": 33188,
      "new_path": "include/hw/intc/arm_gic_common.h"
    }
  ]
}