)]}'
{
  "commit": "ae80a3546f412c407199b9b7ebd52ac604361e10",
  "tree": "a1e979f97c5d2d0ad72c7fcba85afe21e1eb0dfc",
  "parents": [
    "1c5d07909aea7657c7c6b24223460150526369ba"
  ],
  "author": {
    "name": "Peter Crosthwaite",
    "email": "peter.crosthwaite@xilinx.com",
    "time": "Thu Feb 28 18:23:15 2013 +0000"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Thu Feb 28 18:49:24 2013 +0000"
  },
  "message": "cadence_gem: fix interrupt events\n\nBits in the ISR were continually mirroring their corresponding TX/RX SR bits.\nThis is incorrect. The ISR bits are only ever set at the time their\ncorresponding event occurs.\n\nSigned-off-by: Peter Crosthwaite \u003cpeter.crosthwaite@xilinx.com\u003e\nMessage-id: cedfb6d108318846480b416a6041023ea5a353d6.1360901435.git.peter.crosthwaite@xilinx.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "966ab4f8a82c136aec2c5570e2e0a4abfdb5876a",
      "old_mode": 33188,
      "old_path": "hw/cadence_gem.c",
      "new_id": "a1ac069a205e2911483a3c7796ef5d88f8eaf92a",
      "new_mode": 33188,
      "new_path": "hw/cadence_gem.c"
    }
  ]
}