)]}'
{
  "commit": "b4a8c9ae9758efb6873097f415e9972127ccf418",
  "tree": "c1d3111448f3847e7f8a5cddfa7bc3ea47d353ef",
  "parents": [
    "850bbe1b94445cb84a2f648bc2e8c35ef6188eb4",
    "5b0adce156216fb24dcc5f1683e8b686f3793fff"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Sat Feb 01 23:06:11 2014 +0000"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Sat Feb 01 23:06:26 2014 +0000"
  },
  "message": "Merge remote-tracking branch \u0027pmaydell/tags/pull-target-arm-20140131\u0027 into staging\n\ntarget-arm queue:\n * implementation of first part of the A64 Neon instruction set\n * v8 AArch32 rounding and 16\u003c-\u003e64 fp conversion instructions\n * fix MIDR value on Zynq boards\n * some minor bugfixes/code cleanups\n\n# gpg: Signature made Fri 31 Jan 2014 15:06:34 GMT using RSA key ID 14360CDE\n# gpg: Good signature from \"Peter Maydell \u003cpeter.maydell@linaro.org\u003e\"\n\n* pmaydell/tags/pull-target-arm-20140131: (34 commits)\n  arm_gic: Fix GICD_ICPENDR and GICD_ISPENDR writes\n  arm_gic: Introduce define for GIC_NR_SGIS\n  target-arm: A64: Add SIMD shift by immediate\n  target-arm: A64: Add simple SIMD 3-same floating point ops\n  target-arm: A64: Add integer ops from SIMD 3-same group\n  target-arm: A64: Add logic ops from SIMD 3 same group\n  target-arm: A64: Add top level decode for SIMD 3-same group\n  target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops\n  target-arm: A64: Add SIMD three-different ABDL instructions\n  target-arm: A64: Add SIMD three-different multiply accumulate insns\n  target-arm: Add AArch32 SIMD VCVTA, VCVTN, VCVTP and VCVTM\n  target-arm: Add AArch32 FP VCVTA, VCVTN, VCVTP and VCVTM\n  target-arm: Add AArch32 SIMD VRINTA, VRINTN, VRINTP, VRINTM, VRINTZ\n  target-arm: Add set_neon_rmode helper\n  target-arm: Add support for AArch32 SIMD VRINTX\n  target-arm: Add support for AArch32 FP VRINTX\n  target-arm: Add support for AArch32 FP VRINTZ\n  target-arm: Add support for AArch32 FP VRINTR\n  target-arm: Add AArch32 FP VRINTA, VRINTN, VRINTP and VRINTM\n  target-arm: Move arm_rmode_to_sf to a shared location.\n  ...\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": []
}