)]}'
{
  "commit": "b5a12aa204f842c8010ac9d2e4b115114dbf09f0",
  "tree": "b68aaa746a014fe70428204fdc682c11c83c7833",
  "parents": [
    "9f60639b848944200c3d33a89233d808de0b5a43",
    "50c796f9d842bbefeb39ac64d7fe961056ee0267"
  ],
  "author": {
    "name": "Blue Swirl",
    "email": "blauwirbel@gmail.com",
    "time": "Thu Oct 27 20:27:07 2011 +0000"
  },
  "committer": {
    "name": "Blue Swirl",
    "email": "blauwirbel@gmail.com",
    "time": "Thu Oct 27 20:27:07 2011 +0000"
  },
  "message": "Merge branch \u0027rth/vis2\u0027 of git://repo.or.cz/qemu/rth\n\n* \u0027rth/vis2\u0027 of git://repo.or.cz/qemu/rth:\n  target-sparc: Implement FALIGNDATA inline.\n  target-sparc: Implement BMASK/BSHUFFLE.\n  target-sparc: Implement ALIGNADDR* inline.\n  target-sparc: Implement EDGE* instructions.\n  target-sparc: Implement fpack{16,32,fix}.\n  target-sparc: Implement PDIST.\n  target-sparc: Do exceptions management fully inside the helpers.\n  target-sparc: Change fpr representation to doubles.\n  target-sparc: Undo cpu_fpr rename.\n  target-sparc: Extract float128 move to a function.\n  target-sparc: Extract common code for floating-point operations.\n  target-sparc: Make FPU/VIS helpers const when possible.\n  target-sparc: Pass float64 parameters instead of dt0/1 temporaries.\n  target-sparc: Add accessors for double-precision fpr access.\n  target-sparc: Mark fprs dirty in store accessor.\n  target-sparc: Add accessors for single-precision fpr access.\n",
  "tree_diff": []
}