)]}'
{
  "commit": "bc79082e4cd12c1241fa03b0abceacf45f537740",
  "tree": "f07a84ff8655bd6b7e57e50252edf6697d1101e2",
  "parents": [
    "1e700f4c6cddaf29ce1d205f0f8e8b9255481930",
    "31bfa2a40004204aee503c6417fbafb5d17e0a51"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Fri Oct 23 16:35:43 2015 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Fri Oct 23 16:35:43 2015 +0100"
  },
  "message": "Merge remote-tracking branch \u0027remotes/ehabkost/tags/x86-pull-request\u0027 into staging\n\nX86 queue, 2015-10-23\n\n# gpg: Signature made Fri 23 Oct 2015 16:30:58 BST using RSA key ID 984DC5A6\n# gpg: Good signature from \"Eduardo Habkost \u003cehabkost@redhat.com\u003e\"\n\n* remotes/ehabkost/tags/x86-pull-request:\n  vl: trivial: minor tweaks to a max-cpu error msg\n  target-i386: Use 1UL for bit shift\n  target-i386: Add DE to TCG_FEATURES\n  target-i386: Ensure always-1 bits on DR6 can\u0027t be cleared\n  target-i386: Check CR4[DE] for processing DR4/DR5\n  target-i386: Handle I/O breakpoints\n  target-i386: Optimize setting dr[0-3]\n  target-i386: Move hw_*breakpoint_* functions\n  target-i386: Ensure bit 10 on DR7 is never cleared\n  target-i386: Re-introduce optimal breakpoint removal\n  target-i386: Introduce cpu_x86_update_dr7\n  target-i386: Disable cache info passthrough by default\n  target-i386: allow any alignment for SMBASE\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": []
}