)]}'
{
  "commit": "be5e7a76010bd14d09f74504ed6368782e701888",
  "tree": "70418830723cfd7422f72d5c04d04d48e278f9f1",
  "parents": [
    "4b4a72e55660abf7efe85aca78762dcfea5519ad"
  ],
  "author": {
    "name": "Dmitry Eremin-Solenikov",
    "email": "dbaryshkov@gmail.com",
    "time": "Mon Apr 04 17:38:44 2011 +0400"
  },
  "committer": {
    "name": "Aurelien Jarno",
    "email": "aurelien@aurel32.net",
    "time": "Sun Apr 10 00:53:21 2011 +0200"
  },
  "message": "arm: basic support for ARMv4/ARMv4T emulation\n\nCurrently target-arm/ assumes at least ARMv5 core. Add support for\nhandling also ARMv4/ARMv4T. This changes the following instructions:\n\nBX(v4T and later)\n\nBKPT, BLX, CDP2, CLZ, LDC2, LDRD, MCRR, MCRR2, MRRC, MCRR, MRC2, MRRC,\nMRRC2, PLD QADD, QDADD, QDSUB, QSUB, STRD, SMLAxy, SMLALxy, SMLAWxy,\nSMULxy, SMULWxy, STC2 (v5 and later)\n\nAll instructions that are \"v5TE and later\" are also bound to just v5, as\nthat\u0027s how it was before.\n\nThis patch doesn _not_ include disabling of cp15 access and base-updated\ndata abort model (that will be required to emulate chips based on a\nARM7TDMI), because:\n* no ARM7TDMI chips are currently emulated (or planned)\n* those features aren\u0027t strictly necessary for my purposes (SA-1 core\n  emulation).\n\nAll v5 models are handled as they are v5T. Internally we still have a\ncheck if the model is a v5(T) or v5TE, but as all emulated cores are\nv5TE, those two cases are simply aliased (for now).\n\nPatch is heavily based on patch by Filip Navara \u003cfilip.navara@gmail.com\u003e\nwhich in turn is based on work by Ulrich Hecht \u003culi@suse.de\u003e and Vincent\nSanders \u003cvince@kyllikki.org\u003e.\n\nSigned-off-by: Dmitry Eremin-Solenikov \u003cdbaryshkov@gmail.com\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nSigned-off-by: Aurelien Jarno \u003caurelien@aurel32.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1ae7982c7f13cc2ac12d53b9f9f10ccf3d18f78d",
      "old_mode": 33188,
      "old_path": "target-arm/cpu.h",
      "new_id": "e247a7ade0604da77dbab8dfcb2b4ac46c0d3b97",
      "new_mode": 33188,
      "new_path": "target-arm/cpu.h"
    },
    {
      "type": "modify",
      "old_id": "6788a4c3836af5271ef6d648cb1a50758e4166be",
      "old_mode": 33188,
      "old_path": "target-arm/helper.c",
      "new_id": "ce9a9d8fd25b61e1c8dd44e68ae697945ece4c7e",
      "new_mode": 33188,
      "new_path": "target-arm/helper.c"
    },
    {
      "type": "modify",
      "old_id": "55d524ba138e236d22f0551421efa79c4a991306",
      "old_mode": 33188,
      "old_path": "target-arm/translate.c",
      "new_id": "998cfd530c80557a603a9e518de43b397667d681",
      "new_mode": 33188,
      "new_path": "target-arm/translate.c"
    }
  ]
}