)]}'
{
  "commit": "c2f01775dddb9e8ab5595400290d6379910ef2be",
  "tree": "fc016bc9bf00ea3f9872700019a3ac0328dd3337",
  "parents": [
    "e0e36fe91d2eadcec8159eb6d728c9dd7fc6cf44"
  ],
  "author": {
    "name": "balrog",
    "email": "balrog@c046a42c-6fe2-441c-8c8c-71466251a162",
    "time": "Sun Dec 07 19:20:43 2008 +0000"
  },
  "committer": {
    "name": "balrog",
    "email": "balrog@c046a42c-6fe2-441c-8c8c-71466251a162",
    "time": "Sun Dec 07 19:20:43 2008 +0000"
  },
  "message": "SH: r2d pci support (Takashi YOSHII).\n\nThis patch adds pci support to sh/r2d board.\nThis is the first user of PCIC support I formerly sent.\n\nPCIC actually is inside of chip with CPU core on SH7751.\nBut, this code is written as if SH7750 and PCIC are on board.\nI care little about physical device boundary, but fitting with qemu\u0027s\ndesign.\n\nThis patch also adds some BSC (Bus State Controller) registers,\nbecause PCI device driver software have to accesses them.\n\nSigned-off-by: Takashi YOSHII \u003ctakasi-y@ops.dti.ne.jp\u003e\nSigned-off-by: Andrzej Zaborowski \u003candrew.zaborowski@intel.com\u003e\n\n\ngit-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5932 c046a42c-6fe2-441c-8c8c-71466251a162\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ae289be0863a501071010c417c119e3029c52bcf",
      "old_mode": 33188,
      "old_path": "hw/r2d.c",
      "new_id": "78fc1979402fbde746f5bf55bea32fb89e771620",
      "new_mode": 33188,
      "new_path": "hw/r2d.c"
    },
    {
      "type": "modify",
      "old_id": "97597fc54a5afb851a78f78fdbbd6d083dea3b1d",
      "old_mode": 33188,
      "old_path": "hw/sh7750.c",
      "new_id": "a564a802d6c3d1ec083afbe7831b0ac7af967cce",
      "new_mode": 33188,
      "new_path": "hw/sh7750.c"
    }
  ]
}