commit c5fad12fa08228d0c2f04089ba0cd27718f1b723
author Peter Maydell <peter.maydell@linaro.org> Fri Apr 20 07:39:15 2012 +0000
committer Peter Maydell <peter.maydell@linaro.org> Fri Apr 27 11:06:18 2012 +0000
tree 11ae7d19c76bda0b22e0aed311546c5a0cd576e3
parent 778c3a0619f3b47f94e566ca4f656aabe5f4b3d6

target-arm: Move A9 config_base_address reset value to ARMCPU

Move the A9 config_base_address cp15 register reset value to
ARMCPU. This should become a QOM property so that the Highbank
board can set it without having to pull in cpu-qom.h, but at
least this avoids the implicit dependency on reset ordering
that the previous workaround had.

Cc: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Andreas Färber <afaerber@suse.de>

hw/highbank.c

diff --git a/hw/highbank.c b/hw/highbank.c
index 906eed5..4d6d728 100644
--- a/hw/highbank.c
+++ b/hw/highbank.c
@@ -35,12 +35,6 @@
 #define NIRQ_GIC      160
 
 /* Board init.  */
-static void highbank_cpu_reset(void *opaque)
-{
-    CPUARMState *env = opaque;
-
-    env->cp15.c15_config_base_address = GIC_BASE_ADDR;
-}
 
 static void hb_write_secondary(CPUARMState *env, const struct arm_boot_info *info)
 {
@@ -213,14 +207,17 @@
     }
 
     for (n = 0; n < smp_cpus; n++) {
-        env = cpu_init(cpu_model);
-        if (!env) {
+        ARMCPU *cpu;
+        cpu = cpu_arm_init(cpu_model);
+        if (cpu == NULL) {
             fprintf(stderr, "Unable to find CPU definition\n");
             exit(1);
         }
+        env = &cpu->env;
+        /* This will become a QOM property eventually */
+        cpu->reset_cbar = GIC_BASE_ADDR;
         irqp = arm_pic_init_cpu(env);
         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
-        qemu_register_reset(highbank_cpu_reset, env);
     }
 
     sysmem = get_system_memory();

target-arm/cpu-qom.h

diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h
index 2891521..a61c68d 100644
--- a/target-arm/cpu-qom.h
+++ b/target-arm/cpu-qom.h
@@ -93,6 +93,7 @@
      * in the order L1DCache, L1ICache, L2DCache, L2ICache, etc.
      */
     uint32_t ccsidr[16];
+    uint32_t reset_cbar;
 } ARMCPU;
 
 static inline ARMCPU *arm_env_get_cpu(CPUARMState *env)

target-arm/cpu.c

diff --git a/target-arm/cpu.c b/target-arm/cpu.c
index 2e0eccd..7eb323a 100644
--- a/target-arm/cpu.c
+++ b/target-arm/cpu.c
@@ -30,7 +30,6 @@
     ARMCPU *cpu = ARM_CPU(s);
     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
     CPUARMState *env = &cpu->env;
-    uint32_t tmp = 0;
 
     if (qemu_loglevel_mask(CPU_LOG_RESET)) {
         qemu_log("CPU Reset (CPU %d)\n", env->cpu_index);
@@ -39,9 +38,8 @@
 
     acc->parent_reset(s);
 
-    tmp = env->cp15.c15_config_base_address;
     memset(env, 0, offsetof(CPUARMState, breakpoints));
-    env->cp15.c15_config_base_address = tmp;
+    env->cp15.c15_config_base_address = cpu->reset_cbar;
     env->cp15.c0_cpuid = cpu->midr;
     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;