)]}'
{
  "commit": "cb2e37dffaab38e962b86b3ca6f4cf0de22d9e69",
  "tree": "685dc1a65445a8b3d3ce6ec1af4f09f096433fed",
  "parents": [
    "5ebafdf31a22069952cd6c4f4e60df1cb6a6a22e"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Wed Feb 26 17:20:04 2014 +0000"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Wed Feb 26 17:20:04 2014 +0000"
  },
  "message": "target-arm: Implement AArch64 TCR_EL1\n\nImplement the AArch64 TCR_EL1, which is the 64 bit view of\nthe AArch32 TTBCR. (The uses of the bits in the register are\ncompletely different, but in any given situation the CPU will\nalways interpret them one way or the other. In fact for QEMU EL1\nis always 64 bit, but we share the state field because this\nis the correct mapping to permit a future implementation of EL2.)\nWe also make the AArch64 view the \u0027master\u0027 as far as migration\nand reset is concerned.\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Peter Crosthwaite \u003cpeter.crosthwaite@xilinx.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "74b1122927d2971434af455a312f102b77e28d6a",
      "old_mode": 33188,
      "old_path": "target-arm/cpu.h",
      "new_id": "4e87064920bab0aa97eb14b5bc0d7dacd85271e4",
      "new_mode": 33188,
      "new_path": "target-arm/cpu.h"
    },
    {
      "type": "modify",
      "old_id": "630ace98e9f1816bcb4b9c0d3dbc39c69d08f16c",
      "old_mode": 33188,
      "old_path": "target-arm/helper.c",
      "new_id": "7f76e0b97469fc401cb3d8c0d8704b0f7124374a",
      "new_mode": 33188,
      "new_path": "target-arm/helper.c"
    }
  ]
}