)]}'
{
  "commit": "d2ea2bf740c515de41f45e4d6f36683db3458881",
  "tree": "ad7e50ba8cda7d373f831e95ec56842c41ac46c7",
  "parents": [
    "deb05c4c4c2b7bfeccddb8494164cc858a8652ec"
  ],
  "author": {
    "name": "Alexander Graf",
    "email": "agraf@suse.de",
    "time": "Sun Jan 19 17:47:43 2014 +0100"
  },
  "committer": {
    "name": "Alexander Graf",
    "email": "agraf@suse.de",
    "time": "Mon Jun 16 13:24:34 2014 +0200"
  },
  "message": "PPC: Add L1CFG1 SPR emulation\n\nIn addition to the L1 data cache configuration register L1CFG0 there is\nalso another one for the L1 instruction cache called L1CFG1.\n\nEmulate that one with the same values as the data one.\n\nSigned-off-by: Alexander Graf \u003cagraf@suse.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "178fc55689d418b2fd8f343ad3e3ca41bb8e8ac2",
      "old_mode": 33188,
      "old_path": "target-ppc/cpu.h",
      "new_id": "f36c90b47b825397b27301829cc40cd35ab8006d",
      "new_mode": 33188,
      "new_path": "target-ppc/cpu.h"
    },
    {
      "type": "modify",
      "old_id": "07f723da065e157f6eb33853af89e07b2981e72a",
      "old_mode": 33188,
      "old_path": "target-ppc/translate_init.c",
      "new_id": "fc9d9322689203f76448309ac5675f2408ab187c",
      "new_mode": 33188,
      "new_path": "target-ppc/translate_init.c"
    }
  ]
}