)]}'
{
  "commit": "d3afacc7269fee45d54d1501a46b51f12ea7bb15",
  "tree": "5f69a235709ecfb8fc57becf869c604ba4184512",
  "parents": [
    "f6fe04d566f1a1e3219b501487cd2d2d00d723a5"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Mon Jun 09 15:43:26 2014 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Mon Jun 09 16:06:12 2014 +0100"
  },
  "message": "target-arm: Fix errors in writes to generic timer control registers\n\nThe code for handling writes to the generic timer control registers\nhad several bugs:\n * ISTATUS (bit 2) is read-only but we forced it to zero on any write\n * the check for \"was IMASK (bit 1) toggled?\" incorrectly used \u0027\u0026\u0027 where\n   it should be \u0027^\u0027\n * the handling of IMASK was inverted: we should set the IRQ if\n   ISTATUS is set and IMASK is clear, not if both are set\n\nThe combination of these bugs meant that when running a Linux guest\nthat uses the generic timers we would fairly quickly end up either\nforgetting that the timer output should be asserted, or failing to\nset the IRQ when the timer was unmasked. The result is that the guest\nnever gets any more timer interrupts.\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nMessage-id: 1401803208-1281-1-git-send-email-peter.maydell@linaro.org\nCc: qemu-stable@nongnu.org\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "177ed076c7d6e8a6c71117802c8dd7b83f2e84a6",
      "old_mode": 33188,
      "old_path": "target-arm/helper.c",
      "new_id": "050c40981b21e40a7cf5d4ee5fc4f6f65fe294a5",
      "new_mode": 33188,
      "new_path": "target-arm/helper.c"
    }
  ]
}