tree 5c11026b1c413633ef2c4ce567ba274089d322ec
parent 4dc89b782095d7a0b919fafd7b1322b3cb1279f1
author Yongbok Kim <yongbok.kim@imgtec.com> 1435675468 +0100
committer Leon Alrae <leon.alrae@imgtec.com> 1436965637 +0100

target-mips: fix to clear MSACSR.Cause

MSACSR.Cause bits are needed to be cleared before a vector floating-point
instructions.
FEXDO.df, FEXUPL.df and FEXUPR.df were missed out.

Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Leon Alrae <leon.alrae@imgtec.com>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>