)]}'
{
  "commit": "d54a299b83a07642c85a22bfe19b69ca4def9ec4",
  "tree": "e81c778717e27d4ee9525482136669666f7daa70",
  "parents": [
    "db77d8523909b32d798cd2c80de422b68f9e5c42"
  ],
  "author": {
    "name": "Leon Alrae",
    "email": "leon.alrae@imgtec.com",
    "time": "Wed Sep 09 12:44:25 2015 +0100"
  },
  "committer": {
    "name": "Leon Alrae",
    "email": "leon.alrae@imgtec.com",
    "time": "Fri Sep 18 09:20:48 2015 +0100"
  },
  "message": "target-mips: correct MTC0 instruction on MIPS64\n\nMTC0 on a 64-bit processor should move entire 64-bit GPR content to CP0\nregister.\n\nSigned-off-by: Leon Alrae \u003cleon.alrae@imgtec.com\u003e\nReviewed-by: Aurelien Jarno \u003caurelien@aurel32.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "0883782b8ca32789e79cf6672f34ba1a509e52b6",
      "old_mode": 33188,
      "old_path": "target-mips/translate.c",
      "new_id": "a59b6704a19d7c9f0297c823b009a7b7ce2b8bd3",
      "new_mode": 33188,
      "new_path": "target-mips/translate.c"
    }
  ]
}