tree e81c778717e27d4ee9525482136669666f7daa70
parent db77d8523909b32d798cd2c80de422b68f9e5c42
author Leon Alrae <leon.alrae@imgtec.com> 1441799065 +0100
committer Leon Alrae <leon.alrae@imgtec.com> 1442564448 +0100

target-mips: correct MTC0 instruction on MIPS64

MTC0 on a 64-bit processor should move entire 64-bit GPR content to CP0
register.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>