)]}'
{
  "commit": "d5f27e88699f14c802d66c01de70e5ea37b7153a",
  "tree": "da582facc57bb95559af831af30b11f95de327aa",
  "parents": [
    "c9f50cea70a15967daec9bf48fed37eafefdd584"
  ],
  "author": {
    "name": "Michael S. Tsirkin",
    "email": "mst@redhat.com",
    "time": "Tue Feb 21 15:57:58 2012 +0200"
  },
  "committer": {
    "name": "Anthony Liguori",
    "email": "aliguori@us.ibm.com",
    "time": "Wed Feb 22 09:02:18 2012 -0600"
  },
  "message": "pci: set memory type for memory behind the bridge\n\nAs we make upper bits in IO and prefetcheable memory\nregisters writeable, we should declare support\nfor 64 bit prefetcheable memory and 32 bit io\nin the bridge.\n\nThis changes the default for apb, dec, but I\u0027m guessing\nthey got the defaults wrong by accident.\nAlternatively, we could let bridges declare lack of\n64 bit support and make the upper bits read-only zero.\n\nWith this applied, we can drop these bits\nfrom express code.\n\nReported-by: Gerd Hoffmann \u003ckraxel@redhat.com\u003e\nSigned-off-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\n\nCould someone familiar with apb,dec ack this please?\nSigned-off-by: Anthony Liguori \u003caliguori@us.ibm.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "678a8c11173496b923a37ab8a9885b3101abee35",
      "old_mode": 33188,
      "old_path": "hw/pci.c",
      "new_id": "bf046bfcad7beb734a5f584cdad07633e8c87789",
      "new_mode": 33188,
      "new_path": "hw/pci.c"
    }
  ]
}