commit e04bcc691b54cb680138e3aa6e583c82c91cfca2
author ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> Sat Apr 07 01:10:22 2007 +0000
committer ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> Sat Apr 07 01:10:22 2007 +0000
tree 2b89dca901159022c81786fa3ead346f870d2b86
parent f757d6ff29128dd0a09e02299306be22fa38821e

Actually skip over delay slot for a non-taken branch likely.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2628 c046a42c-6fe2-441c-8c8c-71466251a162

target-mips/translate.c

diff --git a/target-mips/translate.c b/target-mips/translate.c
index f3b2de4..c646f7f 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -1530,14 +1530,14 @@
         case OPC_BLTZALL: /* 0 < 0 likely */
             gen_op_set_T0(ctx->pc + 8);
             gen_op_store_T0_gpr(31);
-            gen_goto_tb(ctx, 0, ctx->pc + 4);
+            gen_goto_tb(ctx, 0, ctx->pc + 8);
             return;
         case OPC_BNEL:    /* rx != rx likely */
         case OPC_BGTZL:   /* 0 > 0 likely */
         case OPC_BLTZL:   /* 0 < 0 likely */
             /* Skip the instruction in the delay slot */
             MIPS_DEBUG("bnever and skip");
-            gen_goto_tb(ctx, 0, ctx->pc + 4);
+            gen_goto_tb(ctx, 0, ctx->pc + 8);
             return;
         case OPC_J:
             ctx->hflags |= MIPS_HFLAG_B;