)]}'
{
  "commit": "e33d22fab3ad64bedc1c9addb0a0fa437995c12a",
  "tree": "01afe4144118e2761e51ee7aea96a2dd54d6c7cc",
  "parents": [
    "27fa7479801ac23609110535a997b2e3ed6eb867"
  ],
  "author": {
    "name": "Eduardo Habkost",
    "email": "ehabkost@redhat.com",
    "time": "Fri Aug 07 16:15:31 2015 -0300"
  },
  "committer": {
    "name": "Michael S. Tsirkin",
    "email": "mst@redhat.com",
    "time": "Thu Aug 13 14:08:25 2015 +0300"
  },
  "message": "piix: Document coreboot-specific RAM size config register\n\nThe existing i440fx initialization code sets a PCI config register that\nisn\u0027t documented anywhere in the Intel 440FX datasheet. Register 0x57 is\nDRAMC (DRAM Control) and has nothing to do with the RAM size.\n\nThis was implemented in commit ec5f92ce6ac8ec09056be77e03c941be188648fa\nbecause old coreboot code tried to read registers 0x5a-0x5f,0x56,0x57 to\nget the RAM size from QEMU, but I couldn\u0027t find out why coreboot did\nthat. I assume it was a mistake, and the original code was supposed to\nbe reading the DRB[0-7] registers (offsets 0x60-0x67).\n\nDocument that coreboot-specific register offset in a macro and a\ncomment, for future reference.\n\nCc: Ed Swierk \u003ceswierk@skyportsystems.com\u003e\nCc: Richard Smith \u003csmithbone@gmail.com\u003e\nSigned-off-by: Eduardo Habkost \u003cehabkost@redhat.com\u003e\nReviewed-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\nSigned-off-by: Michael S. Tsirkin \u003cmst@redhat.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ad55f996639c5f5062ec8f1698869dba752af902",
      "old_mode": 33188,
      "old_path": "hw/pci-host/piix.c",
      "new_id": "1cb25f3fa69abdeafd4baf0b0f8fc20d0c491e08",
      "new_mode": 33188,
      "new_path": "hw/pci-host/piix.c"
    }
  ]
}