)]}'
{
  "commit": "e35310260ec57d20301c65a5714ca55369e971cc",
  "tree": "823e928135fa03a39d030cdc26dc0124e6be0032",
  "parents": [
    "ee804264ddc4d3cd36a5183a09847e391da0fc66"
  ],
  "author": {
    "name": "Peter Crosthwaite",
    "email": "peter.crosthwaite@xilinx.com",
    "time": "Thu May 14 19:22:55 2015 -0700"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Mon May 18 16:41:08 2015 +0100"
  },
  "message": "target-arm: cpu64: Add support for Cortex-A53\n\nAdd the ARM Cortex-A53 processor definition. Similar to A57, but with\ndifferent L1 I cache policy, phys addr size and different cache\ngeometries. The cache sizes is implementation configurable, but use\nthese values (from Xilinx Zynq MPSoC) as a default until cache size\nconfigurability is added.\n\nAcked-by: Edgar E. Iglesias \u003cedgar.iglesias@xilinx.com\u003e\nReviewed-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nSigned-off-by: Peter Crosthwaite \u003cpeter.crosthwaite@xilinx.com\u003e\nMessage-id: db439ff834cf0431bc192b05272a3b28fe2045d0.1431381507.git.peter.crosthwaite@xilinx.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "13e042e3ccee298d12b1c8820bf6aee294d31d5a",
      "old_mode": 33188,
      "old_path": "target-arm/cpu64.c",
      "new_id": "bf7dd685f810810df7598dcdb655ec5b27bcbee6",
      "new_mode": 33188,
      "new_path": "target-arm/cpu64.c"
    }
  ]
}