tree 823e928135fa03a39d030cdc26dc0124e6be0032
parent ee804264ddc4d3cd36a5183a09847e391da0fc66
author Peter Crosthwaite <peter.crosthwaite@xilinx.com> 1431656575 -0700
committer Peter Maydell <peter.maydell@linaro.org> 1431963668 +0100

target-arm: cpu64: Add support for Cortex-A53

Add the ARM Cortex-A53 processor definition. Similar to A57, but with
different L1 I cache policy, phys addr size and different cache
geometries. The cache sizes is implementation configurable, but use
these values (from Xilinx Zynq MPSoC) as a default until cache size
configurability is added.

Acked-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: db439ff834cf0431bc192b05272a3b28fe2045d0.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>