)]}'
{
  "commit": "e9ebfbfcf31c11fb3bd2fc436fa17ce45a4e7086",
  "tree": "ab0870ba7fbecc9765af37768f809ea6c8953ef7",
  "parents": [
    "faacc041619581c566c21ed87aa1933420731282"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Mon Sep 07 10:39:28 2015 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Mon Sep 07 10:39:28 2015 +0100"
  },
  "message": "target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call\n\nThe A64 semihosting ABI defines a new call SyncCacheRange\nfor doing a \u0027clean D-cache and invalidate I-cache\u0027 sequence.\nSince QEMU doesn\u0027t implement caches, we can implement this as a nop.\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\nReviewed-by: Christopher Covington \u003cchristopher.covington@linaro.org\u003e\nTested-by: Christopher Covington \u003ccov@codeaurora.org\u003e\nMessage-id: 1439483745-28752-8-git-send-email-peter.maydell@linaro.org\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1d4cc59e7964dec96fe30d626109310f69aa6feb",
      "old_mode": 33188,
      "old_path": "target-arm/arm-semi.c",
      "new_id": "1d0d7aa32b524672e38d16d5a626d3b3f146c517",
      "new_mode": 33188,
      "new_path": "target-arm/arm-semi.c"
    }
  ]
}