tree ab0870ba7fbecc9765af37768f809ea6c8953ef7
parent faacc041619581c566c21ed87aa1933420731282
author Peter Maydell <peter.maydell@linaro.org> 1441618768 +0100
committer Peter Maydell <peter.maydell@linaro.org> 1441618768 +0100

target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call

The A64 semihosting ABI defines a new call SyncCacheRange
for doing a 'clean D-cache and invalidate I-cache' sequence.
Since QEMU doesn't implement caches, we can implement this as a nop.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christopher Covington <christopher.covington@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-8-git-send-email-peter.maydell@linaro.org