)]}'
{
  "commit": "ead4cf04f855575c24e795d7179d93b1601575b7",
  "tree": "fac4a9f3bffd41359466f37498aef255c51594e3",
  "parents": [
    "f9681f116ce06612b12ef41d8637f6659255ec98"
  ],
  "author": {
    "name": "Mark Cave-Ayland",
    "email": "mark.cave-ayland@ilande.co.uk",
    "time": "Sat Feb 22 22:54:53 2014 +0000"
  },
  "committer": {
    "name": "Mark Cave-Ayland",
    "email": "mark.cave-ayland@ilande.co.uk",
    "time": "Thu Feb 27 10:01:41 2014 +0000"
  },
  "message": "sun4m: fix slavio timer RUN/STOP bit\n\nThe sun4m architecture has one \u0027system\u0027 timer and one timer per CPU.\nThe CPU timers can be configured in two modes:\n\n  * 22 bits Counter/Timer. Periodic interrupts.\n  * 54 bits User timer. For profiling. In this mode, the Run/Stop bit\n    controls the timer.\n\nThe run/stop bit controls the timer only when it is in \"User\" mode, but\nits state shall be persistent.\n\nSigned-off-by: Olivier Danet \u003codanet@caramail.com\u003e\nSigned-off-by: Mark Cave-Ayland \u003cmark.cave-ayland@ilande.co.uk\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f75b91495136f6a613a623c577240e37a5e4c01c",
      "old_mode": 33188,
      "old_path": "hw/timer/slavio_timer.c",
      "new_id": "e4dcceaf237f4c31b0101931145f31fd10bb6443",
      "new_mode": 33188,
      "new_path": "hw/timer/slavio_timer.c"
    }
  ]
}