tree 491fb3380e9687ce8075f5c2d3af783f45d99540
parent f6198371539d07cede52d654657b96eab54f9dce
author aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> 1228930311 +0000
committer aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> 1228930311 +0000

target-sh4: Add SH bit handling to TLB

This patch adds SH bit handling to sh4's TLB, which is a part of MMU
functionality that had not been implemented in qemu.

Additionally, increment_urc() call in cpu_load_tlb() is deleted, because
the specification explicitly says that URC is not incremented by an LDTLB
instruction (at Section 3 of SH7751 Hardware manual(REJ09B0370-0400)).
Even though URC is not needed to be strictly same as HW because it is a
random number, this condition is not negligible.

Signed-off-by: Takashi YOSHII <takasi-y@ops.dti.ne.jp>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5971 c046a42c-6fe2-441c-8c8c-71466251a162