commit ef26ee0e6c67d415f8b22850f9f13a972ada8be1
author malc <av1474@comtv.ru> Wed Nov 02 02:16:34 2011 +0400
committer malc <av1474@comtv.ru> Wed Nov 02 02:16:34 2011 +0400
tree c18a9cc2a9f213c8a37473f9b7aa001a99898547
parent dd7b25b5b47df8aaf5580faaf3f60b2a1b779c37
parent e1c2008af64487e7d3cec615612b7f467ebe9bc8

Merge branch 'master' of git://git.qemu.org/qemu

tcg/tcg-op.h

diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h
index 24ec7fc..82e04e7 100644
--- a/tcg/tcg-op.h
+++ b/tcg/tcg-op.h
@@ -2042,8 +2042,8 @@
 }
 
 static inline void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1,
-				       TCGv_i32 arg2, unsigned int ofs,
-				       unsigned int len)
+                                       TCGv_i32 arg2, unsigned int ofs,
+                                       unsigned int len)
 {
     uint32_t mask;
     TCGv_i32 t1;
@@ -2073,8 +2073,8 @@
 }
 
 static inline void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1,
-				       TCGv_i64 arg2, unsigned int ofs,
-				       unsigned int len)
+                                       TCGv_i64 arg2, unsigned int ofs,
+                                       unsigned int len)
 {
     uint64_t mask;
     TCGv_i64 t1;
@@ -2090,6 +2090,7 @@
 
 #if TCG_TARGET_REG_BITS == 32
     if (ofs >= 32) {
+        tcg_gen_mov_i32(TCGV_LOW(ret), TCGV_LOW(arg1));
         tcg_gen_deposit_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1),
                             TCGV_LOW(arg2), ofs - 32, len);
         return;
@@ -2097,6 +2098,7 @@
     if (ofs + len <= 32) {
         tcg_gen_deposit_i32(TCGV_LOW(ret), TCGV_LOW(arg1),
                             TCGV_LOW(arg2), ofs, len);
+        tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1));
         return;
     }
 #endif