)]}'
{
  "commit": "f0a902f76452211cadbdf1d25ef9b94732b096e8",
  "tree": "6ed7d0f42e8538857fa0a6d3a3418a6cdf5fe0ab",
  "parents": [
    "e35310260ec57d20301c65a5714ca55369e971cc"
  ],
  "author": {
    "name": "Peter Crosthwaite",
    "email": "peter.crosthwaite@xilinx.com",
    "time": "Thu May 14 19:22:58 2015 -0700"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Mon May 18 16:41:09 2015 +0100"
  },
  "message": "arm: Introduce Xilinx ZynqMP SoC\n\nWith quad Cortex-A53 CPUs.\n\nUse SMC PSCI, with the standard policy of secondaries starting in\npower-off.\n\nTested-by: Alistair Francis \u003calistair.francis@xilinx.com\u003e\nReviewed-by: Alistair Francis \u003calistair.francis@xilinx.com\u003e\nReviewed-by: Edgar E. Iglesias \u003cedgar.iglesias@xilinx.com\u003e\nSigned-off-by: Peter Crosthwaite \u003cpeter.crosthwaite@xilinx.com\u003e\nMessage-id: a16202a6c7b79e446e5289d38cb18d2ee4b897a0.1431381507.git.peter.crosthwaite@xilinx.com\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
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