tree 6ed7d0f42e8538857fa0a6d3a3418a6cdf5fe0ab
parent e35310260ec57d20301c65a5714ca55369e971cc
author Peter Crosthwaite <peter.crosthwaite@xilinx.com> 1431656578 -0700
committer Peter Maydell <peter.maydell@linaro.org> 1431963669 +0100

arm: Introduce Xilinx ZynqMP SoC

With quad Cortex-A53 CPUs.

Use SMC PSCI, with the standard policy of secondaries starting in
power-off.

Tested-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Message-id: a16202a6c7b79e446e5289d38cb18d2ee4b897a0.1431381507.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>