)]}'
{
  "commit": "f0aff25570003fc618c47dec36852fc7d80436ee",
  "tree": "8cae884e9624845875a42845a479f9ab2d46adff",
  "parents": [
    "fc37b7a0b0cebe4118d172c4fceb0acc2fa25b4a"
  ],
  "author": {
    "name": "Fabian Aggeler",
    "email": "aggelerf@ethz.ch",
    "time": "Tue May 27 17:09:49 2014 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Tue May 27 17:09:49 2014 +0100"
  },
  "message": "target-arm: implement CPACR register logic for ARMv7\n\nIn ARMv7 the CPACR register allows to control access rights to\ncoprocessor 0-13 interfaces. Bits corresponding to unimplemented\ncoprocessors should be RAZ/WI. Bits ASEDIS, D32DIS, TRCDIS are\nUNK/SBZP if VFP is not implemented and RAO/WI in some cases.\nTreating TRCDIS as RAZ/WI since we neither implement a trace\nmacrocell nor a CP14 interface to the trace macrocell registers.\n\nSince CPACR bits for VFP/Neon access are honoured with the CPACR_FPEN\nbit in the TB flags, flushing the TLB is not necessary anymore.\n\nSigned-off-by: Fabian Aggeler \u003caggelerf@ethz.ch\u003e\nMessage-id: 1400532968-30668-1-git-send-email-aggelerf@ethz.ch\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "417161e21646b940f1bcbfc7fe1b63f28270c4a4",
      "old_mode": 33188,
      "old_path": "target-arm/helper.c",
      "new_id": "cb59f00d54f1eaf0a926cf269a203c0e1f727c90",
      "new_mode": 33188,
      "new_path": "target-arm/helper.c"
    }
  ]
}