tree 0189f8fc433cde6b733bd03897c50cfd9ff835d2
parent 419336a9f934d6a6c7098648bc833137a5db2015
author Peter Crosthwaite <peter.crosthwaite@xilinx.com> 1350275824 +1000
committer Peter Crosthwaite <peter.crosthwaite@xilinx.com> 1351492706 +1000

xilinx_spips: Generalised to model QSPI

Extended the xilinx spips controller to model QSPI as well. Paremeterised the
operational difference with the normal spi controller (num_ss_bits, width of the
tx/rx fifo heads etc.). Multiple bus functionality is modelled (needed for QSPI
dual parallel mode. LQSPI is modelled.

Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>