)]}'
{
  "commit": "f364515c836fcc7caa1606a8c27edae25f27a6ce",
  "tree": "544c9948fa5c44b81f5642b3290c4cf7753ab6b5",
  "parents": [
    "41e0c701599de298beec6853f9bb055365e51174"
  ],
  "author": {
    "name": "aurel32",
    "email": "aurel32@c046a42c-6fe2-441c-8c8c-71466251a162",
    "time": "Sat Mar 28 22:22:50 2009 +0000"
  },
  "committer": {
    "name": "aurel32",
    "email": "aurel32@c046a42c-6fe2-441c-8c8c-71466251a162",
    "time": "Sat Mar 28 22:22:50 2009 +0000"
  },
  "message": "target-mips: fix FPU in 64-bit mode\n\nTCG does not allow the same memory location to be aliased in two\ndifferent global registers, fpu_fpr32 and fpu_fpr64.\n\nSigned-off-by: Aurelien Jarno \u003caurelien@aurel32.net\u003e\n\ngit-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6915 c046a42c-6fe2-441c-8c8c-71466251a162\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "8dc7976518fa04c2b9ea0e68614752d82f97f936",
      "old_mode": 33188,
      "old_path": "target-mips/translate.c",
      "new_id": "7a3c719e51774391ef61776d163985abf8b57d37",
      "new_mode": 33188,
      "new_path": "target-mips/translate.c"
    }
  ]
}