)]}'
{
  "commit": "fc04a730b7e60f4a62d6260d4eb9c537d1d3643f",
  "tree": "71a0c298ca37f76a7467118aacbc8a38df0edd99",
  "parents": [
    "8611280505119e296757a60711a881341603fa5a",
    "6fdf3282d16e7fb6e798824fb5f4f60c6a73067d"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Tue Sep 08 18:02:36 2015 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Tue Sep 08 18:02:36 2015 +0100"
  },
  "message": "Merge remote-tracking branch \u0027remotes/pmaydell/tags/pull-target-arm-20150908\u0027 into staging\n\ntarget-arm queue:\n * Implement priority handling properly via GICC_APR\n * Enable TZ extensions on the GIC if we\u0027re using them\n * Minor preparatory patches for EL3 support\n * cadence_gem: Correct Marvell PHY SPCFC reset value\n * Support AHCI in ZynqMP\n\n# gpg: Signature made Tue 08 Sep 2015 17:48:33 BST using RSA key ID 14360CDE\n# gpg: Good signature from \"Peter Maydell \u003cpeter.maydell@linaro.org\u003e\"\n# gpg:                 aka \"Peter Maydell \u003cpmaydell@gmail.com\u003e\"\n# gpg:                 aka \"Peter Maydell \u003cpmaydell@chiark.greenend.org.uk\u003e\"\n\n* remotes/pmaydell/tags/pull-target-arm-20150908:\n  xlnx-zynqmp: Connect the sysbus AHCI to ZynqMP\n  xlnx-zynqmp.c: Convert some of the error_propagate() calls to error_abort\n  ahci.c: Don\u0027t assume AHCIState\u0027s parent is AHCIPCIState\n  ahci: Separate the AHCI state structure into the header\n  cadence_gem: Correct Marvell PHY SPCFC reset value\n  target-arm: Add AArch64 access to PAR_EL1\n  target-arm: Correct opc1 for AT_S12Exx\n  target-arm: Log the target EL when taking exceptions\n  target-arm: Fix default_exception_el() function for the case when EL3 is not supported\n  hw/arm/virt: Enable TZ extensions on the GIC if we are using them\n  hw/arm/virt: Default to not providing TrustZone support\n  hw/cpu/{a15mpcore, a9mpcore}: enable TrustZone in GIC if it is enabled in CPUs\n  hw/intc/arm_gic_common: Configure IRQs as NS if doing direct NS kernel boot\n  hw/arm: new interface for devices which need to behave differently for kernel boot\n  qom: Add recursive version of object_child_for_each\n  hw/intc/arm_gic: Actually set the active bits for active interrupts\n  hw/intc/arm_gic: Drop running_irq and last_active arrays\n  hw/intc/arm_gic: Fix handling of GICC_APR\u003cn\u003e, GICC_NSAPR\u003cn\u003e registers\n  hw/intc/arm_gic: Running priority is group priority, not full priority\n  armv7m_nvic: Implement ICSR without using internal GIC state\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": []
}