)]}'
{
  "commit": "fdaad4715ae9e998fd0595bedfb16fdaf0c68ccc",
  "tree": "9bac96cfe44abbd7efa90780c63cbf2965efbfde",
  "parents": [
    "e50bf23438f8f35dcf32f9e720b04e0e969a3215",
    "f42c5c8ec8aa0e15583487ffee62964830751623"
  ],
  "author": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Fri May 02 11:32:00 2014 +0100"
  },
  "committer": {
    "name": "Peter Maydell",
    "email": "peter.maydell@linaro.org",
    "time": "Fri May 02 11:32:00 2014 +0100"
  },
  "message": "Merge remote-tracking branch \u0027remotes/pmaydell/tags/pull-target-arm-20140501\u0027 into staging\n\ntarget-arm queue:\n * implement XScale cache lockdown cp15 ops\n * fix v7M CPUID base register\n * implement WFE and YIELD as yields for A64\n * fix A64 \"BLR LR\"\n * support Cortex-A57 in virt machine model\n * a few other minor AArch64 bugfixes\n\n# gpg: Signature made Thu 01 May 2014 15:42:17 BST using RSA key ID 14360CDE\n# gpg: Good signature from \"Peter Maydell \u003cpeter.maydell@linaro.org\u003e\"\n\n* remotes/pmaydell/tags/pull-target-arm-20140501:\n  hw/arm/virt: Add support for Cortex-A57\n  hw/arm/virt: Put GIC register banks on 64K boundaries\n  hw/arm/virt: Create the GIC ourselves rather than (ab)using a15mpcore_priv\n  target-arm: Correct a comment refering to EL0\n  target-arm: A64: Fix a typo when declaring TLBI ops\n  target-arm: A64: Handle blr lr\n  target-arm: Make vbar_write 64bit friendly on 32bit hosts\n  target-arm: implement WFE/YIELD as a yield for AArch64\n  armv7m_nvic: fix CPUID Base Register\n  target-arm: Implement XScale cache lockdown operations as NOPs\n\nSigned-off-by: Peter Maydell \u003cpeter.maydell@linaro.org\u003e\n",
  "tree_diff": []
}