| /* |
| * PowerPC CPU initialization for qemu. |
| * |
| * Copyright (c) 2003-2007 Jocelyn Mayer |
| * Copyright 2011 Freescale Semiconductor, Inc. |
| * |
| * This library is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU Lesser General Public |
| * License as published by the Free Software Foundation; either |
| * version 2 of the License, or (at your option) any later version. |
| * |
| * This library is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| * Lesser General Public License for more details. |
| * |
| * You should have received a copy of the GNU Lesser General Public |
| * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| */ |
| |
| #include "disas/bfd.h" |
| #include "exec/gdbstub.h" |
| #include <sysemu/kvm.h> |
| #include "kvm_ppc.h" |
| #include "sysemu/arch_init.h" |
| #include "sysemu/cpus.h" |
| #include "cpu-models.h" |
| #include "mmu-hash32.h" |
| #include "mmu-hash64.h" |
| #include "qemu/error-report.h" |
| |
| //#define PPC_DUMP_CPU |
| //#define PPC_DEBUG_SPR |
| //#define PPC_DUMP_SPR_ACCESSES |
| |
| /* For user-mode emulation, we don't emulate any IRQ controller */ |
| #if defined(CONFIG_USER_ONLY) |
| #define PPC_IRQ_INIT_FN(name) \ |
| static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \ |
| { \ |
| } |
| #else |
| #define PPC_IRQ_INIT_FN(name) \ |
| void glue(glue(ppc, name),_irq_init) (CPUPPCState *env); |
| #endif |
| |
| PPC_IRQ_INIT_FN(40x); |
| PPC_IRQ_INIT_FN(6xx); |
| PPC_IRQ_INIT_FN(970); |
| PPC_IRQ_INIT_FN(POWER7); |
| PPC_IRQ_INIT_FN(e500); |
| |
| /* Generic callbacks: |
| * do nothing but store/retrieve spr value |
| */ |
| static void spr_load_dump_spr(int sprn) |
| { |
| #ifdef PPC_DUMP_SPR_ACCESSES |
| TCGv_i32 t0 = tcg_const_i32(sprn); |
| gen_helper_load_dump_spr(cpu_env, t0); |
| tcg_temp_free_i32(t0); |
| #endif |
| } |
| |
| static void spr_read_generic (void *opaque, int gprn, int sprn) |
| { |
| gen_load_spr(cpu_gpr[gprn], sprn); |
| spr_load_dump_spr(sprn); |
| } |
| |
| static void spr_store_dump_spr(int sprn) |
| { |
| #ifdef PPC_DUMP_SPR_ACCESSES |
| TCGv_i32 t0 = tcg_const_i32(sprn); |
| gen_helper_store_dump_spr(cpu_env, t0); |
| tcg_temp_free_i32(t0); |
| #endif |
| } |
| |
| static void spr_write_generic (void *opaque, int sprn, int gprn) |
| { |
| gen_store_spr(sprn, cpu_gpr[gprn]); |
| spr_store_dump_spr(sprn); |
| } |
| |
| #if !defined(CONFIG_USER_ONLY) |
| static void spr_write_generic32(void *opaque, int sprn, int gprn) |
| { |
| #ifdef TARGET_PPC64 |
| TCGv t0 = tcg_temp_new(); |
| tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]); |
| gen_store_spr(sprn, t0); |
| tcg_temp_free(t0); |
| spr_store_dump_spr(sprn); |
| #else |
| spr_write_generic(opaque, sprn, gprn); |
| #endif |
| } |
| |
| static void spr_write_clear (void *opaque, int sprn, int gprn) |
| { |
| TCGv t0 = tcg_temp_new(); |
| TCGv t1 = tcg_temp_new(); |
| gen_load_spr(t0, sprn); |
| tcg_gen_neg_tl(t1, cpu_gpr[gprn]); |
| tcg_gen_and_tl(t0, t0, t1); |
| gen_store_spr(sprn, t0); |
| tcg_temp_free(t0); |
| tcg_temp_free(t1); |
| } |
| |
| static void spr_access_nop(void *opaque, int sprn, int gprn) |
| { |
| } |
| |
| #endif |
| |
| /* SPR common to all PowerPC */ |
| /* XER */ |
| static void spr_read_xer (void *opaque, int gprn, int sprn) |
| { |
| gen_read_xer(cpu_gpr[gprn]); |
| } |
| |
| static void spr_write_xer (void *opaque, int sprn, int gprn) |
| { |
| gen_write_xer(cpu_gpr[gprn]); |
| } |
| |
| /* LR */ |
| static void spr_read_lr (void *opaque, int gprn, int sprn) |
| { |
| tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr); |
| } |
| |
| static void spr_write_lr (void *opaque, int sprn, int gprn) |
| { |
| tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); |
| } |
| |
| /* CFAR */ |
| #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) |
| static void spr_read_cfar (void *opaque, int gprn, int sprn) |
| { |
| tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); |
| } |
| |
| static void spr_write_cfar (void *opaque, int sprn, int gprn) |
| { |
| tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); |
| } |
| #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ |
| |
| /* CTR */ |
| static void spr_read_ctr (void *opaque, int gprn, int sprn) |
| { |
| tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr); |
| } |
| |
| static void spr_write_ctr (void *opaque, int sprn, int gprn) |
| { |
| tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]); |
| } |
| |
| /* User read access to SPR */ |
| /* USPRx */ |
| /* UMMCRx */ |
| /* UPMCx */ |
| /* USIA */ |
| /* UDECR */ |
| static void spr_read_ureg (void *opaque, int gprn, int sprn) |
| { |
| gen_load_spr(cpu_gpr[gprn], sprn + 0x10); |
| } |
| |
| /* SPR common to all non-embedded PowerPC */ |
| /* DECR */ |
| #if !defined(CONFIG_USER_ONLY) |
| static void spr_read_decr (void *opaque, int gprn, int sprn) |
| { |
| if (use_icount) { |
| gen_io_start(); |
| } |
| gen_helper_load_decr(cpu_gpr[gprn], cpu_env); |
| if (use_icount) { |
| gen_io_end(); |
| gen_stop_exception(opaque); |
| } |
| } |
| |
| static void spr_write_decr (void *opaque, int sprn, int gprn) |
| { |
| if (use_icount) { |
| gen_io_start(); |
| } |
| gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); |
| if (use_icount) { |
| gen_io_end(); |
| gen_stop_exception(opaque); |
| } |
| } |
| #endif |
| |
| /* SPR common to all non-embedded PowerPC, except 601 */ |
| /* Time base */ |
| static void spr_read_tbl (void *opaque, int gprn, int sprn) |
| { |
| if (use_icount) { |
| gen_io_start(); |
| } |
| gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); |
| if (use_icount) { |
| gen_io_end(); |
| gen_stop_exception(opaque); |
| } |
| } |
| |
| static void spr_read_tbu (void *opaque, int gprn, int sprn) |
| { |
| if (use_icount) { |
| gen_io_start(); |
| } |
| gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); |
| if (use_icount) { |
| gen_io_end(); |
| gen_stop_exception(opaque); |
| } |
| } |
| |
| __attribute__ (( unused )) |
| static void spr_read_atbl (void *opaque, int gprn, int sprn) |
| { |
| gen_helper_load_atbl(cpu_gpr[gprn], cpu_env); |
| } |
| |
| __attribute__ (( unused )) |
| static void spr_read_atbu (void *opaque, int gprn, int sprn) |
| { |
| gen_helper_load_atbu(cpu_gpr[gprn], cpu_env); |
| } |
| |
| #if !defined(CONFIG_USER_ONLY) |
| static void spr_write_tbl (void *opaque, int sprn, int gprn) |
| { |
| if (use_icount) { |
| gen_io_start(); |
| } |
| gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); |
| if (use_icount) { |
| gen_io_end(); |
| gen_stop_exception(opaque); |
| } |
| } |
| |
| static void spr_write_tbu (void *opaque, int sprn, int gprn) |
| { |
| if (use_icount) { |
| gen_io_start(); |
| } |
| gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); |
| if (use_icount) { |
| gen_io_end(); |
| gen_stop_exception(opaque); |
| } |
| } |
| |
| __attribute__ (( unused )) |
| static void spr_write_atbl (void *opaque, int sprn, int gprn) |
| { |
| gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]); |
| } |
| |
| __attribute__ (( unused )) |
| static void spr_write_atbu (void *opaque, int sprn, int gprn) |
| { |
| gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]); |
| } |
| |
| #if defined(TARGET_PPC64) |
| __attribute__ (( unused )) |
| static void spr_read_purr (void *opaque, int gprn, int sprn) |
| { |
| gen_helper_load_purr(cpu_gpr[gprn], cpu_env); |
| } |
| #endif |
| #endif |
| |
| #if !defined(CONFIG_USER_ONLY) |
| /* IBAT0U...IBAT0U */ |
| /* IBAT0L...IBAT7L */ |
| static void spr_read_ibat (void *opaque, int gprn, int sprn) |
| { |
| tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); |
| } |
| |
| static void spr_read_ibat_h (void *opaque, int gprn, int sprn) |
| { |
| tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2])); |
| } |
| |
| static void spr_write_ibatu (void *opaque, int sprn, int gprn) |
| { |
| TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
| gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); |
| tcg_temp_free_i32(t0); |
| } |
| |
| static void spr_write_ibatu_h (void *opaque, int sprn, int gprn) |
| { |
| TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4); |
| gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]); |
| tcg_temp_free_i32(t0); |
| } |
| |
| static void spr_write_ibatl (void *opaque, int sprn, int gprn) |
| { |
| TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2); |
| gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); |
| tcg_temp_free_i32(t0); |
| } |
| |
| static void spr_write_ibatl_h (void *opaque, int sprn, int gprn) |
| { |
| TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4); |
| gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]); |
| tcg_temp_free_i32(t0); |
| } |
| |
| /* DBAT0U...DBAT7U */ |
| /* DBAT0L...DBAT7L */ |
| static void spr_read_dbat (void *opaque, int gprn, int sprn) |
| { |
| tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2])); |
| } |
| |
| static void spr_read_dbat_h (void *opaque, int gprn, int sprn) |
| { |
| tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4])); |
| } |
| |
| static void spr_write_dbatu (void *opaque, int sprn, int gprn) |
| { |
| TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2); |
| gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); |
| tcg_temp_free_i32(t0); |
| } |
| |
| static void spr_write_dbatu_h (void *opaque, int sprn, int gprn) |
| { |
| TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4); |
| gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]); |
| tcg_temp_free_i32(t0); |
| } |
| |
| static void spr_write_dbatl (void *opaque, int sprn, int gprn) |
| { |
| TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2); |
| gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); |
| tcg_temp_free_i32(t0); |
| } |
| |
| static void spr_write_dbatl_h (void *opaque, int sprn, int gprn) |
| { |
| TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4); |
| gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]); |
| tcg_temp_free_i32(t0); |
| } |
| |
| /* SDR1 */ |
| static void spr_write_sdr1 (void *opaque, int sprn, int gprn) |
| { |
| gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]); |
| } |
| |
| /* 64 bits PowerPC specific SPRs */ |
| #if defined(TARGET_PPC64) |
| static void spr_read_hior (void *opaque, int gprn, int sprn) |
| { |
| tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix)); |
| } |
| |
| static void spr_write_hior (void *opaque, int sprn, int gprn) |
| { |
| TCGv t0 = tcg_temp_new(); |
| tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL); |
| tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); |
| tcg_temp_free(t0); |
| } |
| #endif |
| #endif |
| |
| /* PowerPC 601 specific registers */ |
| /* RTC */ |
| static void spr_read_601_rtcl (void *opaque, int gprn, int sprn) |
| { |
| gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env); |
| } |
| |
| static void spr_read_601_rtcu (void *opaque, int gprn, int sprn) |
| { |
| gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env); |
| } |
| |
| #if !defined(CONFIG_USER_ONLY) |
| static void spr_write_601_rtcu (void *opaque, int sprn, int gprn) |
| { |
| gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]); |
| } |
| |
| static void spr_write_601_rtcl (void *opaque, int sprn, int gprn) |
| { |
| gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]); |
| } |
| |
| static void spr_write_hid0_601 (void *opaque, int sprn, int gprn) |
| { |
| DisasContext *ctx = opaque; |
| |
| gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]); |
| /* Must stop the translation as endianness may have changed */ |
| gen_stop_exception(ctx); |
| } |
| #endif |
| |
| /* Unified bats */ |
| #if !defined(CONFIG_USER_ONLY) |
| static void spr_read_601_ubat (void *opaque, int gprn, int sprn) |
| { |
| tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2])); |
| } |
| |
| static void spr_write_601_ubatu (void *opaque, int sprn, int gprn) |
| { |
| TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
| gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]); |
| tcg_temp_free_i32(t0); |
| } |
| |
| static void spr_write_601_ubatl (void *opaque, int sprn, int gprn) |
| { |
| TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2); |
| gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]); |
| tcg_temp_free_i32(t0); |
| } |
| #endif |
| |
| /* PowerPC 40x specific registers */ |
| #if !defined(CONFIG_USER_ONLY) |
| static void spr_read_40x_pit (void *opaque, int gprn, int sprn) |
| { |
| gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); |
| } |
| |
| static void spr_write_40x_pit (void *opaque, int sprn, int gprn) |
| { |
| gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); |
| } |
| |
| static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn) |
| { |
| DisasContext *ctx = opaque; |
| |
| gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); |
| /* We must stop translation as we may have rebooted */ |
| gen_stop_exception(ctx); |
| } |
| |
| static void spr_write_40x_sler (void *opaque, int sprn, int gprn) |
| { |
| gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); |
| } |
| |
| static void spr_write_booke_tcr (void *opaque, int sprn, int gprn) |
| { |
| gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); |
| } |
| |
| static void spr_write_booke_tsr (void *opaque, int sprn, int gprn) |
| { |
| gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); |
| } |
| #endif |
| |
| /* PowerPC 403 specific registers */ |
| /* PBL1 / PBU1 / PBL2 / PBU2 */ |
| #if !defined(CONFIG_USER_ONLY) |
| static void spr_read_403_pbr (void *opaque, int gprn, int sprn) |
| { |
| tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1])); |
| } |
| |
| static void spr_write_403_pbr (void *opaque, int sprn, int gprn) |
| { |
| TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1); |
| gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]); |
| tcg_temp_free_i32(t0); |
| } |
| |
| static void spr_write_pir (void *opaque, int sprn, int gprn) |
| { |
| TCGv t0 = tcg_temp_new(); |
| tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF); |
| gen_store_spr(SPR_PIR, t0); |
| tcg_temp_free(t0); |
| } |
| #endif |
| |
| /* SPE specific registers */ |
| static void spr_read_spefscr (void *opaque, int gprn, int sprn) |
| { |
| TCGv_i32 t0 = tcg_temp_new_i32(); |
| tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); |
| tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0); |
| tcg_temp_free_i32(t0); |
| } |
| |
| static void spr_write_spefscr (void *opaque, int sprn, int gprn) |
| { |
| TCGv_i32 t0 = tcg_temp_new_i32(); |
| tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]); |
| tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr)); |
| tcg_temp_free_i32(t0); |
| } |
| |
| #if !defined(CONFIG_USER_ONLY) |
| /* Callback used to write the exception vector base */ |
| static void spr_write_excp_prefix (void *opaque, int sprn, int gprn) |
| { |
| TCGv t0 = tcg_temp_new(); |
| tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask)); |
| tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); |
| tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix)); |
| gen_store_spr(sprn, t0); |
| tcg_temp_free(t0); |
| } |
| |
| static void spr_write_excp_vector (void *opaque, int sprn, int gprn) |
| { |
| DisasContext *ctx = opaque; |
| int sprn_offs; |
| |
| if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) { |
| sprn_offs = sprn - SPR_BOOKE_IVOR0; |
| } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) { |
| sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32; |
| } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) { |
| sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38; |
| } else { |
| printf("Trying to write an unknown exception vector %d %03x\n", |
| sprn, sprn); |
| gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG); |
| return; |
| } |
| |
| TCGv t0 = tcg_temp_new(); |
| tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask)); |
| tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); |
| tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs])); |
| gen_store_spr(sprn, t0); |
| tcg_temp_free(t0); |
| } |
| #endif |
| |
| static inline void vscr_init (CPUPPCState *env, uint32_t val) |
| { |
| env->vscr = val; |
| /* Altivec always uses round-to-nearest */ |
| set_float_rounding_mode(float_round_nearest_even, &env->vec_status); |
| set_flush_to_zero(vscr_nj, &env->vec_status); |
| } |
| |
| #ifdef CONFIG_USER_ONLY |
| #define spr_register_kvm(env, num, name, uea_read, uea_write, \ |
| oea_read, oea_write, one_reg_id, initial_value) \ |
| _spr_register(env, num, name, uea_read, uea_write, initial_value) |
| #else |
| #if !defined(CONFIG_KVM) |
| #define spr_register_kvm(env, num, name, uea_read, uea_write, \ |
| oea_read, oea_write, one_reg_id, initial_value) \ |
| _spr_register(env, num, name, uea_read, uea_write, \ |
| oea_read, oea_write, initial_value) |
| #else |
| #define spr_register_kvm(env, num, name, uea_read, uea_write, \ |
| oea_read, oea_write, one_reg_id, initial_value) \ |
| _spr_register(env, num, name, uea_read, uea_write, \ |
| oea_read, oea_write, one_reg_id, initial_value) |
| #endif |
| #endif |
| |
| #define spr_register(env, num, name, uea_read, uea_write, \ |
| oea_read, oea_write, initial_value) \ |
| spr_register_kvm(env, num, name, uea_read, uea_write, \ |
| oea_read, oea_write, 0, initial_value) |
| |
| static inline void _spr_register(CPUPPCState *env, int num, |
| const char *name, |
| void (*uea_read)(void *opaque, int gprn, int sprn), |
| void (*uea_write)(void *opaque, int sprn, int gprn), |
| #if !defined(CONFIG_USER_ONLY) |
| |
| void (*oea_read)(void *opaque, int gprn, int sprn), |
| void (*oea_write)(void *opaque, int sprn, int gprn), |
| #endif |
| #if defined(CONFIG_KVM) |
| uint64_t one_reg_id, |
| #endif |
| target_ulong initial_value) |
| { |
| ppc_spr_t *spr; |
| |
| spr = &env->spr_cb[num]; |
| if (spr->name != NULL ||env-> spr[num] != 0x00000000 || |
| #if !defined(CONFIG_USER_ONLY) |
| spr->oea_read != NULL || spr->oea_write != NULL || |
| #endif |
| spr->uea_read != NULL || spr->uea_write != NULL) { |
| printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num); |
| exit(1); |
| } |
| #if defined(PPC_DEBUG_SPR) |
| printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num, |
| name, initial_value); |
| #endif |
| spr->name = name; |
| spr->uea_read = uea_read; |
| spr->uea_write = uea_write; |
| #if !defined(CONFIG_USER_ONLY) |
| spr->oea_read = oea_read; |
| spr->oea_write = oea_write; |
| #endif |
| #if defined(CONFIG_KVM) |
| spr->one_reg_id = one_reg_id, |
| #endif |
| env->spr[num] = spr->default_value = initial_value; |
| } |
| |
| /* Generic PowerPC SPRs */ |
| static void gen_spr_generic (CPUPPCState *env) |
| { |
| /* Integer processing */ |
| spr_register(env, SPR_XER, "XER", |
| &spr_read_xer, &spr_write_xer, |
| &spr_read_xer, &spr_write_xer, |
| 0x00000000); |
| /* Branch contol */ |
| spr_register(env, SPR_LR, "LR", |
| &spr_read_lr, &spr_write_lr, |
| &spr_read_lr, &spr_write_lr, |
| 0x00000000); |
| spr_register(env, SPR_CTR, "CTR", |
| &spr_read_ctr, &spr_write_ctr, |
| &spr_read_ctr, &spr_write_ctr, |
| 0x00000000); |
| /* Interrupt processing */ |
| spr_register(env, SPR_SRR0, "SRR0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_SRR1, "SRR1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Processor control */ |
| spr_register(env, SPR_SPRG0, "SPRG0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_SPRG1, "SPRG1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_SPRG2, "SPRG2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_SPRG3, "SPRG3", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| /* SPR common to all non-embedded PowerPC, including 601 */ |
| static void gen_spr_ne_601 (CPUPPCState *env) |
| { |
| /* Exception processing */ |
| spr_register_kvm(env, SPR_DSISR, "DSISR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| KVM_REG_PPC_DSISR, 0x00000000); |
| spr_register_kvm(env, SPR_DAR, "DAR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| KVM_REG_PPC_DAR, 0x00000000); |
| /* Timer */ |
| spr_register(env, SPR_DECR, "DECR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_decr, &spr_write_decr, |
| 0x00000000); |
| /* Memory management */ |
| spr_register(env, SPR_SDR1, "SDR1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_sdr1, |
| 0x00000000); |
| } |
| |
| /* BATs 0-3 */ |
| static void gen_low_BATs (CPUPPCState *env) |
| { |
| #if !defined(CONFIG_USER_ONLY) |
| spr_register(env, SPR_IBAT0U, "IBAT0U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_ibat, &spr_write_ibatu, |
| 0x00000000); |
| spr_register(env, SPR_IBAT0L, "IBAT0L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_ibat, &spr_write_ibatl, |
| 0x00000000); |
| spr_register(env, SPR_IBAT1U, "IBAT1U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_ibat, &spr_write_ibatu, |
| 0x00000000); |
| spr_register(env, SPR_IBAT1L, "IBAT1L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_ibat, &spr_write_ibatl, |
| 0x00000000); |
| spr_register(env, SPR_IBAT2U, "IBAT2U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_ibat, &spr_write_ibatu, |
| 0x00000000); |
| spr_register(env, SPR_IBAT2L, "IBAT2L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_ibat, &spr_write_ibatl, |
| 0x00000000); |
| spr_register(env, SPR_IBAT3U, "IBAT3U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_ibat, &spr_write_ibatu, |
| 0x00000000); |
| spr_register(env, SPR_IBAT3L, "IBAT3L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_ibat, &spr_write_ibatl, |
| 0x00000000); |
| spr_register(env, SPR_DBAT0U, "DBAT0U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_dbat, &spr_write_dbatu, |
| 0x00000000); |
| spr_register(env, SPR_DBAT0L, "DBAT0L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_dbat, &spr_write_dbatl, |
| 0x00000000); |
| spr_register(env, SPR_DBAT1U, "DBAT1U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_dbat, &spr_write_dbatu, |
| 0x00000000); |
| spr_register(env, SPR_DBAT1L, "DBAT1L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_dbat, &spr_write_dbatl, |
| 0x00000000); |
| spr_register(env, SPR_DBAT2U, "DBAT2U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_dbat, &spr_write_dbatu, |
| 0x00000000); |
| spr_register(env, SPR_DBAT2L, "DBAT2L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_dbat, &spr_write_dbatl, |
| 0x00000000); |
| spr_register(env, SPR_DBAT3U, "DBAT3U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_dbat, &spr_write_dbatu, |
| 0x00000000); |
| spr_register(env, SPR_DBAT3L, "DBAT3L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_dbat, &spr_write_dbatl, |
| 0x00000000); |
| env->nb_BATs += 4; |
| #endif |
| } |
| |
| /* BATs 4-7 */ |
| static void gen_high_BATs (CPUPPCState *env) |
| { |
| #if !defined(CONFIG_USER_ONLY) |
| spr_register(env, SPR_IBAT4U, "IBAT4U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_ibat_h, &spr_write_ibatu_h, |
| 0x00000000); |
| spr_register(env, SPR_IBAT4L, "IBAT4L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_ibat_h, &spr_write_ibatl_h, |
| 0x00000000); |
| spr_register(env, SPR_IBAT5U, "IBAT5U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_ibat_h, &spr_write_ibatu_h, |
| 0x00000000); |
| spr_register(env, SPR_IBAT5L, "IBAT5L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_ibat_h, &spr_write_ibatl_h, |
| 0x00000000); |
| spr_register(env, SPR_IBAT6U, "IBAT6U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_ibat_h, &spr_write_ibatu_h, |
| 0x00000000); |
| spr_register(env, SPR_IBAT6L, "IBAT6L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_ibat_h, &spr_write_ibatl_h, |
| 0x00000000); |
| spr_register(env, SPR_IBAT7U, "IBAT7U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_ibat_h, &spr_write_ibatu_h, |
| 0x00000000); |
| spr_register(env, SPR_IBAT7L, "IBAT7L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_ibat_h, &spr_write_ibatl_h, |
| 0x00000000); |
| spr_register(env, SPR_DBAT4U, "DBAT4U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_dbat_h, &spr_write_dbatu_h, |
| 0x00000000); |
| spr_register(env, SPR_DBAT4L, "DBAT4L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_dbat_h, &spr_write_dbatl_h, |
| 0x00000000); |
| spr_register(env, SPR_DBAT5U, "DBAT5U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_dbat_h, &spr_write_dbatu_h, |
| 0x00000000); |
| spr_register(env, SPR_DBAT5L, "DBAT5L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_dbat_h, &spr_write_dbatl_h, |
| 0x00000000); |
| spr_register(env, SPR_DBAT6U, "DBAT6U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_dbat_h, &spr_write_dbatu_h, |
| 0x00000000); |
| spr_register(env, SPR_DBAT6L, "DBAT6L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_dbat_h, &spr_write_dbatl_h, |
| 0x00000000); |
| spr_register(env, SPR_DBAT7U, "DBAT7U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_dbat_h, &spr_write_dbatu_h, |
| 0x00000000); |
| spr_register(env, SPR_DBAT7L, "DBAT7L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_dbat_h, &spr_write_dbatl_h, |
| 0x00000000); |
| env->nb_BATs += 4; |
| #endif |
| } |
| |
| /* Generic PowerPC time base */ |
| static void gen_tbl (CPUPPCState *env) |
| { |
| spr_register(env, SPR_VTBL, "TBL", |
| &spr_read_tbl, SPR_NOACCESS, |
| &spr_read_tbl, SPR_NOACCESS, |
| 0x00000000); |
| spr_register(env, SPR_TBL, "TBL", |
| &spr_read_tbl, SPR_NOACCESS, |
| &spr_read_tbl, &spr_write_tbl, |
| 0x00000000); |
| spr_register(env, SPR_VTBU, "TBU", |
| &spr_read_tbu, SPR_NOACCESS, |
| &spr_read_tbu, SPR_NOACCESS, |
| 0x00000000); |
| spr_register(env, SPR_TBU, "TBU", |
| &spr_read_tbu, SPR_NOACCESS, |
| &spr_read_tbu, &spr_write_tbu, |
| 0x00000000); |
| } |
| |
| /* Softare table search registers */ |
| static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways) |
| { |
| #if !defined(CONFIG_USER_ONLY) |
| env->nb_tlb = nb_tlbs; |
| env->nb_ways = nb_ways; |
| env->id_tlbs = 1; |
| env->tlb_type = TLB_6XX; |
| spr_register(env, SPR_DMISS, "DMISS", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| 0x00000000); |
| spr_register(env, SPR_DCMP, "DCMP", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| 0x00000000); |
| spr_register(env, SPR_HASH1, "HASH1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| 0x00000000); |
| spr_register(env, SPR_HASH2, "HASH2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| 0x00000000); |
| spr_register(env, SPR_IMISS, "IMISS", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| 0x00000000); |
| spr_register(env, SPR_ICMP, "ICMP", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| 0x00000000); |
| spr_register(env, SPR_RPA, "RPA", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| #endif |
| } |
| |
| /* SPR common to MPC755 and G2 */ |
| static void gen_spr_G2_755 (CPUPPCState *env) |
| { |
| /* SGPRs */ |
| spr_register(env, SPR_SPRG4, "SPRG4", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_SPRG5, "SPRG5", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_SPRG6, "SPRG6", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_SPRG7, "SPRG7", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| /* SPR common to all 7xx PowerPC implementations */ |
| static void gen_spr_7xx (CPUPPCState *env) |
| { |
| /* Breakpoints */ |
| /* XXX : not implemented */ |
| spr_register_kvm(env, SPR_DABR, "DABR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| KVM_REG_PPC_DABR, 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_IABR, "IABR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Cache management */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_ICTC, "ICTC", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Performance monitors */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MMCR0, "MMCR0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MMCR1, "MMCR1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_PMC1, "PMC1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_PMC2, "PMC2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_PMC3, "PMC3", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_PMC4, "PMC4", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_SIAR, "SIAR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_UMMCR0, "UMMCR0", |
| &spr_read_ureg, SPR_NOACCESS, |
| &spr_read_ureg, SPR_NOACCESS, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_UMMCR1, "UMMCR1", |
| &spr_read_ureg, SPR_NOACCESS, |
| &spr_read_ureg, SPR_NOACCESS, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_UPMC1, "UPMC1", |
| &spr_read_ureg, SPR_NOACCESS, |
| &spr_read_ureg, SPR_NOACCESS, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_UPMC2, "UPMC2", |
| &spr_read_ureg, SPR_NOACCESS, |
| &spr_read_ureg, SPR_NOACCESS, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_UPMC3, "UPMC3", |
| &spr_read_ureg, SPR_NOACCESS, |
| &spr_read_ureg, SPR_NOACCESS, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_UPMC4, "UPMC4", |
| &spr_read_ureg, SPR_NOACCESS, |
| &spr_read_ureg, SPR_NOACCESS, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_USIAR, "USIAR", |
| &spr_read_ureg, SPR_NOACCESS, |
| &spr_read_ureg, SPR_NOACCESS, |
| 0x00000000); |
| /* External access control */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_EAR, "EAR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| #ifdef TARGET_PPC64 |
| #ifndef CONFIG_USER_ONLY |
| static void spr_read_uamr (void *opaque, int gprn, int sprn) |
| { |
| gen_load_spr(cpu_gpr[gprn], SPR_AMR); |
| spr_load_dump_spr(SPR_AMR); |
| } |
| |
| static void spr_write_uamr (void *opaque, int sprn, int gprn) |
| { |
| gen_store_spr(SPR_AMR, cpu_gpr[gprn]); |
| spr_store_dump_spr(SPR_AMR); |
| } |
| |
| static void spr_write_uamr_pr (void *opaque, int sprn, int gprn) |
| { |
| TCGv t0 = tcg_temp_new(); |
| |
| gen_load_spr(t0, SPR_UAMOR); |
| tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]); |
| gen_store_spr(SPR_AMR, t0); |
| spr_store_dump_spr(SPR_AMR); |
| } |
| #endif /* CONFIG_USER_ONLY */ |
| |
| static void gen_spr_amr (CPUPPCState *env) |
| { |
| #ifndef CONFIG_USER_ONLY |
| /* Virtual Page Class Key protection */ |
| /* The AMR is accessible either via SPR 13 or SPR 29. 13 is |
| * userspace accessible, 29 is privileged. So we only need to set |
| * the kvm ONE_REG id on one of them, we use 29 */ |
| spr_register(env, SPR_UAMR, "UAMR", |
| &spr_read_uamr, &spr_write_uamr_pr, |
| &spr_read_uamr, &spr_write_uamr, |
| 0); |
| spr_register_kvm(env, SPR_AMR, "AMR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| KVM_REG_PPC_AMR, 0); |
| spr_register_kvm(env, SPR_UAMOR, "UAMOR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| KVM_REG_PPC_UAMOR, 0); |
| #endif /* !CONFIG_USER_ONLY */ |
| } |
| #endif /* TARGET_PPC64 */ |
| |
| static void gen_spr_thrm (CPUPPCState *env) |
| { |
| /* Thermal management */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_THRM1, "THRM1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_THRM2, "THRM2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_THRM3, "THRM3", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| /* SPR specific to PowerPC 604 implementation */ |
| static void gen_spr_604 (CPUPPCState *env) |
| { |
| /* Processor identification */ |
| spr_register(env, SPR_PIR, "PIR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_pir, |
| 0x00000000); |
| /* Breakpoints */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_IABR, "IABR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register_kvm(env, SPR_DABR, "DABR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| KVM_REG_PPC_DABR, 0x00000000); |
| /* Performance counters */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MMCR0, "MMCR0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_PMC1, "PMC1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_PMC2, "PMC2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_SIAR, "SIAR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_SDA, "SDA", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| 0x00000000); |
| /* External access control */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_EAR, "EAR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| /* SPR specific to PowerPC 603 implementation */ |
| static void gen_spr_603 (CPUPPCState *env) |
| { |
| /* External access control */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_EAR, "EAR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Breakpoints */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_IABR, "IABR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| |
| } |
| |
| /* SPR specific to PowerPC G2 implementation */ |
| static void gen_spr_G2 (CPUPPCState *env) |
| { |
| /* Memory base address */ |
| /* MBAR */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MBAR, "MBAR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Exception processing */ |
| spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Breakpoints */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_DABR, "DABR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_DABR2, "DABR2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_IABR, "IABR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_IABR2, "IABR2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_IBCR, "IBCR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_DBCR, "DBCR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| /* SPR specific to PowerPC 602 implementation */ |
| static void gen_spr_602 (CPUPPCState *env) |
| { |
| /* ESA registers */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_SER, "SER", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_SEBR, "SEBR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_ESASRR, "ESASRR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Floating point status */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_SP, "SP", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_LT, "LT", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Watchdog timer */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_TCR, "TCR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Interrupt base */ |
| spr_register(env, SPR_IBR, "IBR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_IABR, "IABR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| /* SPR specific to PowerPC 601 implementation */ |
| static void gen_spr_601 (CPUPPCState *env) |
| { |
| /* Multiplication/division register */ |
| /* MQ */ |
| spr_register(env, SPR_MQ, "MQ", |
| &spr_read_generic, &spr_write_generic, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* RTC registers */ |
| spr_register(env, SPR_601_RTCU, "RTCU", |
| SPR_NOACCESS, SPR_NOACCESS, |
| SPR_NOACCESS, &spr_write_601_rtcu, |
| 0x00000000); |
| spr_register(env, SPR_601_VRTCU, "RTCU", |
| &spr_read_601_rtcu, SPR_NOACCESS, |
| &spr_read_601_rtcu, SPR_NOACCESS, |
| 0x00000000); |
| spr_register(env, SPR_601_RTCL, "RTCL", |
| SPR_NOACCESS, SPR_NOACCESS, |
| SPR_NOACCESS, &spr_write_601_rtcl, |
| 0x00000000); |
| spr_register(env, SPR_601_VRTCL, "RTCL", |
| &spr_read_601_rtcl, SPR_NOACCESS, |
| &spr_read_601_rtcl, SPR_NOACCESS, |
| 0x00000000); |
| /* Timer */ |
| #if 0 /* ? */ |
| spr_register(env, SPR_601_UDECR, "UDECR", |
| &spr_read_decr, SPR_NOACCESS, |
| &spr_read_decr, SPR_NOACCESS, |
| 0x00000000); |
| #endif |
| /* External access control */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_EAR, "EAR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Memory management */ |
| #if !defined(CONFIG_USER_ONLY) |
| spr_register(env, SPR_IBAT0U, "IBAT0U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_601_ubat, &spr_write_601_ubatu, |
| 0x00000000); |
| spr_register(env, SPR_IBAT0L, "IBAT0L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_601_ubat, &spr_write_601_ubatl, |
| 0x00000000); |
| spr_register(env, SPR_IBAT1U, "IBAT1U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_601_ubat, &spr_write_601_ubatu, |
| 0x00000000); |
| spr_register(env, SPR_IBAT1L, "IBAT1L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_601_ubat, &spr_write_601_ubatl, |
| 0x00000000); |
| spr_register(env, SPR_IBAT2U, "IBAT2U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_601_ubat, &spr_write_601_ubatu, |
| 0x00000000); |
| spr_register(env, SPR_IBAT2L, "IBAT2L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_601_ubat, &spr_write_601_ubatl, |
| 0x00000000); |
| spr_register(env, SPR_IBAT3U, "IBAT3U", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_601_ubat, &spr_write_601_ubatu, |
| 0x00000000); |
| spr_register(env, SPR_IBAT3L, "IBAT3L", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_601_ubat, &spr_write_601_ubatl, |
| 0x00000000); |
| env->nb_BATs = 4; |
| #endif |
| } |
| |
| static void gen_spr_74xx (CPUPPCState *env) |
| { |
| /* Processor identification */ |
| spr_register(env, SPR_PIR, "PIR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_pir, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MMCR2, "MMCR2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_UMMCR2, "UMMCR2", |
| &spr_read_ureg, SPR_NOACCESS, |
| &spr_read_ureg, SPR_NOACCESS, |
| 0x00000000); |
| /* XXX: not implemented */ |
| spr_register(env, SPR_BAMR, "BAMR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MSSCR0, "MSSCR0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Hardware implementation registers */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_HID0, "HID0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_HID1, "HID1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Altivec */ |
| spr_register(env, SPR_VRSAVE, "VRSAVE", |
| &spr_read_generic, &spr_write_generic, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_L2CR, "L2CR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, spr_access_nop, |
| 0x00000000); |
| /* Not strictly an SPR */ |
| vscr_init(env, 0x00010000); |
| } |
| |
| static void gen_l3_ctrl (CPUPPCState *env) |
| { |
| /* L3CR */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_L3CR, "L3CR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* L3ITCR0 */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_L3ITCR0, "L3ITCR0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* L3PM */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_L3PM, "L3PM", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways) |
| { |
| #if !defined(CONFIG_USER_ONLY) |
| env->nb_tlb = nb_tlbs; |
| env->nb_ways = nb_ways; |
| env->id_tlbs = 1; |
| env->tlb_type = TLB_6XX; |
| /* XXX : not implemented */ |
| spr_register(env, SPR_PTEHI, "PTEHI", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_PTELO, "PTELO", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_TLBMISS, "TLBMISS", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| #endif |
| } |
| |
| #if !defined(CONFIG_USER_ONLY) |
| static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn) |
| { |
| TCGv t0 = tcg_temp_new(); |
| |
| tcg_gen_andi_tl(t0, cpu_gpr[gprn], ~256); |
| gen_store_spr(sprn, t0); |
| tcg_temp_free(t0); |
| } |
| |
| static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn) |
| { |
| TCGv_i32 t0 = tcg_const_i32(sprn); |
| gen_helper_booke206_tlbflush(cpu_env, t0); |
| tcg_temp_free_i32(t0); |
| } |
| |
| static void spr_write_booke_pid (void *opaque, int sprn, int gprn) |
| { |
| TCGv_i32 t0 = tcg_const_i32(sprn); |
| gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]); |
| tcg_temp_free_i32(t0); |
| } |
| #endif |
| |
| static void gen_spr_usprgh (CPUPPCState *env) |
| { |
| spr_register(env, SPR_USPRG4, "USPRG4", |
| &spr_read_ureg, SPR_NOACCESS, |
| &spr_read_ureg, SPR_NOACCESS, |
| 0x00000000); |
| spr_register(env, SPR_USPRG5, "USPRG5", |
| &spr_read_ureg, SPR_NOACCESS, |
| &spr_read_ureg, SPR_NOACCESS, |
| 0x00000000); |
| spr_register(env, SPR_USPRG6, "USPRG6", |
| &spr_read_ureg, SPR_NOACCESS, |
| &spr_read_ureg, SPR_NOACCESS, |
| 0x00000000); |
| spr_register(env, SPR_USPRG7, "USPRG7", |
| &spr_read_ureg, SPR_NOACCESS, |
| &spr_read_ureg, SPR_NOACCESS, |
| 0x00000000); |
| } |
| |
| /* PowerPC BookE SPR */ |
| static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask) |
| { |
| const char *ivor_names[64] = { |
| "IVOR0", "IVOR1", "IVOR2", "IVOR3", |
| "IVOR4", "IVOR5", "IVOR6", "IVOR7", |
| "IVOR8", "IVOR9", "IVOR10", "IVOR11", |
| "IVOR12", "IVOR13", "IVOR14", "IVOR15", |
| "IVOR16", "IVOR17", "IVOR18", "IVOR19", |
| "IVOR20", "IVOR21", "IVOR22", "IVOR23", |
| "IVOR24", "IVOR25", "IVOR26", "IVOR27", |
| "IVOR28", "IVOR29", "IVOR30", "IVOR31", |
| "IVOR32", "IVOR33", "IVOR34", "IVOR35", |
| "IVOR36", "IVOR37", "IVOR38", "IVOR39", |
| "IVOR40", "IVOR41", "IVOR42", "IVOR43", |
| "IVOR44", "IVOR45", "IVOR46", "IVOR47", |
| "IVOR48", "IVOR49", "IVOR50", "IVOR51", |
| "IVOR52", "IVOR53", "IVOR54", "IVOR55", |
| "IVOR56", "IVOR57", "IVOR58", "IVOR59", |
| "IVOR60", "IVOR61", "IVOR62", "IVOR63", |
| }; |
| #define SPR_BOOKE_IVORxx (-1) |
| int ivor_sprn[64] = { |
| SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3, |
| SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7, |
| SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11, |
| SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15, |
| SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
| SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
| SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
| SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
| SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35, |
| SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39, |
| SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx, |
| SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
| SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
| SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
| SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
| SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, |
| }; |
| int i; |
| |
| /* Interrupt processing */ |
| spr_register(env, SPR_BOOKE_CSRR0, "CSRR0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Debug */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_BOOKE_IAC1, "IAC1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_BOOKE_IAC2, "IAC2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_BOOKE_DAC1, "DAC1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_BOOKE_DAC2, "DAC2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_BOOKE_DBCR0, "DBCR0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_40x_dbcr0, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_BOOKE_DBCR1, "DBCR1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_BOOKE_DBCR2, "DBCR2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_BOOKE_DBSR, "DBSR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_clear, |
| 0x00000000); |
| spr_register(env, SPR_BOOKE_DEAR, "DEAR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_BOOKE_ESR, "ESR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_BOOKE_IVPR, "IVPR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_excp_prefix, |
| 0x00000000); |
| /* Exception vectors */ |
| for (i = 0; i < 64; i++) { |
| if (ivor_mask & (1ULL << i)) { |
| if (ivor_sprn[i] == SPR_BOOKE_IVORxx) { |
| fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i); |
| exit(1); |
| } |
| spr_register(env, ivor_sprn[i], ivor_names[i], |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_excp_vector, |
| 0x00000000); |
| } |
| } |
| spr_register(env, SPR_BOOKE_PID, "PID", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_booke_pid, |
| 0x00000000); |
| spr_register(env, SPR_BOOKE_TCR, "TCR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_booke_tcr, |
| 0x00000000); |
| spr_register(env, SPR_BOOKE_TSR, "TSR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_booke_tsr, |
| 0x00000000); |
| /* Timer */ |
| spr_register(env, SPR_DECR, "DECR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_decr, &spr_write_decr, |
| 0x00000000); |
| spr_register(env, SPR_BOOKE_DECAR, "DECAR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| SPR_NOACCESS, &spr_write_generic, |
| 0x00000000); |
| /* SPRGs */ |
| spr_register(env, SPR_USPRG0, "USPRG0", |
| &spr_read_generic, &spr_write_generic, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_SPRG4, "SPRG4", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_SPRG5, "SPRG5", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_SPRG6, "SPRG6", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_SPRG7, "SPRG7", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize, |
| uint32_t maxsize, uint32_t flags, |
| uint32_t nentries) |
| { |
| return (assoc << TLBnCFG_ASSOC_SHIFT) | |
| (minsize << TLBnCFG_MINSIZE_SHIFT) | |
| (maxsize << TLBnCFG_MAXSIZE_SHIFT) | |
| flags | nentries; |
| } |
| |
| /* BookE 2.06 storage control registers */ |
| static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask, |
| uint32_t *tlbncfg) |
| { |
| #if !defined(CONFIG_USER_ONLY) |
| const char *mas_names[8] = { |
| "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7", |
| }; |
| int mas_sprn[8] = { |
| SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3, |
| SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7, |
| }; |
| int i; |
| |
| /* TLB assist registers */ |
| /* XXX : not implemented */ |
| for (i = 0; i < 8; i++) { |
| void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32; |
| if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) { |
| uea_write = &spr_write_generic; |
| } |
| if (mas_mask & (1 << i)) { |
| spr_register(env, mas_sprn[i], mas_names[i], |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, uea_write, |
| 0x00000000); |
| } |
| } |
| if (env->nb_pids > 1) { |
| /* XXX : not implemented */ |
| spr_register(env, SPR_BOOKE_PID1, "PID1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_booke_pid, |
| 0x00000000); |
| } |
| if (env->nb_pids > 2) { |
| /* XXX : not implemented */ |
| spr_register(env, SPR_BOOKE_PID2, "PID2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_booke_pid, |
| 0x00000000); |
| } |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MMUCFG, "MMUCFG", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| 0x00000000); /* TOFIX */ |
| switch (env->nb_ways) { |
| case 4: |
| spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| tlbncfg[3]); |
| /* Fallthru */ |
| case 3: |
| spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| tlbncfg[2]); |
| /* Fallthru */ |
| case 2: |
| spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| tlbncfg[1]); |
| /* Fallthru */ |
| case 1: |
| spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| tlbncfg[0]); |
| /* Fallthru */ |
| case 0: |
| default: |
| break; |
| } |
| #endif |
| |
| gen_spr_usprgh(env); |
| } |
| |
| /* SPR specific to PowerPC 440 implementation */ |
| static void gen_spr_440 (CPUPPCState *env) |
| { |
| /* Cache control */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_DNV0, "DNV0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_DNV1, "DNV1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_DNV2, "DNV2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_DNV3, "DNV3", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_DTV0, "DTV0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_DTV1, "DTV1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_DTV2, "DTV2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_DTV3, "DTV3", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_DVLIM, "DVLIM", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_INV0, "INV0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_INV1, "INV1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_INV2, "INV2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_INV3, "INV3", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_ITV0, "ITV0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_ITV1, "ITV1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_ITV2, "ITV2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_ITV3, "ITV3", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_IVLIM, "IVLIM", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Cache debug */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_440_DBDR, "DBDR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Processor control */ |
| spr_register(env, SPR_4xx_CCR0, "CCR0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_440_RSTCFG, "RSTCFG", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| 0x00000000); |
| /* Storage control */ |
| spr_register(env, SPR_440_MMUCR, "MMUCR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| /* SPR shared between PowerPC 40x implementations */ |
| static void gen_spr_40x (CPUPPCState *env) |
| { |
| /* Cache */ |
| /* not emulated, as QEMU do not emulate caches */ |
| spr_register(env, SPR_40x_DCCR, "DCCR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* not emulated, as QEMU do not emulate caches */ |
| spr_register(env, SPR_40x_ICCR, "ICCR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* not emulated, as QEMU do not emulate caches */ |
| spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, SPR_NOACCESS, |
| 0x00000000); |
| /* Exception */ |
| spr_register(env, SPR_40x_DEAR, "DEAR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_40x_ESR, "ESR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_40x_EVPR, "EVPR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_excp_prefix, |
| 0x00000000); |
| spr_register(env, SPR_40x_SRR2, "SRR2", |
| &spr_read_generic, &spr_write_generic, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_40x_SRR3, "SRR3", |
| &spr_read_generic, &spr_write_generic, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Timers */ |
| spr_register(env, SPR_40x_PIT, "PIT", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_40x_pit, &spr_write_40x_pit, |
| 0x00000000); |
| spr_register(env, SPR_40x_TCR, "TCR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_booke_tcr, |
| 0x00000000); |
| spr_register(env, SPR_40x_TSR, "TSR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_booke_tsr, |
| 0x00000000); |
| } |
| |
| /* SPR specific to PowerPC 405 implementation */ |
| static void gen_spr_405 (CPUPPCState *env) |
| { |
| /* MMU */ |
| spr_register(env, SPR_40x_PID, "PID", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_4xx_CCR0, "CCR0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00700000); |
| /* Debug interface */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_40x_DBCR0, "DBCR0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_40x_dbcr0, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_405_DBCR1, "DBCR1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_40x_DBSR, "DBSR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_clear, |
| /* Last reset was system reset */ |
| 0x00000300); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_40x_DAC1, "DAC1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_40x_DAC2, "DAC2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_405_DVC1, "DVC1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_405_DVC2, "DVC2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_40x_IAC1, "IAC1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_40x_IAC2, "IAC2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_405_IAC3, "IAC3", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_405_IAC4, "IAC4", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Storage control */ |
| /* XXX: TODO: not implemented */ |
| spr_register(env, SPR_405_SLER, "SLER", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_40x_sler, |
| 0x00000000); |
| spr_register(env, SPR_40x_ZPR, "ZPR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_405_SU0R, "SU0R", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* SPRG */ |
| spr_register(env, SPR_USPRG0, "USPRG0", |
| &spr_read_ureg, SPR_NOACCESS, |
| &spr_read_ureg, SPR_NOACCESS, |
| 0x00000000); |
| spr_register(env, SPR_SPRG4, "SPRG4", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_SPRG5, "SPRG5", |
| SPR_NOACCESS, SPR_NOACCESS, |
| spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_SPRG6, "SPRG6", |
| SPR_NOACCESS, SPR_NOACCESS, |
| spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_SPRG7, "SPRG7", |
| SPR_NOACCESS, SPR_NOACCESS, |
| spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| gen_spr_usprgh(env); |
| } |
| |
| /* SPR shared between PowerPC 401 & 403 implementations */ |
| static void gen_spr_401_403 (CPUPPCState *env) |
| { |
| /* Time base */ |
| spr_register(env, SPR_403_VTBL, "TBL", |
| &spr_read_tbl, SPR_NOACCESS, |
| &spr_read_tbl, SPR_NOACCESS, |
| 0x00000000); |
| spr_register(env, SPR_403_TBL, "TBL", |
| SPR_NOACCESS, SPR_NOACCESS, |
| SPR_NOACCESS, &spr_write_tbl, |
| 0x00000000); |
| spr_register(env, SPR_403_VTBU, "TBU", |
| &spr_read_tbu, SPR_NOACCESS, |
| &spr_read_tbu, SPR_NOACCESS, |
| 0x00000000); |
| spr_register(env, SPR_403_TBU, "TBU", |
| SPR_NOACCESS, SPR_NOACCESS, |
| SPR_NOACCESS, &spr_write_tbu, |
| 0x00000000); |
| /* Debug */ |
| /* not emulated, as QEMU do not emulate caches */ |
| spr_register(env, SPR_403_CDBCR, "CDBCR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| /* SPR specific to PowerPC 401 implementation */ |
| static void gen_spr_401 (CPUPPCState *env) |
| { |
| /* Debug interface */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_40x_DBCR0, "DBCR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_40x_dbcr0, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_40x_DBSR, "DBSR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_clear, |
| /* Last reset was system reset */ |
| 0x00000300); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_40x_DAC1, "DAC", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_40x_IAC1, "IAC", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* Storage control */ |
| /* XXX: TODO: not implemented */ |
| spr_register(env, SPR_405_SLER, "SLER", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_40x_sler, |
| 0x00000000); |
| /* not emulated, as QEMU never does speculative access */ |
| spr_register(env, SPR_40x_SGR, "SGR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0xFFFFFFFF); |
| /* not emulated, as QEMU do not emulate caches */ |
| spr_register(env, SPR_40x_DCWR, "DCWR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| static void gen_spr_401x2 (CPUPPCState *env) |
| { |
| gen_spr_401(env); |
| spr_register(env, SPR_40x_PID, "PID", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_40x_ZPR, "ZPR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| /* SPR specific to PowerPC 403 implementation */ |
| static void gen_spr_403 (CPUPPCState *env) |
| { |
| /* Debug interface */ |
| /* XXX : not implemented */ |
| spr_register(env, SPR_40x_DBCR0, "DBCR0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_40x_dbcr0, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_40x_DBSR, "DBSR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_clear, |
| /* Last reset was system reset */ |
| 0x00000300); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_40x_DAC1, "DAC1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_40x_DAC2, "DAC2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_40x_IAC1, "IAC1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_40x_IAC2, "IAC2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| static void gen_spr_403_real (CPUPPCState *env) |
| { |
| spr_register(env, SPR_403_PBL1, "PBL1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_403_pbr, &spr_write_403_pbr, |
| 0x00000000); |
| spr_register(env, SPR_403_PBU1, "PBU1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_403_pbr, &spr_write_403_pbr, |
| 0x00000000); |
| spr_register(env, SPR_403_PBL2, "PBL2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_403_pbr, &spr_write_403_pbr, |
| 0x00000000); |
| spr_register(env, SPR_403_PBU2, "PBU2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_403_pbr, &spr_write_403_pbr, |
| 0x00000000); |
| } |
| |
| static void gen_spr_403_mmu (CPUPPCState *env) |
| { |
| /* MMU */ |
| spr_register(env, SPR_40x_PID, "PID", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| spr_register(env, SPR_40x_ZPR, "ZPR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| /* SPR specific to PowerPC compression coprocessor extension */ |
| static void gen_spr_compress (CPUPPCState *env) |
| { |
| /* XXX : not implemented */ |
| spr_register(env, SPR_401_SKR, "SKR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| static void gen_spr_5xx_8xx (CPUPPCState *env) |
| { |
| /* Exception processing */ |
| spr_register_kvm(env, SPR_DSISR, "DSISR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| KVM_REG_PPC_DSISR, 0x00000000); |
| spr_register_kvm(env, SPR_DAR, "DAR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| KVM_REG_PPC_DAR, 0x00000000); |
| /* Timer */ |
| spr_register(env, SPR_DECR, "DECR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_decr, &spr_write_decr, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_EIE, "EIE", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_EID, "EID", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_NRI, "NRI", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_CMPA, "CMPA", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_CMPB, "CMPB", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_CMPC, "CMPC", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_CMPD, "CMPD", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_ECR, "ECR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_DER, "DER", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_COUNTA, "COUNTA", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_COUNTB, "COUNTB", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_CMPE, "CMPE", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_CMPF, "CMPF", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_CMPG, "CMPG", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_CMPH, "CMPH", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_LCTRL1, "LCTRL1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_LCTRL2, "LCTRL2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_BAR, "BAR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_DPDR, "DPDR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_IMMR, "IMMR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| static void gen_spr_5xx (CPUPPCState *env) |
| { |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_RCPU_FPECR, "FPECR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| static void gen_spr_8xx (CPUPPCState *env) |
| { |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_IC_CST, "IC_CST", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_IC_ADR, "IC_ADR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_IC_DAT, "IC_DAT", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_DC_CST, "DC_CST", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_DC_ADR, "DC_ADR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_DC_DAT, "DC_DAT", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MI_CTR, "MI_CTR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MI_AP, "MI_AP", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MI_EPN, "MI_EPN", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MI_TWC, "MI_TWC", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MI_RPN, "MI_RPN", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MD_CTR, "MD_CTR", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MD_CASID, "MD_CASID", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MD_AP, "MD_AP", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MD_EPN, "MD_EPN", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MD_TWB, "MD_TWB", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MD_TWC, "MD_TWC", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MD_RPN, "MD_RPN", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MD_TW, "MD_TW", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| /* XXX : not implemented */ |
| spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1", |
| SPR_NOACCESS, SPR_NOACCESS, |
| &spr_read_generic, &spr_write_generic, |
| 0x00000000); |
| } |
| |
| // XXX: TODO |
| /* |
| * AMR => SPR 29 (Power 2.04) |
| * CTRL => SPR 136 (Power 2.04) |
| * CTRL => SPR 152 (Power 2.04) |
| * SCOMC => SPR 276 (64 bits ?) |
| * SCOMD => SPR 277 (64 bits ?) |
| * TBU40 => SPR 286 (Power 2.04 hypv) |
| * HSPRG0 => SPR 304 (Power 2.04 hypv) |
| * HSPRG1 => SPR 305 (Power 2.04 hypv) |
| * HDSISR => SPR 306 (Power 2.04 hypv) |
| * HDAR => SPR 307 (Power 2.04 hypv) |
| * PURR => SPR 309 (Power 2.04 hypv) |
| * HDEC => SPR 310 (Power 2.04 hypv) |
| * HIOR => SPR 311 (hypv) |
| * RMOR => SPR 312 (970) |
| * HRMOR => SPR 313 (Power 2.04 hypv) |
| * HSRR0 => SPR 314 (Power 2.04 hypv) |
| * HSRR1 => SPR 315 (Power 2.04 hypv) |
| * LPIDR => SPR 317 (970) |
| * EPR => SPR 702 (Power 2.04 emb) |
| * perf => 768-783 (Power 2.04) |
| * perf => 784-799 (Power 2.04) |
| * PPR => SPR 896 (Power 2.04) |
| * EPLC => SPR 947 (Power 2.04 emb) |
| * EPSC => SPR 948 (Power 2.04 emb) |
| * DABRX => 1015 (Power 2.04 hypv) |
| * FPECR => SPR 1022 (?) |
| * ... and more (thermal management, performance counters, ...) |
| */ |
| |
| /*****************************************************************************/ |
| /* Exception vectors models */ |
| static void init_excp_4xx_real (CPUPPCState *env) |
| { |
| #if !defined(CONFIG_USER_ONLY) |
| env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; |
| env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
| env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
| env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
| env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
| env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
| env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; |
| env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; |
| env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; |
| env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; |
| env->ivor_mask = 0x0000FFF0UL; |
| env->ivpr_mask = 0xFFFF0000UL; |
| /* Hardware reset vector */ |
| env->hreset_vector = 0xFFFFFFFCUL; |
| #endif |
| } |
| |
| static void init_excp_4xx_softmmu (CPUPPCState *env) |
| { |
| #if !defined(CONFIG_USER_ONLY) |
| env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100; |
| env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
| env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
| env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
| env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
| env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
| env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
| env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
| env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000; |
| env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010; |
| env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020; |
| env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100; |
| env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200; |
| env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000; |
| env->ivor_mask = 0x0000FFF0UL; |
| env->ivpr_mask = 0xFFFF0000UL; |
| /* Hardware reset vector */ |
| env->hreset_vector = 0xFFFFFFFCUL; |
| #endif |
| } |
| |
| static void init_excp_MPC5xx (CPUPPCState *env) |
| { |
| #if !defined(CONFIG_USER_ONLY) |
| env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
| env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
| env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
| env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
| env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
| env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; |
| env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
| env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
| env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
| env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; |
| env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; |
| env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; |
| env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; |
| env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; |
| env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; |
| env->ivor_mask = 0x0000FFF0UL; |
| env->ivpr_mask = 0xFFFF0000UL; |
| /* Hardware reset vector */ |
| env->hreset_vector = 0x00000100UL; |
| #endif |
| } |
| |
| static void init_excp_MPC8xx (CPUPPCState *env) |
| { |
| #if !defined(CONFIG_USER_ONLY) |
| env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
| env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
| env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
| env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
| env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
| env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
| env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
| env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900; |
| env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
| env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
| env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
| env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00; |
| env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000; |
| env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100; |
| env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200; |
| env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300; |
| env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400; |
| env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00; |
| env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00; |
| env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00; |
| env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00; |
| env->ivor_mask = 0x0000FFF0UL; |
| env->ivpr_mask = 0xFFFF0000UL; |
| /* Hardware reset vector */ |
| env->hreset_vector = 0x00000100UL; |
| #endif |
| } |
| |
| static void init_excp_G2 (CPUPPCState *env) |
| { |
| #if !defined(CONFIG_USER_ONLY) |
| env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
| env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
| env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
| env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
| env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
| env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
| env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
| env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; |
| env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
| env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00; |
| env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
| env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
| env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; |
| env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; |
| env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; |
| env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
| env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; |
| /* Hardware reset vector */ |
| env->hreset_vector = 0x00000100UL; |
| #endif |
| } |
| |
| static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask) |
| { |
| #if !defined(CONFIG_USER_ONLY) |
| env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC; |
| env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000; |
| env->ivor_mask = 0x0000FFF7UL; |
| env->ivpr_mask = ivpr_mask; |
| /* Hardware reset vector */ |
| env->hreset_vector = 0xFFFFFFFCUL; |
| #endif |
| } |
| |
| static void init_excp_BookE (CPUPPCState *env) |
| { |
| #if !defined(CONFIG_USER_ONLY) |
| env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000; |
| env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000; |
| env->ivor_mask = 0x0000FFE0UL; |
| env->ivpr_mask = 0xFFFF0000UL; |
| /* Hardware reset vector */ |
| env->hreset_vector = 0xFFFFFFFCUL; |
| #endif |
| } |
| |
| static void init_excp_601 (CPUPPCState *env) |
| { |
| #if !defined(CONFIG_USER_ONLY) |
| env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
| env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
| env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
| env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
| env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
| env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
| env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
| env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; |
| env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
| env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00; |
| env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
| env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000; |
| /* Hardware reset vector */ |
| env->hreset_vector = 0x00000100UL; |
| #endif |
| } |
| |
| static void init_excp_602 (CPUPPCState *env) |
| { |
| #if !defined(CONFIG_USER_ONLY) |
| /* XXX: exception prefix has a special behavior on 602 */ |
| env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
| env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
| env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
| env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
| env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
| env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
| env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
| env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; |
| env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
| env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
| env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
| env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; |
| env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; |
| env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; |
| env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
| env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; |
| env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500; |
| env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600; |
| /* Hardware reset vector */ |
| env->hreset_vector = 0x00000100UL; |
| #endif |
| } |
| |
| static void init_excp_603 (CPUPPCState *env) |
| { |
| #if !defined(CONFIG_USER_ONLY) |
| env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
| env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
| env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
| env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
| env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
| env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
| env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
| env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; |
| env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
| env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
| env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
| env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000; |
| env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100; |
| env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200; |
| env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
| env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; |
| /* Hardware reset vector */ |
| env->hreset_vector = 0x00000100UL; |
| #endif |
| } |
| |
| static void init_excp_604 (CPUPPCState *env) |
| { |
| #if !defined(CONFIG_USER_ONLY) |
| env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100; |
| env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200; |
| env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300; |
| env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400; |
| env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500; |
| env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600; |
| env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700; |
| env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800; |
| env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900; |
| env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00; |
| env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00; |
| env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00; |
| env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300; |
| env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400; |
| /* Hardware reset vector */ |
| env->hreset_vector = 0x00000100UL; |
| #endif |
| } |
| |
| static void init_excp_7x0 (CPUPPCState *env) |
| { |
| #if !defined(CONFIG_USER_ONLY) |
| env |