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qemu-android / qemu-android / 711956722c6764336f8b78a2106e57c55f02f36d / target-arm
  1. 06e5cf7 target-arm: Report S/NS status in the CPU debug logs by Peter Maydell · 9 years ago
  2. 08b8e0f target-arm: Bring AArch64 debug CPU display of PSTATE into line with AArch32 by Peter Maydell · 9 years ago
  3. 99a99c1 target-arm: Add and use symbolic names for register banks by Soren Brinkmann · 9 years ago
  4. 522a0d4 target-*: Advance pc after recognizing a breakpoint by Richard Henderson · 9 years ago
  5. 9b53926 target-arm: Add support for S1 + S2 MMU translations by Edgar E. Iglesias · 9 years ago
  6. d759a45 target-arm: Route S2 MMU faults to EL2 by Edgar E. Iglesias · 9 years ago
  7. a614e69 target-arm: Add S2 translation to 32bit S1 PTWs by Edgar E. Iglesias · 9 years ago
  8. 3778597 target-arm: Add S2 translation to 64bit S1 PTWs by Edgar E. Iglesias · 9 years ago
  9. e14b5a2 target-arm: Add ARMMMUFaultInfo by Edgar E. Iglesias · 9 years ago
  10. af51f56 target-arm: Avoid inline for get_phys_addr by Edgar E. Iglesias · 9 years ago
  11. 6ab1a5e target-arm: Add support for S2 page-table protection bits by Edgar E. Iglesias · 9 years ago
  12. 1853d5a target-arm: Add computation of starting level for S2 PTW by Edgar E. Iglesias · 9 years ago
  13. 973a543 target-arm: lpae: Rename granule_sz to stride by Edgar E. Iglesias · 9 years ago
  14. 4ca6a05 target-arm: lpae: Replace tsz with computed inputsize by Edgar E. Iglesias · 9 years ago
  15. 4ee3809 target-arm: Add support for AArch32 S2 negative t0sz by Edgar E. Iglesias · 9 years ago
  16. 1f4c8c1 target-arm: lpae: Move declaration of t0sz and t1sz by Edgar E. Iglesias · 9 years ago
  17. 5c31a10 target-arm: lpae: Make t0sz and t1sz signed integers by Edgar E. Iglesias · 9 years ago
  18. 59e0553 target-arm: Add HPFAR_EL2 by Edgar E. Iglesias · 9 years ago
  19. b876452 target-arm: Add support for SPSR_(ABT|UND|IRQ|FIQ) by Soren Brinkmann · 9 years ago
  20. 541ebcd target-arm/translate.c: Handle non-executable page-straddling Thumb insns by Peter Maydell · 9 years ago
  21. 7cd6de3 target-arm: Fix "no 64-bit EL2" assumption in arm_excp_unmasked() by Peter Maydell · 9 years ago
  22. 526d580 Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging by Peter Maydell · 9 years ago
  23. dc9f06c kvm: Pass PCI device pointer to MSI routing functions by Pavel Fedin · 9 years ago
  24. 5d98bf8 target-arm: Fix CPU breakpoint handling by Sergey Fedorov · 9 years ago
  25. e63a2d4 target-arm: Fix GDB breakpoint handling by Sergey Fedorov · 9 years ago
  26. 81669b8 target-arm: implement arm_debug_target_el() by Sergey Fedorov · 10 years ago
  27. 14cc7b5 target-arm: Add MDCR_EL2 by Sergey Fedorov · 9 years ago
  28. 1424ca8 target-arm: Implement AArch64 OSLAR/OSLSR_EL1 sysregs by Davorin Mista · 9 years ago
  29. 2cde031 target-arm: Avoid calling arm_el_is_aa64() function for unimplemented EL by Sergey Sorokin · 9 years ago
  30. 6df99de target-arm: Break the TB after ISB to execute self-modified code correctly by Sergey Sorokin · 9 years ago
  31. 82c39f6 target-arm: Add missing 'static' attribute by Stefan Weil · 9 years ago
  32. 4c315c2 qdev: Protect device-list-properties against broken devices by Markus Armbruster · 10 years ago
  33. 4e5e121 tcg: Remove gen_intermediate_code_pc by Richard Henderson · 10 years ago
  34. bad729e tcg: Pass data argument to restore_state_to_opc by Richard Henderson · 10 years ago
  35. 190ce7f tcg: Add TCG_MAX_INSNS by Richard Henderson · 10 years ago
  36. dc03246 target-*: Drop cpu_gen_code define by Richard Henderson · 10 years ago
  37. 52e971d target-arm: Add condexec state to insn_start by Richard Henderson · 10 years ago
  38. b933066 target-*: Introduce and use cpu_breakpoint_test by Richard Henderson · 10 years ago
  39. 959082f target-*: Increment num_insns immediately after tcg_gen_insn_start by Richard Henderson · 10 years ago
  40. 667b8e2 target-*: Unconditionally emit tcg_gen_insn_start by Richard Henderson · 10 years ago
  41. 765b842 tcg: Rename debug_insn_start to insn_start by Richard Henderson · 10 years ago
  42. 9e07142 Merge remote-tracking branch 'remotes/bonzini/tags/for-upstream' into staging by Peter Maydell · 10 years ago
  43. 352c98e arm: clarify the use of muldiv64() by Laurent Vivier · 10 years ago
  44. b597c3f arm: Remove ELF_MACHINE from cpu.h by Peter Crosthwaite · 10 years ago
  45. a7bf303 hw/intc: Initial implementation of vGICv3 by Pavel Fedin · 10 years ago
  46. 34e85cd arm_kvm: Do not assume particular GIC type in kvm_arch_irqchip_create() by Pavel Fedin · 10 years ago
  47. 42fedbc target-arm: Use new revbit functions by Richard Henderson · 10 years ago
  48. f0d574d target-arm: Add VMPIDR_EL2 by Edgar E. Iglesias · 10 years ago
  49. 06a7e64 target-arm: Break out mpidr_read_val() by Edgar E. Iglesias · 10 years ago
  50. 731de9e target-arm: Add VPIDR_EL2 by Edgar E. Iglesias · 10 years ago
  51. 0c5fbf3 target-arm: Suppress EPD for S2, EL2 and EL3 translations by Edgar E. Iglesias · 10 years ago
  52. 1edee47 target-arm: Suppress TBI for S2 translations by Edgar E. Iglesias · 10 years ago
  53. b698e9c target-arm: Add VTTBR_EL2 by Edgar E. Iglesias · 10 years ago
  54. 68e9c2f target-arm: Add VTCR_EL2 by Edgar E. Iglesias · 10 years ago
  55. 7cb36e1 target-arm: Use tcg_gen_extrh_i64_i32 by Richard Henderson · 10 years ago
  56. 8fb0ad8 target-arm: Recognize ROR by Richard Henderson · 10 years ago
  57. d3a77b4 target-arm: Eliminate unnecessary zero-extend in disas_bitfield by Richard Henderson · 10 years ago
  58. 9924e85 target-arm: Recognize UXTB, UXTH, LSR, LSL by Richard Henderson · 10 years ago
  59. ef60151 target-arm: Recognize SXTB, SXTH, SXTW, ASR by Richard Henderson · 10 years ago
  60. 6e06102 target-arm: Implement fcsel with movcond by Richard Henderson · 10 years ago
  61. 7dd03d7 target-arm: Implement ccmp branchless by Richard Henderson · 10 years ago
  62. 259cb68 target-arm: Use setcond and movcond for csel by Richard Henderson · 10 years ago
  63. 9305eac target-arm: Handle always condition codes within arm_test_cc by Richard Henderson · 10 years ago
  64. 6c2c63d target-arm: Introduce DisasCompare by Richard Henderson · 10 years ago
  65. 78bcaa3 target-arm: Share all common TCG temporaries by Richard Henderson · 10 years ago
  66. 97ed5cc tlb: Add "ifetch" argument to cpu_mmu_index() by Benjamin Herrenschmidt · 10 years ago
  67. 67cc32e typofixes - v4 by Veres Lajos · 10 years ago
  68. b6af097 maint: remove / fix many doubled words by Daniel P. Berrange · 10 years ago
  69. c96fc9b target-arm: Add AArch64 access to PAR_EL1 by Edgar E. Iglesias · 10 years ago
  70. 7a379c7 target-arm: Correct opc1 for AT_S12Exx by Edgar E. Iglesias · 10 years ago
  71. dbc29a8 target-arm: Log the target EL when taking exceptions by Edgar E. Iglesias · 10 years ago
  72. cef9ee7 target-arm: Fix default_exception_el() function for the case when EL3 is not supported by Sergey Sorokin · 10 years ago
  73. 0f4a9e4 target-arm: Refactor CPU affinity handling by Pavel Fedin · 10 years ago
  74. 7718425 target-arm: Fix arm_excp_unmasked() function by Sergey Sorokin · 10 years ago
  75. 3a9148d target-arm: Fix AArch32:AArch64 general-purpose register mapping by Sergey Sorokin · 10 years ago
  76. 8f6fd32 arm: Remove hw_error() usages. by Peter Crosthwaite · 10 years ago
  77. f128bf2 arm: cpu: assert() on no-EL2 virt IRQ error condition. by Peter Crosthwaite · 10 years ago
  78. 8012c84 target-arm: Wire up HLT 0xf000 as the A64 semihosting instruction by Peter Maydell · 10 years ago
  79. 7446d35 target-arm/arm-semi.c: SYS_EXIT on A64 takes a parameter block by Peter Maydell · 10 years ago
  80. e9ebfbf target-arm/arm-semi.c: Implement A64 specific SyncCacheRange call by Peter Maydell · 10 years ago
  81. faacc04 target-arm/arm-semi.c: Support widening APIs to 64 bits by Peter Maydell · 10 years ago
  82. bb19cbc target-arm/arm-semi.c: Factor out repeated 'return env->regs[0]' by Peter Maydell · 10 years ago
  83. 205ace5 target-arm: Improve semihosting debug prints by Christopher Covington · 10 years ago
  84. 857b55a target-arm/arm-semi.c: Fix broken SYS_WRITE0 via gdb by Peter Maydell · 10 years ago
  85. cea66e9 target-arm: Implement AArch64 TLBI operations on IPAs by Peter Maydell · 10 years ago
  86. 43efaa3 target-arm: Implement missing EL3 TLB invalidate operations by Peter Maydell · 10 years ago
  87. 2bfb9d7 target-arm: Implement missing EL2 TLBI operations by Peter Maydell · 10 years ago
  88. fd3ed96 target-arm: Restrict AArch64 TLB flushes to the MMU indexes they must touch by Peter Maydell · 10 years ago
  89. 83ddf97 target-arm: Move TLBI ALLE1/ALLE1IS definitions into numeric order by Peter Maydell · 10 years ago
  90. 14db7fe target-arm: Implement AArch32 ATS1H* operations by Peter Maydell · 10 years ago
  91. 87562e4 target-arm: Enable the AArch32 ATS12NSO ops by Peter Maydell · 10 years ago
  92. e761572 target-arm: Add CP_ACCESS_TRAP_UNCATEGORIZED_EL2, 3 by Peter Maydell · 10 years ago
  93. 2a47df9 target-arm: Wire up AArch64 EL2 and EL3 address translation ops by Peter Maydell · 10 years ago
  94. d0a2cbc target-arm: there is no TTBR1 for 32-bit EL2 stage 1 translations by Peter Maydell · 10 years ago
  95. 834a6c6 target-arm: Implement missing ACTLR registers by Peter Maydell · 10 years ago
  96. 37cd6c2 target-arm: Implement missing AFSR registers by Peter Maydell · 10 years ago
  97. 2179ef9 target-arm: Implement missing AMAIR registers by Peter Maydell · 10 years ago
  98. 4cfb8ad target-arm: Add missing MAIR_EL3 and TPIDR_EL3 registers by Peter Maydell · 10 years ago
  99. ecc7b3a tcg: Remove tcg_gen_trunc_i64_i32 by Richard Henderson · 10 years ago
  100. 9ff9dd3 target-arm: Add AArch32 banked register access to secure physical timer by Peter Maydell · 10 years ago