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qemu-android / qemu-android / e8eaa2c0125de7a1169601f99a225593d742cb66 / target-sparc
  1. 25517f9 Use correct type for SPARC cpu_cc_op by Paul Brook · 16 years ago
  2. f80f9ec Convert machine registration to use module init functions by Anthony Liguori · 16 years ago
  3. 1ad2134 Hardware convenience library by Paul Brook · 16 years ago
  4. 5561650 Include assert.h from qemu-common.h by Paul Brook · 16 years ago
  5. 001faf3 Replace gcc variadic macro extension with C99 version by Blue Swirl · 16 years ago
  6. d084469 Convert mulscc by Blue Swirl · 16 years ago
  7. 6c78ea3 Convert udiv/sdiv by Blue Swirl · 16 years ago
  8. 3b2d1e9 Convert tagged ops by Blue Swirl · 16 years ago
  9. 2ca1d92 Convert subx by Blue Swirl · 16 years ago
  10. d4b0d46 Convert sub by Blue Swirl · 16 years ago
  11. 38482a7 Convert logical operations and umul/smul by Blue Swirl · 16 years ago
  12. 789c91e Convert addx by Blue Swirl · 16 years ago
  13. bdf9f35 Convert add by Blue Swirl · 16 years ago
  14. 8393617 Use dynamical computation for condition codes by Blue Swirl · 16 years ago
  15. 719f66a Optimize cmp x, 0 case by Blue Swirl · 16 years ago
  16. dc1a697 Reindent by Blue Swirl · 16 years ago
  17. b89e94a Improve instruction name comments for easier searching by Blue Swirl · 16 years ago
  18. 7ab463c Clarify: dmmuregs[1] is not a typo by Blue Swirl · 16 years ago
  19. 41d7285 Optimize operations with immediate parameters by Blue Swirl · 16 years ago
  20. 67526b2 Fix Sparc64 sign extension problems by Blue Swirl · 16 years ago
  21. 417728d sparc64 fix context value for ITLB fault by Igor Kovalenko · 16 years ago
  22. 82f2cfc sparc64 fix TLB match code by Igor Kovalenko · 16 years ago
  23. 9c22a62 Fix a warning in sparc64-linux-user build by Blue Swirl · 16 years ago
  24. 697a77e sparc64 support TSB related MMU registers by Igor Kovalenko · 16 years ago
  25. 0bf46a4 qemu: introduce qemu_init_vcpu (Marcelo Tosatti) by aliguori · 16 years ago
  26. 6a4955a qemu: per-arch cpu_has_work (Marcelo Tosatti) by aliguori · 16 years ago
  27. 1b530a6 Add new command line option -singlestep for tcg single stepping. by aurel32 · 16 years ago
  28. d78f399 Delete some unused macros detected with -Wp,-Wunused-macros use by blueswir1 · 16 years ago
  29. c276471 The _exit syscall is used for both thread termination in NPTL applications, by pbrook · 16 years ago
  30. 415fc90 Turn MMUs and caches off on reset by blueswir1 · 16 years ago
  31. 0d0266a targets: remove error handling from qemu_malloc() callers (Avi Kivity) by aliguori · 16 years ago
  32. eca1bdf Log reset events (Jan Kiszka) by aliguori · 16 years ago
  33. 8fec2b8 global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost) by aliguori · 16 years ago
  34. 93fcfe3 Convert references to logfile/loglevel to use qemu_log*() macros by aliguori · 16 years ago
  35. 72d239e Get rid of user_mode_only by aurel32 · 16 years ago
  36. afdf810 Fix TLB access (Jakub Jermar) by blueswir1 · 16 years ago
  37. fad6cb1 Update FSF address in GPL/LGPL boilerplate by aurel32 · 16 years ago
  38. 4017190 Add SuperSPARC MMU breakpoint registers (Robert Reif) by blueswir1 · 16 years ago
  39. 963262d Better SuperSPARC emulation (Robert Reif) by blueswir1 · 16 years ago
  40. 8fa211e Implement tick interrupt disable bits by blueswir1 · 16 years ago
  41. b1503cd Use the ARRAY_SIZE() macro where appropriate. by malc · 16 years ago
  42. 1d6198c Remove unnecessary trailing newlines by blueswir1 · 16 years ago
  43. f4a5a5b Add missing "static" by blueswir1 · 16 years ago
  44. 2cbd949 Common cpu_loop_exit prototype by aurel32 · 16 years ago
  45. c0ce998 Use sys-queue.h for break/watchpoint managment (Jan Kiszka) by aliguori · 16 years ago
  46. a1d1bb3 Refactor and enhance break/watchpoint API (Jan Kiszka) by aliguori · 16 years ago
  47. 6b91754 Refactor translation block CPU state handling (Jan Kiszka) by aliguori · 16 years ago
  48. 622ed36 Convert CPU_PC_FROM_TB to static inline (Jan Kiszka) by aliguori · 16 years ago
  49. a7812ae TCG variable type checking. by pbrook · 16 years ago
  50. 2576d83 Use TCG not op by blueswir1 · 16 years ago
  51. 81b5b81 Use andc, orc, nor and nand by blueswir1 · 16 years ago
  52. 527067d Fix TCGv size mismatches by blueswir1 · 16 years ago
  53. 797d5db Add static (spotted by sparse) by blueswir1 · 16 years ago
  54. c55bda3 Fix error in fexpand (spotted by sparse) by blueswir1 · 16 years ago
  55. e18231a Show size for unassigned accesses (Robert Reif) by blueswir1 · 16 years ago
  56. f4b1a84 Rearrange tick functions by blueswir1 · 16 years ago
  57. 48585ec Fix missing prototype warnings by moving declarations by blueswir1 · 16 years ago
  58. 9827e45 Fix MXCC printf warning (based on patch by Robert Reif) by blueswir1 · 16 years ago
  59. cc6747f Add mmu tlb demap support (Igor Kovalenko) by blueswir1 · 16 years ago
  60. e87231d Add a generic Niagara machine by blueswir1 · 16 years ago
  61. c99657d Implement some UA2007 block ASIs by blueswir1 · 16 years ago
  62. b158a78 Implement UA2005 hypervisor traps by blueswir1 · 16 years ago
  63. d81fd72 Move also DEBUG_PCALL (see r5085) by blueswir1 · 16 years ago
  64. 9d92659 Add software and timer interrupt support by blueswir1 · 16 years ago
  65. 1121f87 Fix arguments used in cas/casx, thanks to Igor Kovalenko for spotting by blueswir1 · 16 years ago
  66. ab50801 Use the new concat_tl_i64 op for std and stda by blueswir1 · 16 years ago
  67. a7ec422 Use the new concat_i32_i64 op for std and stda by blueswir1 · 16 years ago
  68. f0d5e47 Move signal handler prototype back to cpu.h by blueswir1 · 16 years ago
  69. 9f4576f Fix array subscript above array bounds error by blueswir1 · 17 years ago
  70. 72ccba7 Fix mulscc with high bits set in either src1 or src2 by blueswir1 · 17 years ago
  71. 5068cbd Write zeros to high bits of y, based on patch by Vince Weaver by blueswir1 · 17 years ago
  72. d84763b Convert rest of ops using float32 to TCG, remove FT0 and FT1 by blueswir1 · 17 years ago
  73. c5d04e9 Partially convert float128 conversion ops to TCG by blueswir1 · 17 years ago
  74. e2ea21b Convert basic 64 bit VIS ops to TCG by blueswir1 · 17 years ago
  75. 1d01299 Convert basic 32 bit VIS ops to TCG by blueswir1 · 17 years ago
  76. 714547b Convert basic float32 ops to TCG by blueswir1 · 17 years ago
  77. 3a3b925 Implement ldxfsr/stxfsr, fix ld(x)fsr masks, convert to TCG by blueswir1 · 17 years ago
  78. 510aba2 Fix a typo in fpsub32 by blueswir1 · 17 years ago
  79. 255e1fc Convert most env fields to TCG registers by blueswir1 · 17 years ago
  80. 47ad35f Silence gcc warning about constant overflow by blueswir1 · 17 years ago
  81. e83ce55 Implement no-fault loads by blueswir1 · 17 years ago
  82. b991c38 Fix sign extension problems with smul and umul (Vince Weaver) by blueswir1 · 17 years ago
  83. 105a1f0 Fix y register loads and stores by blueswir1 · 17 years ago
  84. c8f9349 Remove memcpy32() prototype leftover from r5109 by blueswir1 · 17 years ago
  85. ba6a9d8 Fix FCC handling for Sparc64 target, initial patch by Vince Weaver by blueswir1 · 17 years ago
  86. 91736d3 Fix Sparc64 boot on i386 host: by blueswir1 · 17 years ago
  87. 7621a90 Fix udiv and sdiv on Sparc64 (Vince Weaver) by blueswir1 · 17 years ago
  88. c93e781 Fix wrwim masking (Luis Pureza) by blueswir1 · 17 years ago
  89. 5578cea Use initial CPU definition structure for some CPU fields instead of copying by blueswir1 · 17 years ago
  90. 2ae72bc Correct 32bit carry flag for add instruction (Igor Kovalenko) by blueswir1 · 17 years ago
  91. 06057e6 Fix faligndata (Vince Weaver) by blueswir1 · 17 years ago
  92. 43e9e74 Fix I/D MMU tag reads by blueswir1 · 17 years ago
  93. 01b1fa6 Fix Sparc64 shifts by blueswir1 · 17 years ago
  94. 95f9397 Fix offset handling for ASI loads and stores (Vince Weaver) by blueswir1 · 17 years ago
  95. a7a044f Handle wrapped registers correctly when saving by blueswir1 · 17 years ago
  96. dd5e630 Fix cmp/subcc/addcc op bugs reported by Vince Weaver by blueswir1 · 17 years ago
  97. c19148b Make MAXTL dynamic, bounds check tl when indexing by blueswir1 · 17 years ago
  98. 0b8f1b1 Sparc32: save/load all MMU registers, Sparc64: add CPU save/load by blueswir1 · 17 years ago
  99. c7ba218 Add T1 and T2 CPUs, add a Sun4v machine by blueswir1 · 17 years ago
  100. 74b9dec Use MMU globals for some MMU traps by blueswir1 · 17 years ago