include/hw: Minor upstream integration. This updates a few headers under include/hw to get closer to upstream. Change-Id: Ib495c106c3159be78292afb2d2ba9029258dc64d
diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 3cd4f59..2082f59 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c
@@ -9,6 +9,7 @@ #include "hw/sysbus.h" #include "hw/arm/arm.h" +#include "hw/arm/pic.h" #include "exec/ram_addr.h" #include "sysemu/sysemu.h"
diff --git a/hw/arm/pic.c b/hw/arm/pic.c index 4ffee29..0b16427 100644 --- a/hw/arm/pic.c +++ b/hw/arm/pic.c
@@ -10,6 +10,7 @@ #include "hw/hw.h" #include "hw/i386/pc.h" #include "hw/arm/arm.h" +#include "hw/arm/pic.h" /* Stub functions for hardware that doesn't exist. */ void pic_info(Monitor *mon)
diff --git a/include/hw/arm/arm.h b/include/hw/arm/arm.h index b5f68be..53ea265 100644 --- a/include/hw/arm/arm.h +++ b/include/hw/arm/arm.h
@@ -4,7 +4,7 @@ * Copyright (c) 2006 CodeSourcery. * Written by Paul Brook * - * This code is licenced under the LGPL. + * This code is licensed under the LGPL. * */ @@ -14,11 +14,6 @@ #include "cpu.h" #include "hw/loader.h" -/* The CPU is also modeled as an interrupt controller. */ -#define ARM_PIC_CPU_IRQ 0 -#define ARM_PIC_CPU_FIQ 1 -qemu_irq *arm_pic_init_cpu(CPUState *cpu); - /* armv7m.c */ qemu_irq *armv7m_init(int flash_size, int sram_size, const char *kernel_filename, const char *cpu_model);
diff --git a/include/hw/i386/smbios.h b/include/hw/i386/smbios.h index 3a5169d..94e3641 100644 --- a/include/hw/i386/smbios.h +++ b/include/hw/i386/smbios.h
@@ -26,7 +26,7 @@ uint8_t type; uint8_t length; uint16_t handle; -} __attribute__((__packed__)); +} QEMU_PACKED; /* SMBIOS type 0 - BIOS Information */ struct smbios_type_0 { @@ -42,7 +42,7 @@ uint8_t system_bios_minor_release; uint8_t embedded_controller_major_release; uint8_t embedded_controller_minor_release; -} __attribute__((__packed__)); +} QEMU_PACKED; /* SMBIOS type 1 - System Information */ struct smbios_type_1 { @@ -55,7 +55,7 @@ uint8_t wake_up_type; uint8_t sku_number_str; uint8_t family_str; -} __attribute__((__packed__)); +} QEMU_PACKED; /* SMBIOS type 3 - System Enclosure (v2.3) */ struct smbios_type_3 { @@ -74,7 +74,7 @@ uint8_t number_of_power_cords; uint8_t contained_element_count; // contained elements follow -} __attribute__((__packed__)); +} QEMU_PACKED; /* SMBIOS type 4 - Processor Information (v2.0) */ struct smbios_type_4 { @@ -94,7 +94,7 @@ uint16_t l1_cache_handle; uint16_t l2_cache_handle; uint16_t l3_cache_handle; -} __attribute__((__packed__)); +} QEMU_PACKED; /* SMBIOS type 16 - Physical Memory Array * Associated with one type 17 (Memory Device). @@ -107,7 +107,7 @@ uint32_t maximum_capacity; uint16_t memory_error_information_handle; uint16_t number_of_memory_devices; -} __attribute__((__packed__)); +} QEMU_PACKED; /* SMBIOS type 17 - Memory Device * Associated with one type 19 */ @@ -124,7 +124,7 @@ uint8_t bank_locator_str; uint8_t memory_type; uint16_t type_detail; -} __attribute__((__packed__)); +} QEMU_PACKED; /* SMBIOS type 19 - Memory Array Mapped Address */ struct smbios_type_19 { @@ -133,7 +133,7 @@ uint32_t ending_address; uint16_t memory_array_handle; uint8_t partition_width; -} __attribute__((__packed__)); +} QEMU_PACKED; /* SMBIOS type 20 - Memory Device Mapped Address */ struct smbios_type_20 { @@ -145,18 +145,18 @@ uint8_t partition_row_position; uint8_t interleave_position; uint8_t interleaved_data_depth; -} __attribute__((__packed__)); +} QEMU_PACKED; /* SMBIOS type 32 - System Boot Information */ struct smbios_type_32 { struct smbios_structure_header header; uint8_t reserved[6]; uint8_t boot_status; -} __attribute__((__packed__)); +} QEMU_PACKED; /* SMBIOS type 127 -- End-of-table */ struct smbios_type_127 { struct smbios_structure_header header; -} __attribute__((__packed__)); +} QEMU_PACKED; #endif /*QEMU_SMBIOS_H */
diff --git a/include/hw/input/ps2.h b/include/hw/input/ps2.h index 32a4231..7c45ce7 100644 --- a/include/hw/input/ps2.h +++ b/include/hw/input/ps2.h
@@ -1,3 +1,30 @@ +/* + * QEMU PS/2 keyboard/mouse emulation + * + * Copyright (C) 2003 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef HW_PS2_H +#define HW_PS2_H + /* ps2.c */ void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg); void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg); @@ -7,3 +34,5 @@ void ps2_queue(void *, int b); void ps2_keyboard_set_translation(void *opaque, int mode); void ps2_mouse_fake_event(void *opaque); + +#endif /* !HW_PS2_H */
diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 67b3435..54809aa 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h
@@ -55,10 +55,14 @@ #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710 #define PCI_DEVICE_ID_VMWARE_NET 0x0720 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730 +#define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729 +#define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0 /* Intel (0x8086) */ #define PCI_DEVICE_ID_INTEL_82551IT 0x1209 +#define PCI_DEVICE_ID_INTEL_82557 0x1229 +#define PCI_DEVICE_ID_INTEL_82801IR 0x2922 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */ #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4 @@ -69,6 +73,19 @@ #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003 +#define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004 +#define PCI_DEVICE_ID_VIRTIO_RNG 0x1005 +#define PCI_DEVICE_ID_VIRTIO_9P 0x1009 + +#define PCI_VENDOR_ID_REDHAT 0x1b36 +#define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001 +#define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002 +#define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003 +#define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004 +#define PCI_DEVICE_ID_REDHAT_TEST 0x0005 +#define PCI_DEVICE_ID_REDHAT_QXL 0x0100 + +#define FMT_PCIBUS PRIx64 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, uint32_t address, uint32_t data, int len); @@ -139,6 +156,7 @@ struct PCIDevice { DeviceState qdev; + /* PCI config space */ uint8_t config[256]; @@ -260,6 +278,12 @@ } static inline void +pci_config_set_revision(uint8_t *pci_config, uint8_t val) +{ + pci_set_byte(&pci_config[PCI_REVISION_ID], val); +} + +static inline void pci_config_set_class(uint8_t *pci_config, uint16_t val) { pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
diff --git a/include/hw/pci/pci_ids.h b/include/hw/pci/pci_ids.h index 3afe674..e597070 100644 --- a/include/hw/pci/pci_ids.h +++ b/include/hw/pci/pci_ids.h
@@ -7,6 +7,8 @@ * * QEMU-specific definitions belong in pci.h */ +#ifndef HW_PCI_IDS_H +#define HW_PCI_IDS_H 1 /* Device classes and subclasses */ @@ -15,6 +17,9 @@ #define PCI_CLASS_STORAGE_SCSI 0x0100 #define PCI_CLASS_STORAGE_IDE 0x0101 +#define PCI_CLASS_STORAGE_RAID 0x0104 +#define PCI_CLASS_STORAGE_SATA 0x0106 +#define PCI_CLASS_STORAGE_EXPRESS 0x0108 #define PCI_CLASS_STORAGE_OTHER 0x0180 #define PCI_CLASS_NETWORK_ETHERNET 0x0200 @@ -29,12 +34,15 @@ #define PCI_CLASS_SYSTEM_OTHER 0x0880 #define PCI_CLASS_SERIAL_USB 0x0c03 +#define PCI_CLASS_SERIAL_SMBUS 0x0c05 #define PCI_CLASS_BRIDGE_HOST 0x0600 #define PCI_CLASS_BRIDGE_ISA 0x0601 #define PCI_CLASS_BRIDGE_PCI 0x0604 +#define PCI_CLASS_BRIDGE_PCI_INF_SUB 0x01 #define PCI_CLASS_BRIDGE_OTHER 0x0680 +#define PCI_CLASS_COMMUNICATION_SERIAL 0x0700 #define PCI_CLASS_COMMUNICATION_OTHER 0x0780 #define PCI_CLASS_PROCESSOR_CO 0x0b40 @@ -45,7 +53,9 @@ /* Vendors and devices. Sort key: vendor first, device next. */ #define PCI_VENDOR_ID_LSI_LOGIC 0x1000 +#define PCI_DEVICE_ID_LSI_53C810 0x0001 #define PCI_DEVICE_ID_LSI_53C895A 0x0012 +#define PCI_DEVICE_ID_LSI_SAS1078 0x0060 #define PCI_VENDOR_ID_DEC 0x1011 #define PCI_DEVICE_ID_DEC_21154 0x0026 @@ -56,6 +66,9 @@ #define PCI_VENDOR_ID_AMD 0x1022 #define PCI_DEVICE_ID_AMD_LANCE 0x2000 +#define PCI_DEVICE_ID_AMD_SCSI 0x2020 + +#define PCI_VENDOR_ID_TI 0x104c #define PCI_VENDOR_ID_MOTOROLA 0x1057 #define PCI_DEVICE_ID_MOTOROLA_MPC106 0x0002 @@ -63,6 +76,7 @@ #define PCI_VENDOR_ID_APPLE 0x106b #define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020 +#define PCI_DEVICE_ID_APPLE_U3_AGP 0x004b #define PCI_VENDOR_ID_SUN 0x108e #define PCI_DEVICE_ID_SUN_EBUS 0x1000 @@ -77,6 +91,14 @@ #define PCI_VENDOR_ID_XILINX 0x10ee +#define PCI_VENDOR_ID_VIA 0x1106 +#define PCI_DEVICE_ID_VIA_ISA_BRIDGE 0x0686 +#define PCI_DEVICE_ID_VIA_IDE 0x0571 +#define PCI_DEVICE_ID_VIA_UHCI 0x3038 +#define PCI_DEVICE_ID_VIA_ACPI 0x3057 +#define PCI_DEVICE_ID_VIA_AC97 0x3058 +#define PCI_DEVICE_ID_VIA_MC97 0x3068 + #define PCI_VENDOR_ID_MARVELL 0x11ab #define PCI_VENDOR_ID_ENSONIQ 0x1274 @@ -86,8 +108,12 @@ #define PCI_DEVICE_ID_MPC8533E 0x0030 #define PCI_VENDOR_ID_INTEL 0x8086 +#define PCI_DEVICE_ID_INTEL_82378 0x0484 #define PCI_DEVICE_ID_INTEL_82441 0x1237 #define PCI_DEVICE_ID_INTEL_82801AA_5 0x2415 +#define PCI_DEVICE_ID_INTEL_82801BA_11 0x244e +#define PCI_DEVICE_ID_INTEL_82801D 0x24CD +#define PCI_DEVICE_ID_INTEL_ESB_9 0x25ab #define PCI_DEVICE_ID_INTEL_82371SB_0 0x7000 #define PCI_DEVICE_ID_INTEL_82371SB_1 0x7010 #define PCI_DEVICE_ID_INTEL_82371SB_2 0x7020 @@ -95,3 +121,36 @@ #define PCI_DEVICE_ID_INTEL_82371AB 0x7111 #define PCI_DEVICE_ID_INTEL_82371AB_2 0x7112 #define PCI_DEVICE_ID_INTEL_82371AB_3 0x7113 + +#define PCI_DEVICE_ID_INTEL_ICH9_0 0x2910 +#define PCI_DEVICE_ID_INTEL_ICH9_1 0x2917 +#define PCI_DEVICE_ID_INTEL_ICH9_2 0x2912 +#define PCI_DEVICE_ID_INTEL_ICH9_3 0x2913 +#define PCI_DEVICE_ID_INTEL_ICH9_4 0x2914 +#define PCI_DEVICE_ID_INTEL_ICH9_5 0x2919 +#define PCI_DEVICE_ID_INTEL_ICH9_6 0x2930 +#define PCI_DEVICE_ID_INTEL_ICH9_7 0x2916 +#define PCI_DEVICE_ID_INTEL_ICH9_8 0x2918 + +#define PCI_DEVICE_ID_INTEL_82801I_UHCI1 0x2934 +#define PCI_DEVICE_ID_INTEL_82801I_UHCI2 0x2935 +#define PCI_DEVICE_ID_INTEL_82801I_UHCI3 0x2936 +#define PCI_DEVICE_ID_INTEL_82801I_UHCI4 0x2937 +#define PCI_DEVICE_ID_INTEL_82801I_UHCI5 0x2938 +#define PCI_DEVICE_ID_INTEL_82801I_UHCI6 0x2939 +#define PCI_DEVICE_ID_INTEL_82801I_EHCI1 0x293a +#define PCI_DEVICE_ID_INTEL_82801I_EHCI2 0x293c +#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed + +#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0 + +#define PCI_VENDOR_ID_XEN 0x5853 +#define PCI_DEVICE_ID_XEN_PLATFORM 0x0001 + +#define PCI_VENDOR_ID_NEC 0x1033 +#define PCI_DEVICE_ID_NEC_UPD720200 0x0194 + +#define PCI_VENDOR_ID_TEWS 0x1498 +#define PCI_DEVICE_ID_TEWS_TPCI200 0x30C8 + +#endif