cpu_unassigned_access now takes a CPUState* parameter.

Also add empty inlined versions for arm and i386, since this will
be called from the new unified memory API.

Change-Id: Ie1f6ddb6280f716eacba6e73ad41b38710351c06
diff --git a/cputlb.c b/cputlb.c
index e3ba7e8..14808ea 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -329,7 +329,7 @@
     pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
     if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
-        cpu_unassigned_access(env1, addr, 0, 1, 0, 4);
+        cpu_unassigned_access(ENV_GET_CPU(env1), addr, 0, 1, 0, 4);
 #else
         cpu_abort(cpu, "Trying to execute code outside RAM or ROM at 0x"
                   TARGET_FMT_lx "\n", addr);
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 3b818b5..f9bdc3e 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1116,6 +1116,16 @@
             (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB));
 }
 
+// TODO(digit): Remove this.
+static inline void cpu_unassigned_access(CPUState *cpu,
+                                         hwaddr addr,
+                                         bool is_write,
+                                         bool is_exec,
+                                         int unused,
+                                         int size)
+{
+    // Nothing to do on this architecture.
+}
 #include "exec/exec-all.h"
 
 static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index cc2cd47..ca588ce 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -1198,5 +1198,15 @@
     }
 }
 
+// TODO(digit): Remove this.
+static inline void cpu_unassigned_access(CPUState *cpu,
+                                         hwaddr addr,
+                                         bool is_write,
+                                         bool is_exec,
+                                         int unused,
+                                         int size)
+{
+    // Nothing to do on this architecture.
+}
 
 #endif /* CPU_I386_H */
diff --git a/target-mips/cpu.h b/target-mips/cpu.h
index ccb71f6..fddf468 100644
--- a/target-mips/cpu.h
+++ b/target-mips/cpu.h
@@ -496,7 +496,7 @@
 void r4k_helper_tlbr(CPUMIPSState *env);
 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
 
-void cpu_unassigned_access(CPUArchState* env, hwaddr addr,
+void cpu_unassigned_access(CPUState* cpu, hwaddr addr,
                            int is_write, int is_exec, int unused, int size);
 
 #define cpu_init cpu_mips_init
diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c
index 3321b3e..2d2834b 100644
--- a/target-mips/op_helper.c
+++ b/target-mips/op_helper.c
@@ -1980,9 +1980,11 @@
     }
 }
 
-void cpu_unassigned_access(CPUMIPSState* env, hwaddr addr,
+void cpu_unassigned_access(CPUState* cpu, hwaddr addr,
                            int is_write, int is_exec, int unused, int size)
 {
+    CPUMIPSState *env = cpu->env_ptr;
+
     if (is_exec)
         helper_raise_exception(env, EXCP_IBE);
     else