commit 3a123f1c76a5310086fff7c6efef9a957ae8204a
author David 'Digit' Turner <digit@google.com> Thu Apr 24 15:15:07 2014 +0200
committer David 'Digit' Turner <digit@google.com> Fri Jul 18 15:31:43 2014 +0200
tree ac0a0f85b2930d975e726133ecdad01293ce5362
parent 62b9e60815d4f05918c3ac58055522547c1ebbe1

tb_flush_jmp_cache takes a CPUState* argument

Change-Id: I555670766a15fd1bbf7a0256151d3d8454bd0d71

cputlb.c

diff --git a/cputlb.c b/cputlb.c
index e731874..e3ba7e8 100644
--- a/cputlb.c
+++ b/cputlb.c
@@ -23,6 +23,9 @@
 #include "exec/cputlb.h"
 #include "exec/ram_addr.h"
 
+//#define DEBUG_TLB
+//#define DEBUG_TLB_CHECK
+
 /* statistics */
 int tlb_flush_count;
 
@@ -99,7 +102,7 @@
         tlb_flush_entry(&env->tlb_table[mmu_idx][i], addr);
     }
 
-    tb_flush_jmp_cache(env, addr);
+    tb_flush_jmp_cache(cpu, addr);
 }
 
 /* update the TLBs so that writes to code in the virtual page 'addr'
@@ -112,7 +115,7 @@
 
 /* update the TLB so that writes in physical page 'phys_addr' are no longer
    tested for self modifying code */
-void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
+void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr,
                              target_ulong vaddr)
 {
     cpu_physical_memory_set_dirty_flag(ram_addr, DIRTY_MEMORY_CODE);

include/exec/cputlb.h

diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h
index efe0d9c..e0daf4c 100644
--- a/include/exec/cputlb.h
+++ b/include/exec/cputlb.h
@@ -22,7 +22,7 @@
 #if !defined(CONFIG_USER_ONLY)
 /* cputlb.c */
 void tlb_protect_code(ram_addr_t ram_addr);
-void tlb_unprotect_code_phys(CPUArchState *env, ram_addr_t ram_addr,
+void tlb_unprotect_code_phys(CPUState *cpu, ram_addr_t ram_addr,
                              target_ulong vaddr);
 void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
                            uintptr_t length);
@@ -31,13 +31,13 @@
 extern int tlb_flush_count;
 
 /* exec.c */
-void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr);
+void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr);
 
 #ifndef CONFIG_ANDROID // TODO(digit)
 MemoryRegionSection *
 address_space_translate_for_iotlb(AddressSpace *as, hwaddr addr, hwaddr *xlat,
                                   hwaddr *plen);
-hwaddr memory_region_section_get_iotlb(CPUArchState *env,
+hwaddr memory_region_section_get_iotlb(CPUState *cpu,
                                        MemoryRegionSection *section,
                                        target_ulong vaddr,
                                        hwaddr paddr, hwaddr xlat,

translate-all.c

diff --git a/translate-all.c b/translate-all.c
index 179675f..78c643d 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1045,7 +1045,9 @@
 {
     TranslationBlock *tb, *tb_next, *saved_tb;
     CPUState *cpu = current_cpu;
-    CPUArchState *env = cpu ? cpu->env_ptr : NULL;
+#if defined(TARGET_HAS_PRECISE_SMC)
+    CPUArchState *env = NULL;
+#endif
     tb_page_addr_t tb_start, tb_end;
     PageDesc *p;
     int n;
@@ -1068,6 +1070,11 @@
         /* build code bitmap */
         build_page_bitmap(p);
     }
+#if defined(TARGET_HAS_PRECISE_SMC)
+    if (cpu != NULL) {
+        env = cpu->env_ptr;
+    }
+#endif
 
     /* we remove all the TBs in the range [start, end[ */
     /* XXX: see if in some cases it could be faster to invalidate all
@@ -1133,7 +1140,7 @@
     if (!p->first_tb) {
         invalidate_page_bitmap(p);
         if (is_cpu_write_access) {
-            tlb_unprotect_code_phys(env, start, cpu->mem_io_vaddr);
+            tlb_unprotect_code_phys(cpu, start, cpu->mem_io_vaddr);
         }
     }
 #endif
@@ -1560,9 +1567,8 @@
     cpu_resume_from_signal(env, NULL);
 }
 
-void tb_flush_jmp_cache(CPUArchState *env, target_ulong addr)
+void tb_flush_jmp_cache(CPUState *cpu, target_ulong addr)
 {
-    CPUState *cpu = ENV_GET_CPU(env);
     unsigned int i;
 
     /* Discard jump cache entries for any tb which might potentially