target-arm: Remove obsolete ARM SMC support.
Change-Id: I730d48490d2fe2dcabd1d3396f5992c921bf4eaf
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 13e836c..38f8673 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -54,7 +54,6 @@
#define EXCP_EXCEPTION_EXIT 8 /* Return from v7M exception. */
#define EXCP_KERNEL_TRAP 9 /* Jumped to kernel code page. */
#define EXCP_STREX 10
-#define EXCP_SMC 11 /* secure monitor call */
#define ARMV7M_EXCP_RESET 1
#define ARMV7M_EXCP_NMI 2
@@ -549,7 +548,6 @@
ARM_CPU_MODE_FIQ = 0x11,
ARM_CPU_MODE_IRQ = 0x12,
ARM_CPU_MODE_SVC = 0x13,
- ARM_CPU_MODE_SMC = 0x16,
ARM_CPU_MODE_ABT = 0x17,
ARM_CPU_MODE_UND = 0x1b,
ARM_CPU_MODE_SYS = 0x1f
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 15fa0f5..9357ca4 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -699,8 +699,6 @@
return 4;
case ARM_CPU_MODE_FIQ:
return 5;
- case ARM_CPU_MODE_SMC:
- return 6;
}
cpu_abort(env, "Bad mode %x\n", mode);
return -1;
@@ -950,33 +948,15 @@
mask = CPSR_A | CPSR_I | CPSR_F;
offset = 4;
break;
- case EXCP_SMC:
- if (semihosting_enabled) {
- cpu_abort(env, "SMC handling under semihosting not implemented\n");
- return;
- }
- if ((env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SMC) {
- env->cp15.c1_secfg &= ~1;
- }
- offset = env->thumb ? 2 : 0;
- new_mode = ARM_CPU_MODE_SMC;
- addr = 0x08;
- mask = CPSR_A | CPSR_I | CPSR_F;
- break;
default:
cpu_abort(env, "Unhandled exception 0x%x\n", env->exception_index);
return; /* Never happens. Keep compiler happy. */
}
if (arm_feature(env, ARM_FEATURE_TRUSTZONE)) {
- if (new_mode == ARM_CPU_MODE_SMC ||
- (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_SMC) {
- addr += env->cp15.c12_mvbar;
+ if (env->cp15.c1_sys & (1 << 13)) {
+ addr += 0xffff0000;
} else {
- if (env->cp15.c1_sys & (1 << 13)) {
- addr += 0xffff0000;
- } else {
- addr += env->cp15.c12_vbar;
- }
+ addr += env->cp15.c12_vbar;
}
} else {
/* High vectors. */
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 955eaf2..8e2976f 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -744,11 +744,6 @@
}
}
-static inline void gen_smc(CPUARMState *env, DisasContext *s)
-{
- tcg_gen_movi_i32(cpu_R[15], s->pc);
- s->is_jmp = DISAS_SMC;
-}
/* Abstractions of "generate code to do a guest load/store for
* AArch32", where a vaddr is always 32 bits (and is zero
@@ -6980,19 +6975,15 @@
store_reg(s, rd, tmp);
break;
case 7:
- if (op1 == 1) {
- /* bkpt */
- ARCH(5);
- gen_exception_insn(s, 4, EXCP_BKPT);
- } else if (op1 == 3) {
- /* smi/smc */
- if (!(env->cp15.c0_c2[4] & 0xf000) || IS_USER(s)) {
- goto illegal_op;
- }
- gen_smc(env, s);
- } else {
+ /* SMC instruction (op1 == 3)
+ and undefined instructions (op1 == 0 || op1 == 2)
+ will trap */
+ if (op1 != 1) {
goto illegal_op;
}
+ /* bkpt */
+ ARCH(5);
+ gen_exception_insn(s, 4, EXCP_BKPT);
break;
case 0x8: /* signed multiply */
case 0xa:
@@ -8638,11 +8629,10 @@
goto illegal_op;
if (insn & (1 << 26)) {
- /* Secure monitor call / smc (v6Z) */
- if (!(env->cp15.c0_c2[4] & 0xf000) || IS_USER(s)) {
- goto illegal_op;
- }
- gen_smc(env, s);
+ /* Secure monitor call (v6Z) */
+ qemu_log_mask(LOG_UNIMP,
+ "arm: unimplemented secure monitor call\n");
+ goto illegal_op; /* not implemented. */
} else {
op = (insn >> 20) & 7;
switch (op) {
@@ -10000,8 +9990,6 @@
gen_set_condexec(dc);
if (dc->is_jmp == DISAS_SWI) {
gen_exception(EXCP_SWI);
- } else if (dc->is_jmp == DISAS_SMC) {
- gen_exception(EXCP_SMC);
} else {
gen_exception(EXCP_DEBUG);
}
@@ -10014,8 +10002,6 @@
gen_set_condexec(dc);
if (dc->is_jmp == DISAS_SWI && !dc->condjmp) {
gen_exception(EXCP_SWI);
- } else if (dc->is_jmp == DISAS_SMC && !dc->condjmp) {
- gen_exception(EXCP_SMC);
} else {
/* FIXME: Single stepping a WFI insn will not halt
the CPU. */
@@ -10050,9 +10036,6 @@
case DISAS_SWI:
gen_exception(EXCP_SWI);
break;
- case DISAS_SMC:
- gen_exception(EXCP_SMC);
- break;
}
if (dc->condjmp) {
gen_set_label(dc->condlabel);
diff --git a/target-arm/translate.h b/target-arm/translate.h
index 4761e41..a1ff2e0 100644
--- a/target-arm/translate.h
+++ b/target-arm/translate.h
@@ -34,7 +34,6 @@
*/
#define DISAS_WFI 4
#define DISAS_SWI 5
-#define DISAS_SMC 6
/* For instructions which unconditionally cause an exception we can skip
* emitting unreachable code at the end of the TB in the A64 decoder
*/
