target-i386: Make a20_mask 32-bit
Upstream patch: 5ee0ffaa42b02e04d8047c7fc32687b348719294
Change-Id: Iec02904fe4097238e20682dd2cbdfec29943c203
diff --git a/target-i386/cpu.h b/target-i386/cpu.h
index e3a3885..aa936df 100644
--- a/target-i386/cpu.h
+++ b/target-i386/cpu.h
@@ -785,7 +785,7 @@
SegmentCache idt; /* only base and limit are used */
target_ulong cr[5]; /* NOTE: cr1 is unused */
- uint64_t a20_mask;
+ int32_t a20_mask;
/* FPU state */
unsigned int fpstt; /* top of stack index */
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 1999b73..9ce3d80 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -704,7 +704,7 @@
eflags & CC_C ? 'C' : '-',
env->hflags & HF_CPL_MASK,
(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
- (int)(env->a20_mask >> 20) & 1,
+ (env->a20_mask >> 20) & 1,
(env->hflags >> HF_SMM_SHIFT) & 1,
cpu->halted);
} else
@@ -731,7 +731,7 @@
eflags & CC_C ? 'C' : '-',
env->hflags & HF_CPL_MASK,
(env->hflags >> HF_INHIBIT_IRQ_SHIFT) & 1,
- (int)(env->a20_mask >> 20) & 1,
+ (env->a20_mask >> 20) & 1,
(env->hflags >> HF_SMM_SHIFT) & 1,
cpu->halted);
}
@@ -850,7 +850,7 @@
/* when a20 is changed, all the MMU mappings are invalid, so
we must flush everything */
tlb_flush(env, 1);
- env->a20_mask = (~0x100000) | (a20_state << 20);
+ env->a20_mask = ~(1 << 20) | (a20_state << 20);
}
}
diff --git a/target-i386/machine.c b/target-i386/machine.c
index 396cafb..603fe42 100644
--- a/target-i386/machine.c
+++ b/target-i386/machine.c
@@ -27,7 +27,6 @@
CPUX86State *env = opaque;
uint16_t fptag, fpus, fpuc, fpregs_format;
uint32_t hflags;
- int32_t a20_mask;
int i;
cpu_synchronize_state(ENV_GET_CPU(env), 0);
@@ -82,8 +81,7 @@
qemu_put_betls(f, &env->dr[i]);
/* MMU */
- a20_mask = (int32_t) env->a20_mask;
- qemu_put_sbe32s(f, &a20_mask);
+ qemu_put_sbe32s(f, &env->a20_mask);
/* XMM */
qemu_put_be32s(f, &env->mxcsr);
@@ -151,7 +149,6 @@
int i, guess_mmx;
uint32_t hflags;
uint16_t fpus, fpuc, fptag, fpregs_format;
- int32_t a20_mask;
if (version_id < 3 || version_id > CPU_SAVE_VERSION)
return -EINVAL;
@@ -231,8 +228,7 @@
hw_breakpoint_insert(env, i);
/* MMU */
- qemu_get_sbe32s(f, &a20_mask);
- env->a20_mask = a20_mask;
+ qemu_get_sbe32s(f, &env->a20_mask);
qemu_get_be32s(f, &env->mxcsr);
for(i = 0; i < CPU_NB_REGS; i++) {