| /* |
| * AArch64 translation |
| * |
| * Copyright (c) 2013 Alexander Graf <agraf@suse.de> |
| * |
| * This library is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU Lesser General Public |
| * License as published by the Free Software Foundation; either |
| * version 2 of the License, or (at your option) any later version. |
| * |
| * This library is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| * Lesser General Public License for more details. |
| * |
| * You should have received a copy of the GNU Lesser General Public |
| * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
| */ |
| #include "qemu/osdep.h" |
| |
| #include "cpu.h" |
| #include "exec/exec-all.h" |
| #include "tcg-op.h" |
| #include "qemu/log.h" |
| #include "arm_ldst.h" |
| #include "translate.h" |
| #include "internals.h" |
| #include "qemu/host-utils.h" |
| |
| #include "exec/semihost.h" |
| #include "exec/gen-icount.h" |
| |
| #include "exec/helper-proto.h" |
| #include "exec/helper-gen.h" |
| #include "exec/log.h" |
| |
| #include "trace-tcg.h" |
| |
| static TCGv_i64 cpu_X[32]; |
| static TCGv_i64 cpu_pc; |
| |
| /* Load/store exclusive handling */ |
| static TCGv_i64 cpu_exclusive_high; |
| |
| static const char *regnames[] = { |
| "x0", "x1", "x2", "x3", "x4", "x5", "x6", "x7", |
| "x8", "x9", "x10", "x11", "x12", "x13", "x14", "x15", |
| "x16", "x17", "x18", "x19", "x20", "x21", "x22", "x23", |
| "x24", "x25", "x26", "x27", "x28", "x29", "lr", "sp" |
| }; |
| |
| enum a64_shift_type { |
| A64_SHIFT_TYPE_LSL = 0, |
| A64_SHIFT_TYPE_LSR = 1, |
| A64_SHIFT_TYPE_ASR = 2, |
| A64_SHIFT_TYPE_ROR = 3 |
| }; |
| |
| /* Table based decoder typedefs - used when the relevant bits for decode |
| * are too awkwardly scattered across the instruction (eg SIMD). |
| */ |
| typedef void AArch64DecodeFn(DisasContext *s, uint32_t insn); |
| |
| typedef struct AArch64DecodeTable { |
| uint32_t pattern; |
| uint32_t mask; |
| AArch64DecodeFn *disas_fn; |
| } AArch64DecodeTable; |
| |
| /* Function prototype for gen_ functions for calling Neon helpers */ |
| typedef void NeonGenOneOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32); |
| typedef void NeonGenTwoOpFn(TCGv_i32, TCGv_i32, TCGv_i32); |
| typedef void NeonGenTwoOpEnvFn(TCGv_i32, TCGv_ptr, TCGv_i32, TCGv_i32); |
| typedef void NeonGenTwo64OpFn(TCGv_i64, TCGv_i64, TCGv_i64); |
| typedef void NeonGenTwo64OpEnvFn(TCGv_i64, TCGv_ptr, TCGv_i64, TCGv_i64); |
| typedef void NeonGenNarrowFn(TCGv_i32, TCGv_i64); |
| typedef void NeonGenNarrowEnvFn(TCGv_i32, TCGv_ptr, TCGv_i64); |
| typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); |
| typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); |
| typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); |
| typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); |
| typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32); |
| typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); |
| |
| /* initialize TCG globals. */ |
| void a64_translate_init(void) |
| { |
| int i; |
| |
| cpu_pc = tcg_global_mem_new_i64(cpu_env, |
| offsetof(CPUARMState, pc), |
| "pc"); |
| for (i = 0; i < 32; i++) { |
| cpu_X[i] = tcg_global_mem_new_i64(cpu_env, |
| offsetof(CPUARMState, xregs[i]), |
| regnames[i]); |
| } |
| |
| cpu_exclusive_high = tcg_global_mem_new_i64(cpu_env, |
| offsetof(CPUARMState, exclusive_high), "exclusive_high"); |
| } |
| |
| static inline ARMMMUIdx get_a64_user_mem_index(DisasContext *s) |
| { |
| /* Return the mmu_idx to use for A64 "unprivileged load/store" insns: |
| * if EL1, access as if EL0; otherwise access at current EL |
| */ |
| switch (s->mmu_idx) { |
| case ARMMMUIdx_S12NSE1: |
| return ARMMMUIdx_S12NSE0; |
| case ARMMMUIdx_S1SE1: |
| return ARMMMUIdx_S1SE0; |
| case ARMMMUIdx_S2NS: |
| g_assert_not_reached(); |
| default: |
| return s->mmu_idx; |
| } |
| } |
| |
| void aarch64_cpu_dump_state(CPUState *cs, FILE *f, |
| fprintf_function cpu_fprintf, int flags) |
| { |
| ARMCPU *cpu = ARM_CPU(cs); |
| CPUARMState *env = &cpu->env; |
| uint32_t psr = pstate_read(env); |
| int i; |
| int el = arm_current_el(env); |
| const char *ns_status; |
| |
| cpu_fprintf(f, "PC=%016"PRIx64" SP=%016"PRIx64"\n", |
| env->pc, env->xregs[31]); |
| for (i = 0; i < 31; i++) { |
| cpu_fprintf(f, "X%02d=%016"PRIx64, i, env->xregs[i]); |
| if ((i % 4) == 3) { |
| cpu_fprintf(f, "\n"); |
| } else { |
| cpu_fprintf(f, " "); |
| } |
| } |
| |
| if (arm_feature(env, ARM_FEATURE_EL3) && el != 3) { |
| ns_status = env->cp15.scr_el3 & SCR_NS ? "NS " : "S "; |
| } else { |
| ns_status = ""; |
| } |
| |
| cpu_fprintf(f, "\nPSTATE=%08x %c%c%c%c %sEL%d%c\n", |
| psr, |
| psr & PSTATE_N ? 'N' : '-', |
| psr & PSTATE_Z ? 'Z' : '-', |
| psr & PSTATE_C ? 'C' : '-', |
| psr & PSTATE_V ? 'V' : '-', |
| ns_status, |
| el, |
| psr & PSTATE_SP ? 'h' : 't'); |
| |
| if (flags & CPU_DUMP_FPU) { |
| int numvfpregs = 32; |
| for (i = 0; i < numvfpregs; i += 2) { |
| uint64_t vlo = float64_val(env->vfp.regs[i * 2]); |
| uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]); |
| cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ", |
| i, vhi, vlo); |
| vlo = float64_val(env->vfp.regs[(i + 1) * 2]); |
| vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]); |
| cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n", |
| i + 1, vhi, vlo); |
| } |
| cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n", |
| vfp_get_fpcr(env), vfp_get_fpsr(env)); |
| } |
| } |
| |
| void gen_a64_set_pc_im(uint64_t val) |
| { |
| tcg_gen_movi_i64(cpu_pc, val); |
| } |
| |
| typedef struct DisasCompare64 { |
| TCGCond cond; |
| TCGv_i64 value; |
| } DisasCompare64; |
| |
| static void a64_test_cc(DisasCompare64 *c64, int cc) |
| { |
| DisasCompare c32; |
| |
| arm_test_cc(&c32, cc); |
| |
| /* Sign-extend the 32-bit value so that the GE/LT comparisons work |
| * properly. The NE/EQ comparisons are also fine with this choice. */ |
| c64->cond = c32.cond; |
| c64->value = tcg_temp_new_i64(); |
| tcg_gen_ext_i32_i64(c64->value, c32.value); |
| |
| arm_free_cc(&c32); |
| } |
| |
| static void a64_free_cc(DisasCompare64 *c64) |
| { |
| tcg_temp_free_i64(c64->value); |
| } |
| |
| static void gen_exception_internal(int excp) |
| { |
| TCGv_i32 tcg_excp = tcg_const_i32(excp); |
| |
| assert(excp_is_internal(excp)); |
| gen_helper_exception_internal(cpu_env, tcg_excp); |
| tcg_temp_free_i32(tcg_excp); |
| } |
| |
| static void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) |
| { |
| TCGv_i32 tcg_excp = tcg_const_i32(excp); |
| TCGv_i32 tcg_syn = tcg_const_i32(syndrome); |
| TCGv_i32 tcg_el = tcg_const_i32(target_el); |
| |
| gen_helper_exception_with_syndrome(cpu_env, tcg_excp, |
| tcg_syn, tcg_el); |
| tcg_temp_free_i32(tcg_el); |
| tcg_temp_free_i32(tcg_syn); |
| tcg_temp_free_i32(tcg_excp); |
| } |
| |
| static void gen_exception_internal_insn(DisasContext *s, int offset, int excp) |
| { |
| gen_a64_set_pc_im(s->pc - offset); |
| gen_exception_internal(excp); |
| s->is_jmp = DISAS_EXC; |
| } |
| |
| static void gen_exception_insn(DisasContext *s, int offset, int excp, |
| uint32_t syndrome, uint32_t target_el) |
| { |
| gen_a64_set_pc_im(s->pc - offset); |
| gen_exception(excp, syndrome, target_el); |
| s->is_jmp = DISAS_EXC; |
| } |
| |
| static void gen_ss_advance(DisasContext *s) |
| { |
| /* If the singlestep state is Active-not-pending, advance to |
| * Active-pending. |
| */ |
| if (s->ss_active) { |
| s->pstate_ss = 0; |
| gen_helper_clear_pstate_ss(cpu_env); |
| } |
| } |
| |
| static void gen_step_complete_exception(DisasContext *s) |
| { |
| /* We just completed step of an insn. Move from Active-not-pending |
| * to Active-pending, and then also take the swstep exception. |
| * This corresponds to making the (IMPDEF) choice to prioritize |
| * swstep exceptions over asynchronous exceptions taken to an exception |
| * level where debug is disabled. This choice has the advantage that |
| * we do not need to maintain internal state corresponding to the |
| * ISV/EX syndrome bits between completion of the step and generation |
| * of the exception, and our syndrome information is always correct. |
| */ |
| gen_ss_advance(s); |
| gen_exception(EXCP_UDEF, syn_swstep(s->ss_same_el, 1, s->is_ldex), |
| default_exception_el(s)); |
| s->is_jmp = DISAS_EXC; |
| } |
| |
| static inline bool use_goto_tb(DisasContext *s, int n, uint64_t dest) |
| { |
| /* No direct tb linking with singlestep (either QEMU's or the ARM |
| * debug architecture kind) or deterministic io |
| */ |
| if (s->singlestep_enabled || s->ss_active || (s->tb->cflags & CF_LAST_IO)) { |
| return false; |
| } |
| |
| #ifndef CONFIG_USER_ONLY |
| /* Only link tbs from inside the same guest page */ |
| if ((s->tb->pc & TARGET_PAGE_MASK) != (dest & TARGET_PAGE_MASK)) { |
| return false; |
| } |
| #endif |
| |
| return true; |
| } |
| |
| static inline void gen_goto_tb(DisasContext *s, int n, uint64_t dest) |
| { |
| TranslationBlock *tb; |
| |
| tb = s->tb; |
| if (use_goto_tb(s, n, dest)) { |
| tcg_gen_goto_tb(n); |
| gen_a64_set_pc_im(dest); |
| tcg_gen_exit_tb((intptr_t)tb + n); |
| s->is_jmp = DISAS_TB_JUMP; |
| } else { |
| gen_a64_set_pc_im(dest); |
| if (s->ss_active) { |
| gen_step_complete_exception(s); |
| } else if (s->singlestep_enabled) { |
| gen_exception_internal(EXCP_DEBUG); |
| } else { |
| tcg_gen_exit_tb(0); |
| s->is_jmp = DISAS_TB_JUMP; |
| } |
| } |
| } |
| |
| static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) |
| { |
| /* We don't need to save all of the syndrome so we mask and shift |
| * out uneeded bits to help the sleb128 encoder do a better job. |
| */ |
| syn &= ARM_INSN_START_WORD2_MASK; |
| syn >>= ARM_INSN_START_WORD2_SHIFT; |
| |
| /* We check and clear insn_start_idx to catch multiple updates. */ |
| assert(s->insn_start_idx != 0); |
| tcg_set_insn_param(s->insn_start_idx, 2, syn); |
| s->insn_start_idx = 0; |
| } |
| |
| static void unallocated_encoding(DisasContext *s) |
| { |
| /* Unallocated and reserved encodings are uncategorized */ |
| gen_exception_insn(s, 4, EXCP_UDEF, syn_uncategorized(), |
| default_exception_el(s)); |
| } |
| |
| #define unsupported_encoding(s, insn) \ |
| do { \ |
| qemu_log_mask(LOG_UNIMP, \ |
| "%s:%d: unsupported instruction encoding 0x%08x " \ |
| "at pc=%016" PRIx64 "\n", \ |
| __FILE__, __LINE__, insn, s->pc - 4); \ |
| unallocated_encoding(s); \ |
| } while (0); |
| |
| static void init_tmp_a64_array(DisasContext *s) |
| { |
| #ifdef CONFIG_DEBUG_TCG |
| int i; |
| for (i = 0; i < ARRAY_SIZE(s->tmp_a64); i++) { |
| TCGV_UNUSED_I64(s->tmp_a64[i]); |
| } |
| #endif |
| s->tmp_a64_count = 0; |
| } |
| |
| static void free_tmp_a64(DisasContext *s) |
| { |
| int i; |
| for (i = 0; i < s->tmp_a64_count; i++) { |
| tcg_temp_free_i64(s->tmp_a64[i]); |
| } |
| init_tmp_a64_array(s); |
| } |
| |
| static TCGv_i64 new_tmp_a64(DisasContext *s) |
| { |
| assert(s->tmp_a64_count < TMP_A64_MAX); |
| return s->tmp_a64[s->tmp_a64_count++] = tcg_temp_new_i64(); |
| } |
| |
| static TCGv_i64 new_tmp_a64_zero(DisasContext *s) |
| { |
| TCGv_i64 t = new_tmp_a64(s); |
| tcg_gen_movi_i64(t, 0); |
| return t; |
| } |
| |
| /* |
| * Register access functions |
| * |
| * These functions are used for directly accessing a register in where |
| * changes to the final register value are likely to be made. If you |
| * need to use a register for temporary calculation (e.g. index type |
| * operations) use the read_* form. |
| * |
| * B1.2.1 Register mappings |
| * |
| * In instruction register encoding 31 can refer to ZR (zero register) or |
| * the SP (stack pointer) depending on context. In QEMU's case we map SP |
| * to cpu_X[31] and ZR accesses to a temporary which can be discarded. |
| * This is the point of the _sp forms. |
| */ |
| static TCGv_i64 cpu_reg(DisasContext *s, int reg) |
| { |
| if (reg == 31) { |
| return new_tmp_a64_zero(s); |
| } else { |
| return cpu_X[reg]; |
| } |
| } |
| |
| /* register access for when 31 == SP */ |
| static TCGv_i64 cpu_reg_sp(DisasContext *s, int reg) |
| { |
| return cpu_X[reg]; |
| } |
| |
| /* read a cpu register in 32bit/64bit mode. Returns a TCGv_i64 |
| * representing the register contents. This TCGv is an auto-freed |
| * temporary so it need not be explicitly freed, and may be modified. |
| */ |
| static TCGv_i64 read_cpu_reg(DisasContext *s, int reg, int sf) |
| { |
| TCGv_i64 v = new_tmp_a64(s); |
| if (reg != 31) { |
| if (sf) { |
| tcg_gen_mov_i64(v, cpu_X[reg]); |
| } else { |
| tcg_gen_ext32u_i64(v, cpu_X[reg]); |
| } |
| } else { |
| tcg_gen_movi_i64(v, 0); |
| } |
| return v; |
| } |
| |
| static TCGv_i64 read_cpu_reg_sp(DisasContext *s, int reg, int sf) |
| { |
| TCGv_i64 v = new_tmp_a64(s); |
| if (sf) { |
| tcg_gen_mov_i64(v, cpu_X[reg]); |
| } else { |
| tcg_gen_ext32u_i64(v, cpu_X[reg]); |
| } |
| return v; |
| } |
| |
| /* We should have at some point before trying to access an FP register |
| * done the necessary access check, so assert that |
| * (a) we did the check and |
| * (b) we didn't then just plough ahead anyway if it failed. |
| * Print the instruction pattern in the abort message so we can figure |
| * out what we need to fix if a user encounters this problem in the wild. |
| */ |
| static inline void assert_fp_access_checked(DisasContext *s) |
| { |
| #ifdef CONFIG_DEBUG_TCG |
| if (unlikely(!s->fp_access_checked || s->fp_excp_el)) { |
| fprintf(stderr, "target-arm: FP access check missing for " |
| "instruction 0x%08x\n", s->insn); |
| abort(); |
| } |
| #endif |
| } |
| |
| /* Return the offset into CPUARMState of an element of specified |
| * size, 'element' places in from the least significant end of |
| * the FP/vector register Qn. |
| */ |
| static inline int vec_reg_offset(DisasContext *s, int regno, |
| int element, TCGMemOp size) |
| { |
| int offs = offsetof(CPUARMState, vfp.regs[regno * 2]); |
| #ifdef HOST_WORDS_BIGENDIAN |
| /* This is complicated slightly because vfp.regs[2n] is |
| * still the low half and vfp.regs[2n+1] the high half |
| * of the 128 bit vector, even on big endian systems. |
| * Calculate the offset assuming a fully bigendian 128 bits, |
| * then XOR to account for the order of the two 64 bit halves. |
| */ |
| offs += (16 - ((element + 1) * (1 << size))); |
| offs ^= 8; |
| #else |
| offs += element * (1 << size); |
| #endif |
| assert_fp_access_checked(s); |
| return offs; |
| } |
| |
| /* Return the offset into CPUARMState of a slice (from |
| * the least significant end) of FP register Qn (ie |
| * Dn, Sn, Hn or Bn). |
| * (Note that this is not the same mapping as for A32; see cpu.h) |
| */ |
| static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size) |
| { |
| int offs = offsetof(CPUARMState, vfp.regs[regno * 2]); |
| #ifdef HOST_WORDS_BIGENDIAN |
| offs += (8 - (1 << size)); |
| #endif |
| assert_fp_access_checked(s); |
| return offs; |
| } |
| |
| /* Offset of the high half of the 128 bit vector Qn */ |
| static inline int fp_reg_hi_offset(DisasContext *s, int regno) |
| { |
| assert_fp_access_checked(s); |
| return offsetof(CPUARMState, vfp.regs[regno * 2 + 1]); |
| } |
| |
| /* Convenience accessors for reading and writing single and double |
| * FP registers. Writing clears the upper parts of the associated |
| * 128 bit vector register, as required by the architecture. |
| * Note that unlike the GP register accessors, the values returned |
| * by the read functions must be manually freed. |
| */ |
| static TCGv_i64 read_fp_dreg(DisasContext *s, int reg) |
| { |
| TCGv_i64 v = tcg_temp_new_i64(); |
| |
| tcg_gen_ld_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64)); |
| return v; |
| } |
| |
| static TCGv_i32 read_fp_sreg(DisasContext *s, int reg) |
| { |
| TCGv_i32 v = tcg_temp_new_i32(); |
| |
| tcg_gen_ld_i32(v, cpu_env, fp_reg_offset(s, reg, MO_32)); |
| return v; |
| } |
| |
| static void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) |
| { |
| TCGv_i64 tcg_zero = tcg_const_i64(0); |
| |
| tcg_gen_st_i64(v, cpu_env, fp_reg_offset(s, reg, MO_64)); |
| tcg_gen_st_i64(tcg_zero, cpu_env, fp_reg_hi_offset(s, reg)); |
| tcg_temp_free_i64(tcg_zero); |
| } |
| |
| static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) |
| { |
| TCGv_i64 tmp = tcg_temp_new_i64(); |
| |
| tcg_gen_extu_i32_i64(tmp, v); |
| write_fp_dreg(s, reg, tmp); |
| tcg_temp_free_i64(tmp); |
| } |
| |
| static TCGv_ptr get_fpstatus_ptr(void) |
| { |
| TCGv_ptr statusptr = tcg_temp_new_ptr(); |
| int offset; |
| |
| /* In A64 all instructions (both FP and Neon) use the FPCR; |
| * there is no equivalent of the A32 Neon "standard FPSCR value" |
| * and all operations use vfp.fp_status. |
| */ |
| offset = offsetof(CPUARMState, vfp.fp_status); |
| tcg_gen_addi_ptr(statusptr, cpu_env, offset); |
| return statusptr; |
| } |
| |
| /* Set ZF and NF based on a 64 bit result. This is alas fiddlier |
| * than the 32 bit equivalent. |
| */ |
| static inline void gen_set_NZ64(TCGv_i64 result) |
| { |
| tcg_gen_extr_i64_i32(cpu_ZF, cpu_NF, result); |
| tcg_gen_or_i32(cpu_ZF, cpu_ZF, cpu_NF); |
| } |
| |
| /* Set NZCV as for a logical operation: NZ as per result, CV cleared. */ |
| static inline void gen_logic_CC(int sf, TCGv_i64 result) |
| { |
| if (sf) { |
| gen_set_NZ64(result); |
| } else { |
| tcg_gen_extrl_i64_i32(cpu_ZF, result); |
| tcg_gen_mov_i32(cpu_NF, cpu_ZF); |
| } |
| tcg_gen_movi_i32(cpu_CF, 0); |
| tcg_gen_movi_i32(cpu_VF, 0); |
| } |
| |
| /* dest = T0 + T1; compute C, N, V and Z flags */ |
| static void gen_add_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) |
| { |
| if (sf) { |
| TCGv_i64 result, flag, tmp; |
| result = tcg_temp_new_i64(); |
| flag = tcg_temp_new_i64(); |
| tmp = tcg_temp_new_i64(); |
| |
| tcg_gen_movi_i64(tmp, 0); |
| tcg_gen_add2_i64(result, flag, t0, tmp, t1, tmp); |
| |
| tcg_gen_extrl_i64_i32(cpu_CF, flag); |
| |
| gen_set_NZ64(result); |
| |
| tcg_gen_xor_i64(flag, result, t0); |
| tcg_gen_xor_i64(tmp, t0, t1); |
| tcg_gen_andc_i64(flag, flag, tmp); |
| tcg_temp_free_i64(tmp); |
| tcg_gen_extrh_i64_i32(cpu_VF, flag); |
| |
| tcg_gen_mov_i64(dest, result); |
| tcg_temp_free_i64(result); |
| tcg_temp_free_i64(flag); |
| } else { |
| /* 32 bit arithmetic */ |
| TCGv_i32 t0_32 = tcg_temp_new_i32(); |
| TCGv_i32 t1_32 = tcg_temp_new_i32(); |
| TCGv_i32 tmp = tcg_temp_new_i32(); |
| |
| tcg_gen_movi_i32(tmp, 0); |
| tcg_gen_extrl_i64_i32(t0_32, t0); |
| tcg_gen_extrl_i64_i32(t1_32, t1); |
| tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, t1_32, tmp); |
| tcg_gen_mov_i32(cpu_ZF, cpu_NF); |
| tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); |
| tcg_gen_xor_i32(tmp, t0_32, t1_32); |
| tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); |
| tcg_gen_extu_i32_i64(dest, cpu_NF); |
| |
| tcg_temp_free_i32(tmp); |
| tcg_temp_free_i32(t0_32); |
| tcg_temp_free_i32(t1_32); |
| } |
| } |
| |
| /* dest = T0 - T1; compute C, N, V and Z flags */ |
| static void gen_sub_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) |
| { |
| if (sf) { |
| /* 64 bit arithmetic */ |
| TCGv_i64 result, flag, tmp; |
| |
| result = tcg_temp_new_i64(); |
| flag = tcg_temp_new_i64(); |
| tcg_gen_sub_i64(result, t0, t1); |
| |
| gen_set_NZ64(result); |
| |
| tcg_gen_setcond_i64(TCG_COND_GEU, flag, t0, t1); |
| tcg_gen_extrl_i64_i32(cpu_CF, flag); |
| |
| tcg_gen_xor_i64(flag, result, t0); |
| tmp = tcg_temp_new_i64(); |
| tcg_gen_xor_i64(tmp, t0, t1); |
| tcg_gen_and_i64(flag, flag, tmp); |
| tcg_temp_free_i64(tmp); |
| tcg_gen_extrh_i64_i32(cpu_VF, flag); |
| tcg_gen_mov_i64(dest, result); |
| tcg_temp_free_i64(flag); |
| tcg_temp_free_i64(result); |
| } else { |
| /* 32 bit arithmetic */ |
| TCGv_i32 t0_32 = tcg_temp_new_i32(); |
| TCGv_i32 t1_32 = tcg_temp_new_i32(); |
| TCGv_i32 tmp; |
| |
| tcg_gen_extrl_i64_i32(t0_32, t0); |
| tcg_gen_extrl_i64_i32(t1_32, t1); |
| tcg_gen_sub_i32(cpu_NF, t0_32, t1_32); |
| tcg_gen_mov_i32(cpu_ZF, cpu_NF); |
| tcg_gen_setcond_i32(TCG_COND_GEU, cpu_CF, t0_32, t1_32); |
| tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); |
| tmp = tcg_temp_new_i32(); |
| tcg_gen_xor_i32(tmp, t0_32, t1_32); |
| tcg_temp_free_i32(t0_32); |
| tcg_temp_free_i32(t1_32); |
| tcg_gen_and_i32(cpu_VF, cpu_VF, tmp); |
| tcg_temp_free_i32(tmp); |
| tcg_gen_extu_i32_i64(dest, cpu_NF); |
| } |
| } |
| |
| /* dest = T0 + T1 + CF; do not compute flags. */ |
| static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) |
| { |
| TCGv_i64 flag = tcg_temp_new_i64(); |
| tcg_gen_extu_i32_i64(flag, cpu_CF); |
| tcg_gen_add_i64(dest, t0, t1); |
| tcg_gen_add_i64(dest, dest, flag); |
| tcg_temp_free_i64(flag); |
| |
| if (!sf) { |
| tcg_gen_ext32u_i64(dest, dest); |
| } |
| } |
| |
| /* dest = T0 + T1 + CF; compute C, N, V and Z flags. */ |
| static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) |
| { |
| if (sf) { |
| TCGv_i64 result, cf_64, vf_64, tmp; |
| result = tcg_temp_new_i64(); |
| cf_64 = tcg_temp_new_i64(); |
| vf_64 = tcg_temp_new_i64(); |
| tmp = tcg_const_i64(0); |
| |
| tcg_gen_extu_i32_i64(cf_64, cpu_CF); |
| tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp); |
| tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp); |
| tcg_gen_extrl_i64_i32(cpu_CF, cf_64); |
| gen_set_NZ64(result); |
| |
| tcg_gen_xor_i64(vf_64, result, t0); |
| tcg_gen_xor_i64(tmp, t0, t1); |
| tcg_gen_andc_i64(vf_64, vf_64, tmp); |
| tcg_gen_extrh_i64_i32(cpu_VF, vf_64); |
| |
| tcg_gen_mov_i64(dest, result); |
| |
| tcg_temp_free_i64(tmp); |
| tcg_temp_free_i64(vf_64); |
| tcg_temp_free_i64(cf_64); |
| tcg_temp_free_i64(result); |
| } else { |
| TCGv_i32 t0_32, t1_32, tmp; |
| t0_32 = tcg_temp_new_i32(); |
| t1_32 = tcg_temp_new_i32(); |
| tmp = tcg_const_i32(0); |
| |
| tcg_gen_extrl_i64_i32(t0_32, t0); |
| tcg_gen_extrl_i64_i32(t1_32, t1); |
| tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp); |
| tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp); |
| |
| tcg_gen_mov_i32(cpu_ZF, cpu_NF); |
| tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); |
| tcg_gen_xor_i32(tmp, t0_32, t1_32); |
| tcg_gen_andc_i32(cpu_VF, cpu_VF, tmp); |
| tcg_gen_extu_i32_i64(dest, cpu_NF); |
| |
| tcg_temp_free_i32(tmp); |
| tcg_temp_free_i32(t1_32); |
| tcg_temp_free_i32(t0_32); |
| } |
| } |
| |
| /* |
| * Load/Store generators |
| */ |
| |
| /* |
| * Store from GPR register to memory. |
| */ |
| static void do_gpr_st_memidx(DisasContext *s, TCGv_i64 source, |
| TCGv_i64 tcg_addr, int size, int memidx, |
| bool iss_valid, |
| unsigned int iss_srt, |
| bool iss_sf, bool iss_ar) |
| { |
| g_assert(size <= 3); |
| tcg_gen_qemu_st_i64(source, tcg_addr, memidx, s->be_data + size); |
| |
| if (iss_valid) { |
| uint32_t syn; |
| |
| syn = syn_data_abort_with_iss(0, |
| size, |
| false, |
| iss_srt, |
| iss_sf, |
| iss_ar, |
| 0, 0, 0, 0, 0, false); |
| disas_set_insn_syndrome(s, syn); |
| } |
| } |
| |
| static void do_gpr_st(DisasContext *s, TCGv_i64 source, |
| TCGv_i64 tcg_addr, int size, |
| bool iss_valid, |
| unsigned int iss_srt, |
| bool iss_sf, bool iss_ar) |
| { |
| do_gpr_st_memidx(s, source, tcg_addr, size, get_mem_index(s), |
| iss_valid, iss_srt, iss_sf, iss_ar); |
| } |
| |
| /* |
| * Load from memory to GPR register |
| */ |
| static void do_gpr_ld_memidx(DisasContext *s, |
| TCGv_i64 dest, TCGv_i64 tcg_addr, |
| int size, bool is_signed, |
| bool extend, int memidx, |
| bool iss_valid, unsigned int iss_srt, |
| bool iss_sf, bool iss_ar) |
| { |
| TCGMemOp memop = s->be_data + size; |
| |
| g_assert(size <= 3); |
| |
| if (is_signed) { |
| memop += MO_SIGN; |
| } |
| |
| tcg_gen_qemu_ld_i64(dest, tcg_addr, memidx, memop); |
| |
| if (extend && is_signed) { |
| g_assert(size < 3); |
| tcg_gen_ext32u_i64(dest, dest); |
| } |
| |
| if (iss_valid) { |
| uint32_t syn; |
| |
| syn = syn_data_abort_with_iss(0, |
| size, |
| is_signed, |
| iss_srt, |
| iss_sf, |
| iss_ar, |
| 0, 0, 0, 0, 0, false); |
| disas_set_insn_syndrome(s, syn); |
| } |
| } |
| |
| static void do_gpr_ld(DisasContext *s, |
| TCGv_i64 dest, TCGv_i64 tcg_addr, |
| int size, bool is_signed, bool extend, |
| bool iss_valid, unsigned int iss_srt, |
| bool iss_sf, bool iss_ar) |
| { |
| do_gpr_ld_memidx(s, dest, tcg_addr, size, is_signed, extend, |
| get_mem_index(s), |
| iss_valid, iss_srt, iss_sf, iss_ar); |
| } |
| |
| /* |
| * Store from FP register to memory |
| */ |
| static void do_fp_st(DisasContext *s, int srcidx, TCGv_i64 tcg_addr, int size) |
| { |
| /* This writes the bottom N bits of a 128 bit wide vector to memory */ |
| TCGv_i64 tmp = tcg_temp_new_i64(); |
| tcg_gen_ld_i64(tmp, cpu_env, fp_reg_offset(s, srcidx, MO_64)); |
| if (size < 4) { |
| tcg_gen_qemu_st_i64(tmp, tcg_addr, get_mem_index(s), |
| s->be_data + size); |
| } else { |
| bool be = s->be_data == MO_BE; |
| TCGv_i64 tcg_hiaddr = tcg_temp_new_i64(); |
| |
| tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); |
| tcg_gen_qemu_st_i64(tmp, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), |
| s->be_data | MO_Q); |
| tcg_gen_ld_i64(tmp, cpu_env, fp_reg_hi_offset(s, srcidx)); |
| tcg_gen_qemu_st_i64(tmp, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), |
| s->be_data | MO_Q); |
| tcg_temp_free_i64(tcg_hiaddr); |
| } |
| |
| tcg_temp_free_i64(tmp); |
| } |
| |
| /* |
| * Load from memory to FP register |
| */ |
| static void do_fp_ld(DisasContext *s, int destidx, TCGv_i64 tcg_addr, int size) |
| { |
| /* This always zero-extends and writes to a full 128 bit wide vector */ |
| TCGv_i64 tmplo = tcg_temp_new_i64(); |
| TCGv_i64 tmphi; |
| |
| if (size < 4) { |
| TCGMemOp memop = s->be_data + size; |
| tmphi = tcg_const_i64(0); |
| tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); |
| } else { |
| bool be = s->be_data == MO_BE; |
| TCGv_i64 tcg_hiaddr; |
| |
| tmphi = tcg_temp_new_i64(); |
| tcg_hiaddr = tcg_temp_new_i64(); |
| |
| tcg_gen_addi_i64(tcg_hiaddr, tcg_addr, 8); |
| tcg_gen_qemu_ld_i64(tmplo, be ? tcg_hiaddr : tcg_addr, get_mem_index(s), |
| s->be_data | MO_Q); |
| tcg_gen_qemu_ld_i64(tmphi, be ? tcg_addr : tcg_hiaddr, get_mem_index(s), |
| s->be_data | MO_Q); |
| tcg_temp_free_i64(tcg_hiaddr); |
| } |
| |
| tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64)); |
| tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx)); |
| |
| tcg_temp_free_i64(tmplo); |
| tcg_temp_free_i64(tmphi); |
| } |
| |
| /* |
| * Vector load/store helpers. |
| * |
| * The principal difference between this and a FP load is that we don't |
| * zero extend as we are filling a partial chunk of the vector register. |
| * These functions don't support 128 bit loads/stores, which would be |
| * normal load/store operations. |
| * |
| * The _i32 versions are useful when operating on 32 bit quantities |
| * (eg for floating point single or using Neon helper functions). |
| */ |
| |
| /* Get value of an element within a vector register */ |
| static void read_vec_element(DisasContext *s, TCGv_i64 tcg_dest, int srcidx, |
| int element, TCGMemOp memop) |
| { |
| int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE); |
| switch (memop) { |
| case MO_8: |
| tcg_gen_ld8u_i64(tcg_dest, cpu_env, vect_off); |
| break; |
| case MO_16: |
| tcg_gen_ld16u_i64(tcg_dest, cpu_env, vect_off); |
| break; |
| case MO_32: |
| tcg_gen_ld32u_i64(tcg_dest, cpu_env, vect_off); |
| break; |
| case MO_8|MO_SIGN: |
| tcg_gen_ld8s_i64(tcg_dest, cpu_env, vect_off); |
| break; |
| case MO_16|MO_SIGN: |
| tcg_gen_ld16s_i64(tcg_dest, cpu_env, vect_off); |
| break; |
| case MO_32|MO_SIGN: |
| tcg_gen_ld32s_i64(tcg_dest, cpu_env, vect_off); |
| break; |
| case MO_64: |
| case MO_64|MO_SIGN: |
| tcg_gen_ld_i64(tcg_dest, cpu_env, vect_off); |
| break; |
| default: |
| g_assert_not_reached(); |
| } |
| } |
| |
| static void read_vec_element_i32(DisasContext *s, TCGv_i32 tcg_dest, int srcidx, |
| int element, TCGMemOp memop) |
| { |
| int vect_off = vec_reg_offset(s, srcidx, element, memop & MO_SIZE); |
| switch (memop) { |
| case MO_8: |
| tcg_gen_ld8u_i32(tcg_dest, cpu_env, vect_off); |
| break; |
| case MO_16: |
| tcg_gen_ld16u_i32(tcg_dest, cpu_env, vect_off); |
| break; |
| case MO_8|MO_SIGN: |
| tcg_gen_ld8s_i32(tcg_dest, cpu_env, vect_off); |
| break; |
| case MO_16|MO_SIGN: |
| tcg_gen_ld16s_i32(tcg_dest, cpu_env, vect_off); |
| break; |
| case MO_32: |
| case MO_32|MO_SIGN: |
| tcg_gen_ld_i32(tcg_dest, cpu_env, vect_off); |
| break; |
| default: |
| g_assert_not_reached(); |
| } |
| } |
| |
| /* Set value of an element within a vector register */ |
| static void write_vec_element(DisasContext *s, TCGv_i64 tcg_src, int destidx, |
| int element, TCGMemOp memop) |
| { |
| int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE); |
| switch (memop) { |
| case MO_8: |
| tcg_gen_st8_i64(tcg_src, cpu_env, vect_off); |
| break; |
| case MO_16: |
| tcg_gen_st16_i64(tcg_src, cpu_env, vect_off); |
| break; |
| case MO_32: |
| tcg_gen_st32_i64(tcg_src, cpu_env, vect_off); |
| break; |
| case MO_64: |
| tcg_gen_st_i64(tcg_src, cpu_env, vect_off); |
| break; |
| default: |
| g_assert_not_reached(); |
| } |
| } |
| |
| static void write_vec_element_i32(DisasContext *s, TCGv_i32 tcg_src, |
| int destidx, int element, TCGMemOp memop) |
| { |
| int vect_off = vec_reg_offset(s, destidx, element, memop & MO_SIZE); |
| switch (memop) { |
| case MO_8: |
| tcg_gen_st8_i32(tcg_src, cpu_env, vect_off); |
| break; |
| case MO_16: |
| tcg_gen_st16_i32(tcg_src, cpu_env, vect_off); |
| break; |
| case MO_32: |
| tcg_gen_st_i32(tcg_src, cpu_env, vect_off); |
| break; |
| default: |
| g_assert_not_reached(); |
| } |
| } |
| |
| /* Clear the high 64 bits of a 128 bit vector (in general non-quad |
| * vector ops all need to do this). |
| */ |
| static void clear_vec_high(DisasContext *s, int rd) |
| { |
| TCGv_i64 tcg_zero = tcg_const_i64(0); |
| |
| write_vec_element(s, tcg_zero, rd, 1, MO_64); |
| tcg_temp_free_i64(tcg_zero); |
| } |
| |
| /* Store from vector register to memory */ |
| static void do_vec_st(DisasContext *s, int srcidx, int element, |
| TCGv_i64 tcg_addr, int size) |
| { |
| TCGMemOp memop = s->be_data + size; |
| TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
| |
| read_vec_element(s, tcg_tmp, srcidx, element, size); |
| tcg_gen_qemu_st_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop); |
| |
| tcg_temp_free_i64(tcg_tmp); |
| } |
| |
| /* Load from memory to vector register */ |
| static void do_vec_ld(DisasContext *s, int destidx, int element, |
| TCGv_i64 tcg_addr, int size) |
| { |
| TCGMemOp memop = s->be_data + size; |
| TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
| |
| tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, get_mem_index(s), memop); |
| write_vec_element(s, tcg_tmp, destidx, element, size); |
| |
| tcg_temp_free_i64(tcg_tmp); |
| } |
| |
| /* Check that FP/Neon access is enabled. If it is, return |
| * true. If not, emit code to generate an appropriate exception, |
| * and return false; the caller should not emit any code for |
| * the instruction. Note that this check must happen after all |
| * unallocated-encoding checks (otherwise the syndrome information |
| * for the resulting exception will be incorrect). |
| */ |
| static inline bool fp_access_check(DisasContext *s) |
| { |
| assert(!s->fp_access_checked); |
| s->fp_access_checked = true; |
| |
| if (!s->fp_excp_el) { |
| return true; |
| } |
| |
| gen_exception_insn(s, 4, EXCP_UDEF, syn_fp_access_trap(1, 0xe, false), |
| s->fp_excp_el); |
| return false; |
| } |
| |
| /* |
| * This utility function is for doing register extension with an |
| * optional shift. You will likely want to pass a temporary for the |
| * destination register. See DecodeRegExtend() in the ARM ARM. |
| */ |
| static void ext_and_shift_reg(TCGv_i64 tcg_out, TCGv_i64 tcg_in, |
| int option, unsigned int shift) |
| { |
| int extsize = extract32(option, 0, 2); |
| bool is_signed = extract32(option, 2, 1); |
| |
| if (is_signed) { |
| switch (extsize) { |
| case 0: |
| tcg_gen_ext8s_i64(tcg_out, tcg_in); |
| break; |
| case 1: |
| tcg_gen_ext16s_i64(tcg_out, tcg_in); |
| break; |
| case 2: |
| tcg_gen_ext32s_i64(tcg_out, tcg_in); |
| break; |
| case 3: |
| tcg_gen_mov_i64(tcg_out, tcg_in); |
| break; |
| } |
| } else { |
| switch (extsize) { |
| case 0: |
| tcg_gen_ext8u_i64(tcg_out, tcg_in); |
| break; |
| case 1: |
| tcg_gen_ext16u_i64(tcg_out, tcg_in); |
| break; |
| case 2: |
| tcg_gen_ext32u_i64(tcg_out, tcg_in); |
| break; |
| case 3: |
| tcg_gen_mov_i64(tcg_out, tcg_in); |
| break; |
| } |
| } |
| |
| if (shift) { |
| tcg_gen_shli_i64(tcg_out, tcg_out, shift); |
| } |
| } |
| |
| static inline void gen_check_sp_alignment(DisasContext *s) |
| { |
| /* The AArch64 architecture mandates that (if enabled via PSTATE |
| * or SCTLR bits) there is a check that SP is 16-aligned on every |
| * SP-relative load or store (with an exception generated if it is not). |
| * In line with general QEMU practice regarding misaligned accesses, |
| * we omit these checks for the sake of guest program performance. |
| * This function is provided as a hook so we can more easily add these |
| * checks in future (possibly as a "favour catching guest program bugs |
| * over speed" user selectable option). |
| */ |
| } |
| |
| /* |
| * This provides a simple table based table lookup decoder. It is |
| * intended to be used when the relevant bits for decode are too |
| * awkwardly placed and switch/if based logic would be confusing and |
| * deeply nested. Since it's a linear search through the table, tables |
| * should be kept small. |
| * |
| * It returns the first handler where insn & mask == pattern, or |
| * NULL if there is no match. |
| * The table is terminated by an empty mask (i.e. 0) |
| */ |
| static inline AArch64DecodeFn *lookup_disas_fn(const AArch64DecodeTable *table, |
| uint32_t insn) |
| { |
| const AArch64DecodeTable *tptr = table; |
| |
| while (tptr->mask) { |
| if ((insn & tptr->mask) == tptr->pattern) { |
| return tptr->disas_fn; |
| } |
| tptr++; |
| } |
| return NULL; |
| } |
| |
| /* |
| * the instruction disassembly implemented here matches |
| * the instruction encoding classifications in chapter 3 (C3) |
| * of the ARM Architecture Reference Manual (DDI0487A_a) |
| */ |
| |
| /* C3.2.7 Unconditional branch (immediate) |
| * 31 30 26 25 0 |
| * +----+-----------+-------------------------------------+ |
| * | op | 0 0 1 0 1 | imm26 | |
| * +----+-----------+-------------------------------------+ |
| */ |
| static void disas_uncond_b_imm(DisasContext *s, uint32_t insn) |
| { |
| uint64_t addr = s->pc + sextract32(insn, 0, 26) * 4 - 4; |
| |
| if (insn & (1U << 31)) { |
| /* C5.6.26 BL Branch with link */ |
| tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); |
| } |
| |
| /* C5.6.20 B Branch / C5.6.26 BL Branch with link */ |
| gen_goto_tb(s, 0, addr); |
| } |
| |
| /* C3.2.1 Compare & branch (immediate) |
| * 31 30 25 24 23 5 4 0 |
| * +----+-------------+----+---------------------+--------+ |
| * | sf | 0 1 1 0 1 0 | op | imm19 | Rt | |
| * +----+-------------+----+---------------------+--------+ |
| */ |
| static void disas_comp_b_imm(DisasContext *s, uint32_t insn) |
| { |
| unsigned int sf, op, rt; |
| uint64_t addr; |
| TCGLabel *label_match; |
| TCGv_i64 tcg_cmp; |
| |
| sf = extract32(insn, 31, 1); |
| op = extract32(insn, 24, 1); /* 0: CBZ; 1: CBNZ */ |
| rt = extract32(insn, 0, 5); |
| addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; |
| |
| tcg_cmp = read_cpu_reg(s, rt, sf); |
| label_match = gen_new_label(); |
| |
| tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, |
| tcg_cmp, 0, label_match); |
| |
| gen_goto_tb(s, 0, s->pc); |
| gen_set_label(label_match); |
| gen_goto_tb(s, 1, addr); |
| } |
| |
| /* C3.2.5 Test & branch (immediate) |
| * 31 30 25 24 23 19 18 5 4 0 |
| * +----+-------------+----+-------+-------------+------+ |
| * | b5 | 0 1 1 0 1 1 | op | b40 | imm14 | Rt | |
| * +----+-------------+----+-------+-------------+------+ |
| */ |
| static void disas_test_b_imm(DisasContext *s, uint32_t insn) |
| { |
| unsigned int bit_pos, op, rt; |
| uint64_t addr; |
| TCGLabel *label_match; |
| TCGv_i64 tcg_cmp; |
| |
| bit_pos = (extract32(insn, 31, 1) << 5) | extract32(insn, 19, 5); |
| op = extract32(insn, 24, 1); /* 0: TBZ; 1: TBNZ */ |
| addr = s->pc + sextract32(insn, 5, 14) * 4 - 4; |
| rt = extract32(insn, 0, 5); |
| |
| tcg_cmp = tcg_temp_new_i64(); |
| tcg_gen_andi_i64(tcg_cmp, cpu_reg(s, rt), (1ULL << bit_pos)); |
| label_match = gen_new_label(); |
| tcg_gen_brcondi_i64(op ? TCG_COND_NE : TCG_COND_EQ, |
| tcg_cmp, 0, label_match); |
| tcg_temp_free_i64(tcg_cmp); |
| gen_goto_tb(s, 0, s->pc); |
| gen_set_label(label_match); |
| gen_goto_tb(s, 1, addr); |
| } |
| |
| /* C3.2.2 / C5.6.19 Conditional branch (immediate) |
| * 31 25 24 23 5 4 3 0 |
| * +---------------+----+---------------------+----+------+ |
| * | 0 1 0 1 0 1 0 | o1 | imm19 | o0 | cond | |
| * +---------------+----+---------------------+----+------+ |
| */ |
| static void disas_cond_b_imm(DisasContext *s, uint32_t insn) |
| { |
| unsigned int cond; |
| uint64_t addr; |
| |
| if ((insn & (1 << 4)) || (insn & (1 << 24))) { |
| unallocated_encoding(s); |
| return; |
| } |
| addr = s->pc + sextract32(insn, 5, 19) * 4 - 4; |
| cond = extract32(insn, 0, 4); |
| |
| if (cond < 0x0e) { |
| /* genuinely conditional branches */ |
| TCGLabel *label_match = gen_new_label(); |
| arm_gen_test_cc(cond, label_match); |
| gen_goto_tb(s, 0, s->pc); |
| gen_set_label(label_match); |
| gen_goto_tb(s, 1, addr); |
| } else { |
| /* 0xe and 0xf are both "always" conditions */ |
| gen_goto_tb(s, 0, addr); |
| } |
| } |
| |
| /* C5.6.68 HINT */ |
| static void handle_hint(DisasContext *s, uint32_t insn, |
| unsigned int op1, unsigned int op2, unsigned int crm) |
| { |
| unsigned int selector = crm << 3 | op2; |
| |
| if (op1 != 3) { |
| unallocated_encoding(s); |
| return; |
| } |
| |
| switch (selector) { |
| case 0: /* NOP */ |
| return; |
| case 3: /* WFI */ |
| s->is_jmp = DISAS_WFI; |
| return; |
| case 1: /* YIELD */ |
| s->is_jmp = DISAS_YIELD; |
| return; |
| case 2: /* WFE */ |
| s->is_jmp = DISAS_WFE; |
| return; |
| case 4: /* SEV */ |
| case 5: /* SEVL */ |
| /* we treat all as NOP at least for now */ |
| return; |
| default: |
| /* default specified as NOP equivalent */ |
| return; |
| } |
| } |
| |
| static void gen_clrex(DisasContext *s, uint32_t insn) |
| { |
| tcg_gen_movi_i64(cpu_exclusive_addr, -1); |
| } |
| |
| /* CLREX, DSB, DMB, ISB */ |
| static void handle_sync(DisasContext *s, uint32_t insn, |
| unsigned int op1, unsigned int op2, unsigned int crm) |
| { |
| if (op1 != 3) { |
| unallocated_encoding(s); |
| return; |
| } |
| |
| switch (op2) { |
| case 2: /* CLREX */ |
| gen_clrex(s, insn); |
| return; |
| case 4: /* DSB */ |
| case 5: /* DMB */ |
| /* We don't emulate caches so barriers are no-ops */ |
| return; |
| case 6: /* ISB */ |
| /* We need to break the TB after this insn to execute |
| * a self-modified code correctly and also to take |
| * any pending interrupts immediately. |
| */ |
| s->is_jmp = DISAS_UPDATE; |
| return; |
| default: |
| unallocated_encoding(s); |
| return; |
| } |
| } |
| |
| /* C5.6.130 MSR (immediate) - move immediate to processor state field */ |
| static void handle_msr_i(DisasContext *s, uint32_t insn, |
| unsigned int op1, unsigned int op2, unsigned int crm) |
| { |
| int op = op1 << 3 | op2; |
| switch (op) { |
| case 0x05: /* SPSel */ |
| if (s->current_el == 0) { |
| unallocated_encoding(s); |
| return; |
| } |
| /* fall through */ |
| case 0x1e: /* DAIFSet */ |
| case 0x1f: /* DAIFClear */ |
| { |
| TCGv_i32 tcg_imm = tcg_const_i32(crm); |
| TCGv_i32 tcg_op = tcg_const_i32(op); |
| gen_a64_set_pc_im(s->pc - 4); |
| gen_helper_msr_i_pstate(cpu_env, tcg_op, tcg_imm); |
| tcg_temp_free_i32(tcg_imm); |
| tcg_temp_free_i32(tcg_op); |
| s->is_jmp = DISAS_UPDATE; |
| break; |
| } |
| default: |
| unallocated_encoding(s); |
| return; |
| } |
| } |
| |
| static void gen_get_nzcv(TCGv_i64 tcg_rt) |
| { |
| TCGv_i32 tmp = tcg_temp_new_i32(); |
| TCGv_i32 nzcv = tcg_temp_new_i32(); |
| |
| /* build bit 31, N */ |
| tcg_gen_andi_i32(nzcv, cpu_NF, (1U << 31)); |
| /* build bit 30, Z */ |
| tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_ZF, 0); |
| tcg_gen_deposit_i32(nzcv, nzcv, tmp, 30, 1); |
| /* build bit 29, C */ |
| tcg_gen_deposit_i32(nzcv, nzcv, cpu_CF, 29, 1); |
| /* build bit 28, V */ |
| tcg_gen_shri_i32(tmp, cpu_VF, 31); |
| tcg_gen_deposit_i32(nzcv, nzcv, tmp, 28, 1); |
| /* generate result */ |
| tcg_gen_extu_i32_i64(tcg_rt, nzcv); |
| |
| tcg_temp_free_i32(nzcv); |
| tcg_temp_free_i32(tmp); |
| } |
| |
| static void gen_set_nzcv(TCGv_i64 tcg_rt) |
| |
| { |
| TCGv_i32 nzcv = tcg_temp_new_i32(); |
| |
| /* take NZCV from R[t] */ |
| tcg_gen_extrl_i64_i32(nzcv, tcg_rt); |
| |
| /* bit 31, N */ |
| tcg_gen_andi_i32(cpu_NF, nzcv, (1U << 31)); |
| /* bit 30, Z */ |
| tcg_gen_andi_i32(cpu_ZF, nzcv, (1 << 30)); |
| tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_ZF, cpu_ZF, 0); |
| /* bit 29, C */ |
| tcg_gen_andi_i32(cpu_CF, nzcv, (1 << 29)); |
| tcg_gen_shri_i32(cpu_CF, cpu_CF, 29); |
| /* bit 28, V */ |
| tcg_gen_andi_i32(cpu_VF, nzcv, (1 << 28)); |
| tcg_gen_shli_i32(cpu_VF, cpu_VF, 3); |
| tcg_temp_free_i32(nzcv); |
| } |
| |
| /* C5.6.129 MRS - move from system register |
| * C5.6.131 MSR (register) - move to system register |
| * C5.6.204 SYS |
| * C5.6.205 SYSL |
| * These are all essentially the same insn in 'read' and 'write' |
| * versions, with varying op0 fields. |
| */ |
| static void handle_sys(DisasContext *s, uint32_t insn, bool isread, |
| unsigned int op0, unsigned int op1, unsigned int op2, |
| unsigned int crn, unsigned int crm, unsigned int rt) |
| { |
| const ARMCPRegInfo *ri; |
| TCGv_i64 tcg_rt; |
| |
| ri = get_arm_cp_reginfo(s->cp_regs, |
| ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, |
| crn, crm, op0, op1, op2)); |
| |
| if (!ri) { |
| /* Unknown register; this might be a guest error or a QEMU |
| * unimplemented feature. |
| */ |
| qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 " |
| "system register op0:%d op1:%d crn:%d crm:%d op2:%d\n", |
| isread ? "read" : "write", op0, op1, crn, crm, op2); |
| unallocated_encoding(s); |
| return; |
| } |
| |
| /* Check access permissions */ |
| if (!cp_access_ok(s->current_el, ri, isread)) { |
| unallocated_encoding(s); |
| return; |
| } |
| |
| if (ri->accessfn) { |
| /* Emit code to perform further access permissions checks at |
| * runtime; this may result in an exception. |
| */ |
| TCGv_ptr tmpptr; |
| TCGv_i32 tcg_syn, tcg_isread; |
| uint32_t syndrome; |
| |
| gen_a64_set_pc_im(s->pc - 4); |
| tmpptr = tcg_const_ptr(ri); |
| syndrome = syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isread); |
| tcg_syn = tcg_const_i32(syndrome); |
| tcg_isread = tcg_const_i32(isread); |
| gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isread); |
| tcg_temp_free_ptr(tmpptr); |
| tcg_temp_free_i32(tcg_syn); |
| tcg_temp_free_i32(tcg_isread); |
| } |
| |
| /* Handle special cases first */ |
| switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { |
| case ARM_CP_NOP: |
| return; |
| case ARM_CP_NZCV: |
| tcg_rt = cpu_reg(s, rt); |
| if (isread) { |
| gen_get_nzcv(tcg_rt); |
| } else { |
| gen_set_nzcv(tcg_rt); |
| } |
| return; |
| case ARM_CP_CURRENTEL: |
| /* Reads as current EL value from pstate, which is |
| * guaranteed to be constant by the tb flags. |
| */ |
| tcg_rt = cpu_reg(s, rt); |
| tcg_gen_movi_i64(tcg_rt, s->current_el << 2); |
| return; |
| case ARM_CP_DC_ZVA: |
| /* Writes clear the aligned block of memory which rt points into. */ |
| tcg_rt = cpu_reg(s, rt); |
| gen_helper_dc_zva(cpu_env, tcg_rt); |
| return; |
| default: |
| break; |
| } |
| |
| if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { |
| gen_io_start(); |
| } |
| |
| tcg_rt = cpu_reg(s, rt); |
| |
| if (isread) { |
| if (ri->type & ARM_CP_CONST) { |
| tcg_gen_movi_i64(tcg_rt, ri->resetvalue); |
| } else if (ri->readfn) { |
| TCGv_ptr tmpptr; |
| tmpptr = tcg_const_ptr(ri); |
| gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr); |
| tcg_temp_free_ptr(tmpptr); |
| } else { |
| tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset); |
| } |
| } else { |
| if (ri->type & ARM_CP_CONST) { |
| /* If not forbidden by access permissions, treat as WI */ |
| return; |
| } else if (ri->writefn) { |
| TCGv_ptr tmpptr; |
| tmpptr = tcg_const_ptr(ri); |
| gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt); |
| tcg_temp_free_ptr(tmpptr); |
| } else { |
| tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset); |
| } |
| } |
| |
| if ((s->tb->cflags & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { |
| /* I/O operations must end the TB here (whether read or write) */ |
| gen_io_end(); |
| s->is_jmp = DISAS_UPDATE; |
| } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { |
| /* We default to ending the TB on a coprocessor register write, |
| * but allow this to be suppressed by the register definition |
| * (usually only necessary to work around guest bugs). |
| */ |
| s->is_jmp = DISAS_UPDATE; |
| } |
| } |
| |
| /* C3.2.4 System |
| * 31 22 21 20 19 18 16 15 12 11 8 7 5 4 0 |
| * +---------------------+---+-----+-----+-------+-------+-----+------+ |
| * | 1 1 0 1 0 1 0 1 0 0 | L | op0 | op1 | CRn | CRm | op2 | Rt | |
| * +---------------------+---+-----+-----+-------+-------+-----+------+ |
| */ |
| static void disas_system(DisasContext *s, uint32_t insn) |
| { |
| unsigned int l, op0, op1, crn, crm, op2, rt; |
| l = extract32(insn, 21, 1); |
| op0 = extract32(insn, 19, 2); |
| op1 = extract32(insn, 16, 3); |
| crn = extract32(insn, 12, 4); |
| crm = extract32(insn, 8, 4); |
| op2 = extract32(insn, 5, 3); |
| rt = extract32(insn, 0, 5); |
| |
| if (op0 == 0) { |
| if (l || rt != 31) { |
| unallocated_encoding(s); |
| return; |
| } |
| switch (crn) { |
| case 2: /* C5.6.68 HINT */ |
| handle_hint(s, insn, op1, op2, crm); |
| break; |
| case 3: /* CLREX, DSB, DMB, ISB */ |
| handle_sync(s, insn, op1, op2, crm); |
| break; |
| case 4: /* C5.6.130 MSR (immediate) */ |
| handle_msr_i(s, insn, op1, op2, crm); |
| break; |
| default: |
| unallocated_encoding(s); |
| break; |
| } |
| return; |
| } |
| handle_sys(s, insn, l, op0, op1, op2, crn, crm, rt); |
| } |
| |
| /* C3.2.3 Exception generation |
| * |
| * 31 24 23 21 20 5 4 2 1 0 |
| * +-----------------+-----+------------------------+-----+----+ |
| * | 1 1 0 1 0 1 0 0 | opc | imm16 | op2 | LL | |
| * +-----------------------+------------------------+----------+ |
| */ |
| static void disas_exc(DisasContext *s, uint32_t insn) |
| { |
| int opc = extract32(insn, 21, 3); |
| int op2_ll = extract32(insn, 0, 5); |
| int imm16 = extract32(insn, 5, 16); |
| TCGv_i32 tmp; |
| |
| switch (opc) { |
| case 0: |
| /* For SVC, HVC and SMC we advance the single-step state |
| * machine before taking the exception. This is architecturally |
| * mandated, to ensure that single-stepping a system call |
| * instruction works properly. |
| */ |
| switch (op2_ll) { |
| case 1: |
| gen_ss_advance(s); |
| gen_exception_insn(s, 0, EXCP_SWI, syn_aa64_svc(imm16), |
| default_exception_el(s)); |
| break; |
| case 2: |
| if (s->current_el == 0) { |
| unallocated_encoding(s); |
| break; |
| } |
| /* The pre HVC helper handles cases when HVC gets trapped |
| * as an undefined insn by runtime configuration. |
| */ |
| gen_a64_set_pc_im(s->pc - 4); |
| gen_helper_pre_hvc(cpu_env); |
| gen_ss_advance(s); |
| gen_exception_insn(s, 0, EXCP_HVC, syn_aa64_hvc(imm16), 2); |
| break; |
| case 3: |
| if (s->current_el == 0) { |
| unallocated_encoding(s); |
| break; |
| } |
| gen_a64_set_pc_im(s->pc - 4); |
| tmp = tcg_const_i32(syn_aa64_smc(imm16)); |
| gen_helper_pre_smc(cpu_env, tmp); |
| tcg_temp_free_i32(tmp); |
| gen_ss_advance(s); |
| gen_exception_insn(s, 0, EXCP_SMC, syn_aa64_smc(imm16), 3); |
| break; |
| default: |
| unallocated_encoding(s); |
| break; |
| } |
| break; |
| case 1: |
| if (op2_ll != 0) { |
| unallocated_encoding(s); |
| break; |
| } |
| /* BRK */ |
| gen_exception_insn(s, 4, EXCP_BKPT, syn_aa64_bkpt(imm16), |
| default_exception_el(s)); |
| break; |
| case 2: |
| if (op2_ll != 0) { |
| unallocated_encoding(s); |
| break; |
| } |
| /* HLT. This has two purposes. |
| * Architecturally, it is an external halting debug instruction. |
| * Since QEMU doesn't implement external debug, we treat this as |
| * it is required for halting debug disabled: it will UNDEF. |
| * Secondly, "HLT 0xf000" is the A64 semihosting syscall instruction. |
| */ |
| if (semihosting_enabled() && imm16 == 0xf000) { |
| #ifndef CONFIG_USER_ONLY |
| /* In system mode, don't allow userspace access to semihosting, |
| * to provide some semblance of security (and for consistency |
| * with our 32-bit semihosting). |
| */ |
| if (s->current_el == 0) { |
| unsupported_encoding(s, insn); |
| break; |
| } |
| #endif |
| gen_exception_internal_insn(s, 0, EXCP_SEMIHOST); |
| } else { |
| unsupported_encoding(s, insn); |
| } |
| break; |
| case 5: |
| if (op2_ll < 1 || op2_ll > 3) { |
| unallocated_encoding(s); |
| break; |
| } |
| /* DCPS1, DCPS2, DCPS3 */ |
| unsupported_encoding(s, insn); |
| break; |
| default: |
| unallocated_encoding(s); |
| break; |
| } |
| } |
| |
| /* C3.2.7 Unconditional branch (register) |
| * 31 25 24 21 20 16 15 10 9 5 4 0 |
| * +---------------+-------+-------+-------+------+-------+ |
| * | 1 1 0 1 0 1 1 | opc | op2 | op3 | Rn | op4 | |
| * +---------------+-------+-------+-------+------+-------+ |
| */ |
| static void disas_uncond_b_reg(DisasContext *s, uint32_t insn) |
| { |
| unsigned int opc, op2, op3, rn, op4; |
| |
| opc = extract32(insn, 21, 4); |
| op2 = extract32(insn, 16, 5); |
| op3 = extract32(insn, 10, 6); |
| rn = extract32(insn, 5, 5); |
| op4 = extract32(insn, 0, 5); |
| |
| if (op4 != 0x0 || op3 != 0x0 || op2 != 0x1f) { |
| unallocated_encoding(s); |
| return; |
| } |
| |
| switch (opc) { |
| case 0: /* BR */ |
| case 2: /* RET */ |
| tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn)); |
| break; |
| case 1: /* BLR */ |
| tcg_gen_mov_i64(cpu_pc, cpu_reg(s, rn)); |
| tcg_gen_movi_i64(cpu_reg(s, 30), s->pc); |
| break; |
| case 4: /* ERET */ |
| if (s->current_el == 0) { |
| unallocated_encoding(s); |
| return; |
| } |
| gen_helper_exception_return(cpu_env); |
| s->is_jmp = DISAS_JUMP; |
| return; |
| case 5: /* DRPS */ |
| if (rn != 0x1f) { |
| unallocated_encoding(s); |
| } else { |
| unsupported_encoding(s, insn); |
| } |
| return; |
| default: |
| unallocated_encoding(s); |
| return; |
| } |
| |
| s->is_jmp = DISAS_JUMP; |
| } |
| |
| /* C3.2 Branches, exception generating and system instructions */ |
| static void disas_b_exc_sys(DisasContext *s, uint32_t insn) |
| { |
| switch (extract32(insn, 25, 7)) { |
| case 0x0a: case 0x0b: |
| case 0x4a: case 0x4b: /* Unconditional branch (immediate) */ |
| disas_uncond_b_imm(s, insn); |
| break; |
| case 0x1a: case 0x5a: /* Compare & branch (immediate) */ |
| disas_comp_b_imm(s, insn); |
| break; |
| case 0x1b: case 0x5b: /* Test & branch (immediate) */ |
| disas_test_b_imm(s, insn); |
| break; |
| case 0x2a: /* Conditional branch (immediate) */ |
| disas_cond_b_imm(s, insn); |
| break; |
| case 0x6a: /* Exception generation / System */ |
| if (insn & (1 << 24)) { |
| disas_system(s, insn); |
| } else { |
| disas_exc(s, insn); |
| } |
| break; |
| case 0x6b: /* Unconditional branch (register) */ |
| disas_uncond_b_reg(s, insn); |
| break; |
| default: |
| unallocated_encoding(s); |
| break; |
| } |
| } |
| |
| /* |
| * Load/Store exclusive instructions are implemented by remembering |
| * the value/address loaded, and seeing if these are the same |
| * when the store is performed. This is not actually the architecturally |
| * mandated semantics, but it works for typical guest code sequences |
| * and avoids having to monitor regular stores. |
| * |
| * In system emulation mode only one CPU will be running at once, so |
| * this sequence is effectively atomic. In user emulation mode we |
| * throw an exception and handle the atomic operation elsewhere. |
| */ |
| static void gen_load_exclusive(DisasContext *s, int rt, int rt2, |
| TCGv_i64 addr, int size, bool is_pair) |
| { |
| TCGv_i64 tmp = tcg_temp_new_i64(); |
| TCGMemOp memop = s->be_data + size; |
| |
| g_assert(size <= 3); |
| tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), memop); |
| |
| if (is_pair) { |
| TCGv_i64 addr2 = tcg_temp_new_i64(); |
| TCGv_i64 hitmp = tcg_temp_new_i64(); |
| |
| g_assert(size >= 2); |
| tcg_gen_addi_i64(addr2, addr, 1 << size); |
| tcg_gen_qemu_ld_i64(hitmp, addr2, get_mem_index(s), memop); |
| tcg_temp_free_i64(addr2); |
| tcg_gen_mov_i64(cpu_exclusive_high, hitmp); |
| tcg_gen_mov_i64(cpu_reg(s, rt2), hitmp); |
| tcg_temp_free_i64(hitmp); |
| } |
| |
| tcg_gen_mov_i64(cpu_exclusive_val, tmp); |
| tcg_gen_mov_i64(cpu_reg(s, rt), tmp); |
| |
| tcg_temp_free_i64(tmp); |
| tcg_gen_mov_i64(cpu_exclusive_addr, addr); |
| } |
| |
| #ifdef CONFIG_USER_ONLY |
| static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, |
| TCGv_i64 addr, int size, int is_pair) |
| { |
| tcg_gen_mov_i64(cpu_exclusive_test, addr); |
| tcg_gen_movi_i32(cpu_exclusive_info, |
| size | is_pair << 2 | (rd << 4) | (rt << 9) | (rt2 << 14)); |
| gen_exception_internal_insn(s, 4, EXCP_STREX); |
| } |
| #else |
| static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2, |
| TCGv_i64 inaddr, int size, int is_pair) |
| { |
| /* if (env->exclusive_addr == addr && env->exclusive_val == [addr] |
| * && (!is_pair || env->exclusive_high == [addr + datasize])) { |
| * [addr] = {Rt}; |
| * if (is_pair) { |
| * [addr + datasize] = {Rt2}; |
| * } |
| * {Rd} = 0; |
| * } else { |
| * {Rd} = 1; |
| * } |
| * env->exclusive_addr = -1; |
| */ |
| TCGLabel *fail_label = gen_new_label(); |
| TCGLabel *done_label = gen_new_label(); |
| TCGv_i64 addr = tcg_temp_local_new_i64(); |
| TCGv_i64 tmp; |
| |
| /* Copy input into a local temp so it is not trashed when the |
| * basic block ends at the branch insn. |
| */ |
| tcg_gen_mov_i64(addr, inaddr); |
| tcg_gen_brcond_i64(TCG_COND_NE, addr, cpu_exclusive_addr, fail_label); |
| |
| tmp = tcg_temp_new_i64(); |
| tcg_gen_qemu_ld_i64(tmp, addr, get_mem_index(s), s->be_data + size); |
| tcg_gen_brcond_i64(TCG_COND_NE, tmp, cpu_exclusive_val, fail_label); |
| tcg_temp_free_i64(tmp); |
| |
| if (is_pair) { |
| TCGv_i64 addrhi = tcg_temp_new_i64(); |
| TCGv_i64 tmphi = tcg_temp_new_i64(); |
| |
| tcg_gen_addi_i64(addrhi, addr, 1 << size); |
| tcg_gen_qemu_ld_i64(tmphi, addrhi, get_mem_index(s), |
| s->be_data + size); |
| tcg_gen_brcond_i64(TCG_COND_NE, tmphi, cpu_exclusive_high, fail_label); |
| |
| tcg_temp_free_i64(tmphi); |
| tcg_temp_free_i64(addrhi); |
| } |
| |
| /* We seem to still have the exclusive monitor, so do the store */ |
| tcg_gen_qemu_st_i64(cpu_reg(s, rt), addr, get_mem_index(s), |
| s->be_data + size); |
| if (is_pair) { |
| TCGv_i64 addrhi = tcg_temp_new_i64(); |
| |
| tcg_gen_addi_i64(addrhi, addr, 1 << size); |
| tcg_gen_qemu_st_i64(cpu_reg(s, rt2), addrhi, |
| get_mem_index(s), s->be_data + size); |
| tcg_temp_free_i64(addrhi); |
| } |
| |
| tcg_temp_free_i64(addr); |
| |
| tcg_gen_movi_i64(cpu_reg(s, rd), 0); |
| tcg_gen_br(done_label); |
| gen_set_label(fail_label); |
| tcg_gen_movi_i64(cpu_reg(s, rd), 1); |
| gen_set_label(done_label); |
| tcg_gen_movi_i64(cpu_exclusive_addr, -1); |
| |
| } |
| #endif |
| |
| /* Update the Sixty-Four bit (SF) registersize. This logic is derived |
| * from the ARMv8 specs for LDR (Shared decode for all encodings). |
| */ |
| static bool disas_ldst_compute_iss_sf(int size, bool is_signed, int opc) |
| { |
| int opc0 = extract32(opc, 0, 1); |
| int regsize; |
| |
| if (is_signed) { |
| regsize = opc0 ? 32 : 64; |
| } else { |
| regsize = size == 3 ? 64 : 32; |
| } |
| return regsize == 64; |
| } |
| |
| /* C3.3.6 Load/store exclusive |
| * |
| * 31 30 29 24 23 22 21 20 16 15 14 10 9 5 4 0 |
| * +-----+-------------+----+---+----+------+----+-------+------+------+ |
| * | sz | 0 0 1 0 0 0 | o2 | L | o1 | Rs | o0 | Rt2 | Rn | Rt | |
| * +-----+-------------+----+---+----+------+----+-------+------+------+ |
| * |
| * sz: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64 bit |
| * L: 0 -> store, 1 -> load |
| * o2: 0 -> exclusive, 1 -> not |
| * o1: 0 -> single register, 1 -> register pair |
| * o0: 1 -> load-acquire/store-release, 0 -> not |
| */ |
| static void disas_ldst_excl(DisasContext *s, uint32_t insn) |
| { |
| int rt = extract32(insn, 0, 5); |
| int rn = extract32(insn, 5, 5); |
| int rt2 = extract32(insn, 10, 5); |
| int is_lasr = extract32(insn, 15, 1); |
| int rs = extract32(insn, 16, 5); |
| int is_pair = extract32(insn, 21, 1); |
| int is_store = !extract32(insn, 22, 1); |
| int is_excl = !extract32(insn, 23, 1); |
| int size = extract32(insn, 30, 2); |
| TCGv_i64 tcg_addr; |
| |
| if ((!is_excl && !is_pair && !is_lasr) || |
| (!is_excl && is_pair) || |
| (is_pair && size < 2)) { |
| unallocated_encoding(s); |
| return; |
| } |
| |
| if (rn == 31) { |
| gen_check_sp_alignment(s); |
| } |
| tcg_addr = read_cpu_reg_sp(s, rn, 1); |
| |
| /* Note that since TCG is single threaded load-acquire/store-release |
| * semantics require no extra if (is_lasr) { ... } handling. |
| */ |
| |
| if (is_excl) { |
| if (!is_store) { |
| s->is_ldex = true; |
| gen_load_exclusive(s, rt, rt2, tcg_addr, size, is_pair); |
| } else { |
| gen_store_exclusive(s, rs, rt, rt2, tcg_addr, size, is_pair); |
| } |
| } else { |
| TCGv_i64 tcg_rt = cpu_reg(s, rt); |
| bool iss_sf = disas_ldst_compute_iss_sf(size, false, 0); |
| |
| /* Generate ISS for non-exclusive accesses including LASR. */ |
| if (is_store) { |
| do_gpr_st(s, tcg_rt, tcg_addr, size, |
| true, rt, iss_sf, is_lasr); |
| } else { |
| do_gpr_ld(s, tcg_rt, tcg_addr, size, false, false, |
| true, rt, iss_sf, is_lasr); |
| } |
| } |
| } |
| |
| /* |
| * C3.3.5 Load register (literal) |
| * |
| * 31 30 29 27 26 25 24 23 5 4 0 |
| * +-----+-------+---+-----+-------------------+-------+ |
| * | opc | 0 1 1 | V | 0 0 | imm19 | Rt | |
| * +-----+-------+---+-----+-------------------+-------+ |
| * |
| * V: 1 -> vector (simd/fp) |
| * opc (non-vector): 00 -> 32 bit, 01 -> 64 bit, |
| * 10-> 32 bit signed, 11 -> prefetch |
| * opc (vector): 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit (11 unallocated) |
| */ |
| static void disas_ld_lit(DisasContext *s, uint32_t insn) |
| { |
| int rt = extract32(insn, 0, 5); |
| int64_t imm = sextract32(insn, 5, 19) << 2; |
| bool is_vector = extract32(insn, 26, 1); |
| int opc = extract32(insn, 30, 2); |
| bool is_signed = false; |
| int size = 2; |
| TCGv_i64 tcg_rt, tcg_addr; |
| |
| if (is_vector) { |
| if (opc == 3) { |
| unallocated_encoding(s); |
| return; |
| } |
| size = 2 + opc; |
| if (!fp_access_check(s)) { |
| return; |
| } |
| } else { |
| if (opc == 3) { |
| /* PRFM (literal) : prefetch */ |
| return; |
| } |
| size = 2 + extract32(opc, 0, 1); |
| is_signed = extract32(opc, 1, 1); |
| } |
| |
| tcg_rt = cpu_reg(s, rt); |
| |
| tcg_addr = tcg_const_i64((s->pc - 4) + imm); |
| if (is_vector) { |
| do_fp_ld(s, rt, tcg_addr, size); |
| } else { |
| /* Only unsigned 32bit loads target 32bit registers. */ |
| bool iss_sf = opc == 0 ? 32 : 64; |
| |
| do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false, |
| true, rt, iss_sf, false); |
| } |
| tcg_temp_free_i64(tcg_addr); |
| } |
| |
| /* |
| * C5.6.80 LDNP (Load Pair - non-temporal hint) |
| * C5.6.81 LDP (Load Pair - non vector) |
| * C5.6.82 LDPSW (Load Pair Signed Word - non vector) |
| * C5.6.176 STNP (Store Pair - non-temporal hint) |
| * C5.6.177 STP (Store Pair - non vector) |
| * C6.3.165 LDNP (Load Pair of SIMD&FP - non-temporal hint) |
| * C6.3.165 LDP (Load Pair of SIMD&FP) |
| * C6.3.284 STNP (Store Pair of SIMD&FP - non-temporal hint) |
| * C6.3.284 STP (Store Pair of SIMD&FP) |
| * |
| * 31 30 29 27 26 25 24 23 22 21 15 14 10 9 5 4 0 |
| * +-----+-------+---+---+-------+---+-----------------------------+ |
| * | opc | 1 0 1 | V | 0 | index | L | imm7 | Rt2 | Rn | Rt | |
| * +-----+-------+---+---+-------+---+-------+-------+------+------+ |
| * |
| * opc: LDP/STP/LDNP/STNP 00 -> 32 bit, 10 -> 64 bit |
| * LDPSW 01 |
| * LDP/STP/LDNP/STNP (SIMD) 00 -> 32 bit, 01 -> 64 bit, 10 -> 128 bit |
| * V: 0 -> GPR, 1 -> Vector |
| * idx: 00 -> signed offset with non-temporal hint, 01 -> post-index, |
| * 10 -> signed offset, 11 -> pre-index |
| * L: 0 -> Store 1 -> Load |
| * |
| * Rt, Rt2 = GPR or SIMD registers to be stored |
| * Rn = general purpose register containing address |
| * imm7 = signed offset (multiple of 4 or 8 depending on size) |
| */ |
| static void disas_ldst_pair(DisasContext *s, uint32_t insn) |
| { |
| int rt = extract32(insn, 0, 5); |
| int rn = extract32(insn, 5, 5); |
| int rt2 = extract32(insn, 10, 5); |
| uint64_t offset = sextract64(insn, 15, 7); |
| int index = extract32(insn, 23, 2); |
| bool is_vector = extract32(insn, 26, 1); |
| bool is_load = extract32(insn, 22, 1); |
| int opc = extract32(insn, 30, 2); |
| |
| bool is_signed = false; |
| bool postindex = false; |
| bool wback = false; |
| |
| TCGv_i64 tcg_addr; /* calculated address */ |
| int size; |
| |
| if (opc == 3) { |
| unallocated_encoding(s); |
| return; |
| } |
| |
| if (is_vector) { |
| size = 2 + opc; |
| } else { |
| size = 2 + extract32(opc, 1, 1); |
| is_signed = extract32(opc, 0, 1); |
| if (!is_load && is_signed) { |
| unallocated_encoding(s); |
| return; |
| } |
| } |
| |
| switch (index) { |
| case 1: /* post-index */ |
| postindex = true; |
| wback = true; |
| break; |
| case 0: |
| /* signed offset with "non-temporal" hint. Since we don't emulate |
| * caches we don't care about hints to the cache system about |
| * data access patterns, and handle this identically to plain |
| * signed offset. |
| */ |
| if (is_signed) { |
| /* There is no non-temporal-hint version of LDPSW */ |
| unallocated_encoding(s); |
| return; |
| } |
| postindex = false; |
| break; |
| case 2: /* signed offset, rn not updated */ |
| postindex = false; |
| break; |
| case 3: /* pre-index */ |
| postindex = false; |
| wback = true; |
| break; |
| } |
| |
| if (is_vector && !fp_access_check(s)) { |
| return; |
| } |
| |
| offset <<= size; |
| |
| if (rn == 31) { |
| gen_check_sp_alignment(s); |
| } |
| |
| tcg_addr = read_cpu_reg_sp(s, rn, 1); |
| |
| if (!postindex) { |
| tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); |
| } |
| |
| if (is_vector) { |
| if (is_load) { |
| do_fp_ld(s, rt, tcg_addr, size); |
| } else { |
| do_fp_st(s, rt, tcg_addr, size); |
| } |
| } else { |
| TCGv_i64 tcg_rt = cpu_reg(s, rt); |
| if (is_load) { |
| do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, false, |
| false, 0, false, false); |
| } else { |
| do_gpr_st(s, tcg_rt, tcg_addr, size, |
| false, 0, false, false); |
| } |
| } |
| tcg_gen_addi_i64(tcg_addr, tcg_addr, 1 << size); |
| if (is_vector) { |
| if (is_load) { |
| do_fp_ld(s, rt2, tcg_addr, size); |
| } else { |
| do_fp_st(s, rt2, tcg_addr, size); |
| } |
| } else { |
| TCGv_i64 tcg_rt2 = cpu_reg(s, rt2); |
| if (is_load) { |
| do_gpr_ld(s, tcg_rt2, tcg_addr, size, is_signed, false, |
| false, 0, false, false); |
| } else { |
| do_gpr_st(s, tcg_rt2, tcg_addr, size, |
| false, 0, false, false); |
| } |
| } |
| |
| if (wback) { |
| if (postindex) { |
| tcg_gen_addi_i64(tcg_addr, tcg_addr, offset - (1 << size)); |
| } else { |
| tcg_gen_subi_i64(tcg_addr, tcg_addr, 1 << size); |
| } |
| tcg_gen_mov_i64(cpu_reg_sp(s, rn), tcg_addr); |
| } |
| } |
| |
| /* |
| * C3.3.8 Load/store (immediate post-indexed) |
| * C3.3.9 Load/store (immediate pre-indexed) |
| * C3.3.12 Load/store (unscaled immediate) |
| * |
| * 31 30 29 27 26 25 24 23 22 21 20 12 11 10 9 5 4 0 |
| * +----+-------+---+-----+-----+---+--------+-----+------+------+ |
| * |size| 1 1 1 | V | 0 0 | opc | 0 | imm9 | idx | Rn | Rt | |
| * +----+-------+---+-----+-----+---+--------+-----+------+------+ |
| * |
| * idx = 01 -> post-indexed, 11 pre-indexed, 00 unscaled imm. (no writeback) |
| 10 -> unprivileged |
| * V = 0 -> non-vector |
| * size: 00 -> 8 bit, 01 -> 16 bit, 10 -> 32 bit, 11 -> 64bit |
| * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 |
| */ |
| static void disas_ldst_reg_imm9(DisasContext *s, uint32_t insn, |
| int opc, |
| int size, |
| int rt, |
| bool is_vector) |
| { |
| int rn = extract32(insn, 5, 5); |
| int imm9 = sextract32(insn, 12, 9); |
| int idx = extract32(insn, 10, 2); |
| bool is_signed = false; |
| bool is_store = false; |
| bool is_extended = false; |
| bool is_unpriv = (idx == 2); |
| bool iss_valid = !is_vector; |
| bool post_index; |
| bool writeback; |
| |
| TCGv_i64 tcg_addr; |
| |
| if (is_vector) { |
| size |= (opc & 2) << 1; |
| if (size > 4 || is_unpriv) { |
| unallocated_encoding(s); |
| return; |
| } |
| is_store = ((opc & 1) == 0); |
| if (!fp_access_check(s)) { |
| return; |
| } |
| } else { |
| if (size == 3 && opc == 2) { |
| /* PRFM - prefetch */ |
| if (is_unpriv) { |
| unallocated_encoding(s); |
| return; |
| } |
| return; |
| } |
| if (opc == 3 && size > 1) { |
| unallocated_encoding(s); |
| return; |
| } |
| is_store = (opc == 0); |
| is_signed = extract32(opc, 1, 1); |
| is_extended = (size < 3) && extract32(opc, 0, 1); |
| } |
| |
| switch (idx) { |
| case 0: |
| case 2: |
| post_index = false; |
| writeback = false; |
| break; |
| case 1: |
| post_index = true; |
| writeback = true; |
| break; |
| case 3: |
| post_index = false; |
| writeback = true; |
| break; |
| } |
| |
| if (rn == 31) { |
| gen_check_sp_alignment(s); |
| } |
| tcg_addr = read_cpu_reg_sp(s, rn, 1); |
| |
| if (!post_index) { |
| tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); |
| } |
| |
| if (is_vector) { |
| if (is_store) { |
| do_fp_st(s, rt, tcg_addr, size); |
| } else { |
| do_fp_ld(s, rt, tcg_addr, size); |
| } |
| } else { |
| TCGv_i64 tcg_rt = cpu_reg(s, rt); |
| int memidx = is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); |
| bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
| |
| if (is_store) { |
| do_gpr_st_memidx(s, tcg_rt, tcg_addr, size, memidx, |
| iss_valid, rt, iss_sf, false); |
| } else { |
| do_gpr_ld_memidx(s, tcg_rt, tcg_addr, size, |
| is_signed, is_extended, memidx, |
| iss_valid, rt, iss_sf, false); |
| } |
| } |
| |
| if (writeback) { |
| TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); |
| if (post_index) { |
| tcg_gen_addi_i64(tcg_addr, tcg_addr, imm9); |
| } |
| tcg_gen_mov_i64(tcg_rn, tcg_addr); |
| } |
| } |
| |
| /* |
| * C3.3.10 Load/store (register offset) |
| * |
| * 31 30 29 27 26 25 24 23 22 21 20 16 15 13 12 11 10 9 5 4 0 |
| * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ |
| * |size| 1 1 1 | V | 0 0 | opc | 1 | Rm | opt | S| 1 0 | Rn | Rt | |
| * +----+-------+---+-----+-----+---+------+-----+--+-----+----+----+ |
| * |
| * For non-vector: |
| * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit |
| * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 |
| * For vector: |
| * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated |
| * opc<0>: 0 -> store, 1 -> load |
| * V: 1 -> vector/simd |
| * opt: extend encoding (see DecodeRegExtend) |
| * S: if S=1 then scale (essentially index by sizeof(size)) |
| * Rt: register to transfer into/out of |
| * Rn: address register or SP for base |
| * Rm: offset register or ZR for offset |
| */ |
| static void disas_ldst_reg_roffset(DisasContext *s, uint32_t insn, |
| int opc, |
| int size, |
| int rt, |
| bool is_vector) |
| { |
| int rn = extract32(insn, 5, 5); |
| int shift = extract32(insn, 12, 1); |
| int rm = extract32(insn, 16, 5); |
| int opt = extract32(insn, 13, 3); |
| bool is_signed = false; |
| bool is_store = false; |
| bool is_extended = false; |
| |
| TCGv_i64 tcg_rm; |
| TCGv_i64 tcg_addr; |
| |
| if (extract32(opt, 1, 1) == 0) { |
| unallocated_encoding(s); |
| return; |
| } |
| |
| if (is_vector) { |
| size |= (opc & 2) << 1; |
| if (size > 4) { |
| unallocated_encoding(s); |
| return; |
| } |
| is_store = !extract32(opc, 0, 1); |
| if (!fp_access_check(s)) { |
| return; |
| } |
| } else { |
| if (size == 3 && opc == 2) { |
| /* PRFM - prefetch */ |
| return; |
| } |
| if (opc == 3 && size > 1) { |
| unallocated_encoding(s); |
| return; |
| } |
| is_store = (opc == 0); |
| is_signed = extract32(opc, 1, 1); |
| is_extended = (size < 3) && extract32(opc, 0, 1); |
| } |
| |
| if (rn == 31) { |
| gen_check_sp_alignment(s); |
| } |
| tcg_addr = read_cpu_reg_sp(s, rn, 1); |
| |
| tcg_rm = read_cpu_reg(s, rm, 1); |
| ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); |
| |
| tcg_gen_add_i64(tcg_addr, tcg_addr, tcg_rm); |
| |
| if (is_vector) { |
| if (is_store) { |
| do_fp_st(s, rt, tcg_addr, size); |
| } else { |
| do_fp_ld(s, rt, tcg_addr, size); |
| } |
| } else { |
| TCGv_i64 tcg_rt = cpu_reg(s, rt); |
| bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
| if (is_store) { |
| do_gpr_st(s, tcg_rt, tcg_addr, size, |
| true, rt, iss_sf, false); |
| } else { |
| do_gpr_ld(s, tcg_rt, tcg_addr, size, |
| is_signed, is_extended, |
| true, rt, iss_sf, false); |
| } |
| } |
| } |
| |
| /* |
| * C3.3.13 Load/store (unsigned immediate) |
| * |
| * 31 30 29 27 26 25 24 23 22 21 10 9 5 |
| * +----+-------+---+-----+-----+------------+-------+------+ |
| * |size| 1 1 1 | V | 0 1 | opc | imm12 | Rn | Rt | |
| * +----+-------+---+-----+-----+------------+-------+------+ |
| * |
| * For non-vector: |
| * size: 00-> byte, 01 -> 16 bit, 10 -> 32bit, 11 -> 64bit |
| * opc: 00 -> store, 01 -> loadu, 10 -> loads 64, 11 -> loads 32 |
| * For vector: |
| * size is opc<1>:size<1:0> so 100 -> 128 bit; 110 and 111 unallocated |
| * opc<0>: 0 -> store, 1 -> load |
| * Rn: base address register (inc SP) |
| * Rt: target register |
| */ |
| static void disas_ldst_reg_unsigned_imm(DisasContext *s, uint32_t insn, |
| int opc, |
| int size, |
| int rt, |
| bool is_vector) |
| { |
| int rn = extract32(insn, 5, 5); |
| unsigned int imm12 = extract32(insn, 10, 12); |
| unsigned int offset; |
| |
| TCGv_i64 tcg_addr; |
| |
| bool is_store; |
| bool is_signed = false; |
| bool is_extended = false; |
| |
| if (is_vector) { |
| size |= (opc & 2) << 1; |
| if (size > 4) { |
| unallocated_encoding(s); |
| return; |
| } |
| is_store = !extract32(opc, 0, 1); |
| if (!fp_access_check(s)) { |
| return; |
| } |
| } else { |
| if (size == 3 && opc == 2) { |
| /* PRFM - prefetch */ |
| return; |
| } |
| if (opc == 3 && size > 1) { |
| unallocated_encoding(s); |
| return; |
| } |
| is_store = (opc == 0); |
| is_signed = extract32(opc, 1, 1); |
| is_extended = (size < 3) && extract32(opc, 0, 1); |
| } |
| |
| if (rn == 31) { |
| gen_check_sp_alignment(s); |
| } |
| tcg_addr = read_cpu_reg_sp(s, rn, 1); |
| offset = imm12 << size; |
| tcg_gen_addi_i64(tcg_addr, tcg_addr, offset); |
| |
| if (is_vector) { |
| if (is_store) { |
| do_fp_st(s, rt, tcg_addr, size); |
| } else { |
| do_fp_ld(s, rt, tcg_addr, size); |
| } |
| } else { |
| TCGv_i64 tcg_rt = cpu_reg(s, rt); |
| bool iss_sf = disas_ldst_compute_iss_sf(size, is_signed, opc); |
| if (is_store) { |
| do_gpr_st(s, tcg_rt, tcg_addr, size, |
| true, rt, iss_sf, false); |
| } else { |
| do_gpr_ld(s, tcg_rt, tcg_addr, size, is_signed, is_extended, |
| true, rt, iss_sf, false); |
| } |
| } |
| } |
| |
| /* Load/store register (all forms) */ |
| static void disas_ldst_reg(DisasContext *s, uint32_t insn) |
| { |
| int rt = extract32(insn, 0, 5); |
| int opc = extract32(insn, 22, 2); |
| bool is_vector = extract32(insn, 26, 1); |
| int size = extract32(insn, 30, 2); |
| |
| switch (extract32(insn, 24, 2)) { |
| case 0: |
| if (extract32(insn, 21, 1) == 1 && extract32(insn, 10, 2) == 2) { |
| disas_ldst_reg_roffset(s, insn, opc, size, rt, is_vector); |
| } else { |
| /* Load/store register (unscaled immediate) |
| * Load/store immediate pre/post-indexed |
| * Load/store register unprivileged |
| */ |
| disas_ldst_reg_imm9(s, insn, opc, size, rt, is_vector); |
| } |
| break; |
| case 1: |
| disas_ldst_reg_unsigned_imm(s, insn, opc, size, rt, is_vector); |
| break; |
| default: |
| unallocated_encoding(s); |
| break; |
| } |
| } |
| |
| /* C3.3.1 AdvSIMD load/store multiple structures |
| * |
| * 31 30 29 23 22 21 16 15 12 11 10 9 5 4 0 |
| * +---+---+---------------+---+-------------+--------+------+------+------+ |
| * | 0 | Q | 0 0 1 1 0 0 0 | L | 0 0 0 0 0 0 | opcode | size | Rn | Rt | |
| * +---+---+---------------+---+-------------+--------+------+------+------+ |
| * |
| * C3.3.2 AdvSIMD load/store multiple structures (post-indexed) |
| * |
| * 31 30 29 23 22 21 20 16 15 12 11 10 9 5 4 0 |
| * +---+---+---------------+---+---+---------+--------+------+------+------+ |
| * | 0 | Q | 0 0 1 1 0 0 1 | L | 0 | Rm | opcode | size | Rn | Rt | |
| * +---+---+---------------+---+---+---------+--------+------+------+------+ |
| * |
| * Rt: first (or only) SIMD&FP register to be transferred |
| * Rn: base address or SP |
| * Rm (post-index only): post-index register (when !31) or size dependent #imm |
| */ |
| static void disas_ldst_multiple_struct(DisasContext *s, uint32_t insn) |
| { |
| int rt = extract32(insn, 0, 5); |
| int rn = extract32(insn, 5, 5); |
| int size = extract32(insn, 10, 2); |
| int opcode = extract32(insn, 12, 4); |
| bool is_store = !extract32(insn, 22, 1); |
| bool is_postidx = extract32(insn, 23, 1); |
| bool is_q = extract32(insn, 30, 1); |
| TCGv_i64 tcg_addr, tcg_rn; |
| |
| int ebytes = 1 << size; |
| int elements = (is_q ? 128 : 64) / (8 << size); |
| int rpt; /* num iterations */ |
| int selem; /* structure elements */ |
| int r; |
| |
| if (extract32(insn, 31, 1) || extract32(insn, 21, 1)) { |
| unallocated_encoding(s); |
| return; |
| } |
| |
| /* From the shared decode logic */ |
| switch (opcode) { |
| case 0x0: |
| rpt = 1; |
| selem = 4; |
| break; |
| case 0x2: |
| rpt = 4; |
| selem = 1; |
| break; |
| case 0x4: |
| rpt = 1; |
| selem = 3; |
| break; |
| case 0x6: |
| rpt = 3; |
| selem = 1; |
| break; |
| case 0x7: |
| rpt = 1; |
| selem = 1; |
| break; |
| case 0x8: |
| rpt = 1; |
| selem = 2; |
| break; |
| case 0xa: |
| rpt = 2; |
| selem = 1; |
| break; |
| default: |
| unallocated_encoding(s); |
| return; |
| } |
| |
| if (size == 3 && !is_q && selem != 1) { |
| /* reserved */ |
| unallocated_encoding(s); |
| return; |
| } |
| |
| if (!fp_access_check(s)) { |
| return; |
| } |
| |
| if (rn == 31) { |
| gen_check_sp_alignment(s); |
| } |
| |
| tcg_rn = cpu_reg_sp(s, rn); |
| tcg_addr = tcg_temp_new_i64(); |
| tcg_gen_mov_i64(tcg_addr, tcg_rn); |
| |
| for (r = 0; r < rpt; r++) { |
| int e; |
| for (e = 0; e < elements; e++) { |
| int tt = (rt + r) % 32; |
| int xs; |
| for (xs = 0; xs < selem; xs++) { |
| if (is_store) { |
| do_vec_st(s, tt, e, tcg_addr, size); |
| } else { |
| do_vec_ld(s, tt, e, tcg_addr, size); |
| |
| /* For non-quad operations, setting a slice of the low |
| * 64 bits of the register clears the high 64 bits (in |
| * the ARM ARM pseudocode this is implicit in the fact |
| * that 'rval' is a 64 bit wide variable). We optimize |
| * by noticing that we only need to do this the first |
| * time we touch a register. |
| */ |
| if (!is_q && e == 0 && (r == 0 || xs == selem - 1)) { |
| clear_vec_high(s, tt); |
| } |
| } |
| tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes); |
| tt = (tt + 1) % 32; |
| } |
| } |
| } |
| |
| if (is_postidx) { |
| int rm = extract32(insn, 16, 5); |
| if (rm == 31) { |
| tcg_gen_mov_i64(tcg_rn, tcg_addr); |
| } else { |
| tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); |
| } |
| } |
| tcg_temp_free_i64(tcg_addr); |
| } |
| |
| /* C3.3.3 AdvSIMD load/store single structure |
| * |
| * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 |
| * +---+---+---------------+-----+-----------+-----+---+------+------+------+ |
| * | 0 | Q | 0 0 1 1 0 1 0 | L R | 0 0 0 0 0 | opc | S | size | Rn | Rt | |
| * +---+---+---------------+-----+-----------+-----+---+------+------+------+ |
| * |
| * C3.3.4 AdvSIMD load/store single structure (post-indexed) |
| * |
| * 31 30 29 23 22 21 20 16 15 13 12 11 10 9 5 4 0 |
| * +---+---+---------------+-----+-----------+-----+---+------+------+------+ |
| * | 0 | Q | 0 0 1 1 0 1 1 | L R | Rm | opc | S | size | Rn | Rt | |
| * +---+---+---------------+-----+-----------+-----+---+------+------+------+ |
| * |
| * Rt: first (or only) SIMD&FP register to be transferred |
| * Rn: base address or SP |
| * Rm (post-index only): post-index register (when !31) or size dependent #imm |
| * index = encoded in Q:S:size dependent on size |
| * |
| * lane_size = encoded in R, opc |
| * transfer width = encoded in opc, S, size |
| */ |
| static void disas_ldst_single_struct(DisasContext *s, uint32_t insn) |
| { |
| int rt = extract32(insn, 0, 5); |
| int rn = extract32(insn, 5, 5); |
| int size = extract32(insn, 10, 2); |
| int S = extract32(insn, 12, 1); |
| int opc = extract32(insn, 13, 3); |
| int R = extract32(insn, 21, 1); |
| int is_load = extract32(insn, 22, 1); |
| int is_postidx = extract32(insn, 23, 1); |
| int is_q = extract32(insn, 30, 1); |
| |
| int scale = extract32(opc, 1, 2); |
| int selem = (extract32(opc, 0, 1) << 1 | R) + 1; |
| bool replicate = false; |
| int index = is_q << 3 | S << 2 | size; |
| int ebytes, xs; |
| TCGv_i64 tcg_addr, tcg_rn; |
| |
| switch (scale) { |
| case 3: |
| if (!is_load || S) { |
| unallocated_encoding(s); |
| return; |
| } |
| scale = size; |
| replicate = true; |
| break; |
| case 0: |
| break; |
| case 1: |
| if (extract32(size, 0, 1)) { |
| unallocated_encoding(s); |
| return; |
| } |
| index >>= 1; |
| break; |
| case 2: |
| if (extract32(size, 1, 1)) { |
| unallocated_encoding(s); |
| return; |
| } |
| if (!extract32(size, 0, 1)) { |
| index >>= 2; |
| } else { |
| if (S) { |
| unallocated_encoding(s); |
| return; |
| } |
| index >>= 3; |
| scale = 3; |
| } |
| break; |
| default: |
| g_assert_not_reached(); |
| } |
| |
| if (!fp_access_check(s)) { |
| return; |
| } |
| |
| ebytes = 1 << scale; |
| |
| if (rn == 31) { |
| gen_check_sp_alignment(s); |
| } |
| |
| tcg_rn = cpu_reg_sp(s, rn); |
| tcg_addr = tcg_temp_new_i64(); |
| tcg_gen_mov_i64(tcg_addr, tcg_rn); |
| |
| for (xs = 0; xs < selem; xs++) { |
| if (replicate) { |
| /* Load and replicate to all elements */ |
| uint64_t mulconst; |
| TCGv_i64 tcg_tmp = tcg_temp_new_i64(); |
| |
| tcg_gen_qemu_ld_i64(tcg_tmp, tcg_addr, |
| get_mem_index(s), s->be_data + scale); |
| switch (scale) { |
| case 0: |
| mulconst = 0x0101010101010101ULL; |
| break; |
| case 1: |
| mulconst = 0x0001000100010001ULL; |
| break; |
| case 2: |
| mulconst = 0x0000000100000001ULL; |
| break; |
| case 3: |
| mulconst = 0; |
| break; |
| default: |
| g_assert_not_reached(); |
| } |
| if (mulconst) { |
| tcg_gen_muli_i64(tcg_tmp, tcg_tmp, mulconst); |
| } |
| write_vec_element(s, tcg_tmp, rt, 0, MO_64); |
| if (is_q) { |
| write_vec_element(s, tcg_tmp, rt, 1, MO_64); |
| } else { |
| clear_vec_high(s, rt); |
| } |
| tcg_temp_free_i64(tcg_tmp); |
| } else { |
| /* Load/store one element per register */ |
| if (is_load) { |
| do_vec_ld(s, rt, index, tcg_addr, s->be_data + scale); |
| } else { |
| do_vec_st(s, rt, index, tcg_addr, s->be_data + scale); |
| } |
| } |
| tcg_gen_addi_i64(tcg_addr, tcg_addr, ebytes); |
| rt = (rt + 1) % 32; |
| } |
| |
| if (is_postidx) { |
| int rm = extract32(insn, 16, 5); |
| if (rm == 31) { |
| tcg_gen_mov_i64(tcg_rn, tcg_addr); |
| } else { |
| tcg_gen_add_i64(tcg_rn, tcg_rn, cpu_reg(s, rm)); |
| } |
| } |
| tcg_temp_free_i64(tcg_addr); |
| } |
| |
| /* C3.3 Loads and stores */ |
| static void disas_ldst(DisasContext *s, uint32_t insn) |
| { |
| switch (extract32(insn, 24, 6)) { |
| case 0x08: /* Load/store exclusive */ |
| disas_ldst_excl(s, insn); |
| break; |
| case 0x18: case 0x1c: /* Load register (literal) */ |
| disas_ld_lit(s, insn); |
| break; |
| case 0x28: case 0x29: |
| case 0x2c: case 0x2d: /* Load/store pair (all forms) */ |
| disas_ldst_pair(s, insn); |
| break; |
| case 0x38: case 0x39: |
| case 0x3c: case 0x3d: /* Load/store register (all forms) */ |
| disas_ldst_reg(s, insn); |
| break; |
| case 0x0c: /* AdvSIMD load/store multiple structures */ |
| disas_ldst_multiple_struct(s, insn); |
| break; |
| case 0x0d: /* AdvSIMD load/store single structure */ |
| disas_ldst_single_struct(s, insn); |
| break; |
| default: |
| unallocated_encoding(s); |
| break; |
| } |
| } |
| |
| /* C3.4.6 PC-rel. addressing |
| * 31 30 29 28 24 23 5 4 0 |
| * +----+-------+-----------+-------------------+------+ |
| * | op | immlo | 1 0 0 0 0 | immhi | Rd | |
| * +----+-------+-----------+-------------------+------+ |
| */ |
| static void disas_pc_rel_adr(DisasContext *s, uint32_t insn) |
| { |
| unsigned int page, rd; |
| uint64_t base; |
| uint64_t offset; |
| |
| page = extract32(insn, 31, 1); |
| /* SignExtend(immhi:immlo) -> offset */ |
| offset = sextract64(insn, 5, 19); |
| offset = offset << 2 | extract32(insn, 29, 2); |
| rd = extract32(insn, 0, 5); |
| base = s->pc - 4; |
| |
| if (page) { |
| /* ADRP (page based) */ |
| base &= ~0xfff; |
| offset <<= 12; |
| } |
| |
| tcg_gen_movi_i64(cpu_reg(s, rd), base + offset); |
| } |
| |
| /* |
| * C3.4.1 Add/subtract (immediate) |
| * |
| * 31 30 29 28 24 23 22 21 10 9 5 4 0 |
| * +--+--+--+-----------+-----+-------------+-----+-----+ |
| * |sf|op| S| 1 0 0 0 1 |shift| imm12 | Rn | Rd | |
| * +--+--+--+-----------+-----+-------------+-----+-----+ |
| * |
| * sf: 0 -> 32bit, 1 -> 64bit |
| * op: 0 -> add , 1 -> sub |
| * S: 1 -> set flags |
| * shift: 00 -> LSL imm by 0, 01 -> LSL imm by 12 |
| */ |
| static void disas_add_sub_imm(DisasContext *s, uint32_t insn) |
| { |
| int rd = extract32(insn, 0, 5); |
| int rn = extract32(insn, 5, 5); |
| uint64_t imm = extract32(insn, 10, 12); |
| int shift = extract32(insn, 22, 2); |
| bool setflags = extract32(insn, 29, 1); |
| bool sub_op = extract32(insn, 30, 1); |
| bool is_64bit = extract32(insn, 31, 1); |
| |
| TCGv_i64 tcg_rn = cpu_reg_sp(s, rn); |
| TCGv_i64 tcg_rd = setflags ? cpu_reg(s, rd) : cpu_reg_sp(s, rd); |
| TCGv_i64 tcg_result; |
| |
| switch (shift) { |
| case 0x0: |
| break; |
| case 0x1: |
| imm <<= 12; |
| break; |
| default: |
| unallocated_encoding(s); |
| return; |
| } |
| |
| tcg_result = tcg_temp_new_i64(); |
| if (!setflags) { |
| if (sub_op) { |
| tcg_gen_subi_i64(tcg_result, tcg_rn, imm); |
| } else { |
| tcg_gen_addi_i64(tcg_result, tcg_rn, imm); |
| } |
| } else { |
| TCGv_i64 tcg_imm = tcg_const_i64(imm); |
| if (sub_op) { |
| gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); |
| } else { |
| gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); |
| } |
| tcg_temp_free_i64(tcg_imm); |
| } |
| |
| if (is_64bit) { |
| tcg_gen_mov_i64(tcg_rd, tcg_result); |
| } else { |
| tcg_gen_ext32u_i64(tcg_rd, tcg_result); |
| } |
| |
| tcg_temp_free_i64(tcg_result); |
| } |
| |
| /* The input should be a value in the bottom e bits (with higher |
| * bits zero); returns that value replicated into every element |
| * of size e in a 64 bit integer. |
| */ |
| static uint64_t bitfield_replicate(uint64_t mask, unsigned int e) |
| { |
| assert(e != 0); |
| while (e < 64) { |
| mask |= mask << e; |
| e *= 2; |
| } |
| return mask; |
| } |
| |
| /* Return a value with the bottom len bits set (where 0 < len <= 64) */ |
| static inline uint64_t bitmask64(unsigned int length) |
| { |
| assert(length > 0 && length <= 64); |
| return ~0ULL >> (64 - length); |
| } |
| |
| /* Simplified variant of pseudocode DecodeBitMasks() for the case where we |
| * only require the wmask. Returns false if the imms/immr/immn are a reserved |
| * value (ie should cause a guest UNDEF exception), and true if they are |
| * valid, in which case the decoded bit pattern is written to result. |
| */ |
| static bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, |
| unsigned int imms, unsigned int immr) |
| { |
| uint64_t mask; |
| unsigned e, levels, s, r; |
| int len; |
| |
| assert(immn < 2 && imms < 64 && immr < 64); |
| |
| /* The bit patterns we create here are 64 bit patterns which |
| * are vectors of identical elements of size e = 2, 4, 8, 16, 32 or |
| * 64 bits each. Each element contains the same value: a run |
| * of between 1 and e-1 non-zero bits, rotated within the |
| * element by between 0 and e-1 bits. |
| * |
| * The element size and run length are encoded into immn (1 bit) |
| * and imms (6 bits) as follows: |
| * 64 bit elements: immn = 1, imms = <length of run - 1> |
| * 32 bit elements: immn = 0, imms = 0 : <length of run - 1> |
| * 16 bit elements: immn = 0, imms = 10 : <length of run - 1> |
| * 8 bit elements: immn = 0, imms = 110 : <length of run - 1> |
| * 4 bit elements: immn = 0, imms = 1110 : <length of run - 1> |
| * 2 bit elements: immn = 0, imms = 11110 : <length of run - 1> |
| * Notice that immn = 0, imms = 11111x is the only combination |
| * not covered by one of the above options; this is reserved. |
| * Further, <length of run - 1> all-ones is a reserved pattern. |
| * |
| * In all cases the rotation is by immr % e (and immr is 6 bits). |
| */ |
| |
| /* First determine the element size */ |
| len = 31 - clz32((immn << 6) | (~imms & 0x3f)); |
| if (len < 1) { |
| /* This is the immn == 0, imms == 0x11111x case */ |
| return false; |
| } |
| e = 1 << len; |
| |
| levels = e - 1; |
| s = imms & levels; |
| r = immr & levels; |
| |
| if (s == levels) { |
| /* <length of run - 1> mustn't be all-ones. */ |
| return false; |
| } |
| |
| /* Create the value of one element: s+1 set bits rotated |
| * by r within the element (which is e bits wide)... |
| */ |
| mask = bitmask64(s + 1); |
| if (r) { |
| mask = (mask >> r) | (mask << (e - r)); |
| mask &= bitmask64(e); |
| } |
| /* ...then replicate the element over the whole 64 bit value */ |
| mask = bitfield_replicate(mask, e); |
| *result = mask; |
| return true; |
| } |
| |
| /* C3.4.4 Logical (immediate) |
| * 31 30 29 28 23 22 21 16 15 10 9 5 4 0 |
| * +----+-----+-------------+---+------+------+------+------+ |
| * | sf | opc | 1 0 0 1 0 0 | N | immr | imms | Rn | Rd | |
| * +----+-----+-------------+---+------+------+------+------+ |
| */ |
| static void disas_logic_imm(DisasContext *s, uint32_t insn) |
| { |
| unsigned int sf, opc, is_n, immr, imms, rn, rd; |
| TCGv_i64 tcg_rd, tcg_rn; |
| uint64_t wmask; |
| bool is_and = false; |
| |
| sf = extract32(insn, 31, 1); |
| opc = extract32(insn, 29, 2); |
| is_n = extract32(insn, 22, 1); |
| immr = extract32(insn, 16, 6); |
| imms = extract32(insn, 10, 6); |
| rn = extract32(insn, 5, 5); |
| rd = extract32(insn, 0, 5); |
| |
| if (!sf && is_n) { |
| unallocated_encoding(s); |
| return; |
| } |