commit | 6b9c26fb5eed2345398daca4eef601da2f3d7867 | [log] [tgz] |
---|---|---|
author | Yongbok Kim <yongbok.kim@imgtec.com> | Tue Jun 30 16:33:15 2015 +0100 |
committer | Leon Alrae <leon.alrae@imgtec.com> | Wed Jul 15 14:07:20 2015 +0100 |
tree | 285285860c7d2e441592aea59bc9f777d9b514b4 | |
parent | d4f4f0d5d9e74c19614479592c8bc865d92773d0 [diff] |
disas/mips: fix disassembling R6 instructions In the Release 6 of the MIPS Architecture, LL, SC, LLD, SCD, PREF and CACHE instructions have 9 bits offsets. Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net> Reviewed-by: Leon Alrae <leon.alrae@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>