Merge remote-tracking branch 'remotes/cohuck/tags/s390x-20141105' into staging Several bugfixes for s390x: - instruction decoding and sparse warning in kvm - overlong input and hangs in the sclp consoles # gpg: Signature made Wed 05 Nov 2014 15:42:14 GMT using RSA key ID C6F02FAF # gpg: Good signature from "Cornelia Huck <huckc@linux.vnet.ibm.com>" # gpg: aka "Cornelia Huck <cornelia.huck@de.ibm.com>" * remotes/cohuck/tags/s390x-20141105: s390x/sclpconsole: Avoid hanging SCLP ASCII console s390x/sclpconsole-lm: Fix hanging SCLP line mode console s390x/sclpconsole-lm: truncate input if line is too long s390x/kvm: Fix warning from sparse s390x/kvm: Fix opcode decoding for eb instruction handler Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
diff --git a/default-configs/mips-softmmu.mak b/default-configs/mips-softmmu.mak index 71177ef..2a80b04 100644 --- a/default-configs/mips-softmmu.mak +++ b/default-configs/mips-softmmu.mak
@@ -32,6 +32,5 @@ CONFIG_I8259=y CONFIG_JAZZ_LED=y CONFIG_MC146818RTC=y -CONFIG_VT82C686=y CONFIG_ISA_TESTDEV=y CONFIG_EMPTY_SLOT=y
diff --git a/default-configs/mips64-softmmu.mak b/default-configs/mips64-softmmu.mak index 617301b..f1f933b 100644 --- a/default-configs/mips64-softmmu.mak +++ b/default-configs/mips64-softmmu.mak
@@ -32,6 +32,5 @@ CONFIG_I8259=y CONFIG_JAZZ_LED=y CONFIG_MC146818RTC=y -CONFIG_VT82C686=y CONFIG_ISA_TESTDEV=y CONFIG_EMPTY_SLOT=y
diff --git a/default-configs/mipsel-softmmu.mak b/default-configs/mipsel-softmmu.mak index 532a9ae..7708185 100644 --- a/default-configs/mipsel-softmmu.mak +++ b/default-configs/mipsel-softmmu.mak
@@ -32,6 +32,5 @@ CONFIG_I8259=y CONFIG_JAZZ_LED=y CONFIG_MC146818RTC=y -CONFIG_VT82C686=y CONFIG_ISA_TESTDEV=y CONFIG_EMPTY_SLOT=y
diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c index c6870f1..a7b1b68 100644 --- a/hw/char/virtio-serial-bus.c +++ b/hw/char/virtio-serial-bus.c
@@ -871,7 +871,7 @@ return; } - if (find_port_by_name(port->name)) { + if (port->name != NULL && find_port_by_name(port->name)) { error_setg(errp, "virtio-serial-bus: A port already exists by name %s", port->name); return;
diff --git a/target-mips/cpu.h b/target-mips/cpu.h index d21da8e..c01bbda 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h
@@ -424,17 +424,25 @@ #define CP0C2_SA 0 int32_t CP0_Config3; #define CP0C3_M 31 +#define CP0C3_BPG 30 +#define CP0C3_CMCGR 29 #define CP0C3_MSAP 28 #define CP0C3_BP 27 #define CP0C3_BI 26 +#define CP0C3_IPLW 21 +#define CP0C3_MMAR 18 +#define CP0C3_MCU 17 #define CP0C3_ISA_ON_EXC 16 +#define CP0C3_ISA 14 #define CP0C3_ULRI 13 #define CP0C3_RXI 12 +#define CP0C3_DSP2P 11 #define CP0C3_DSPP 10 #define CP0C3_LPA 7 #define CP0C3_VEIC 6 #define CP0C3_VInt 5 #define CP0C3_SP 4 +#define CP0C3_CDMM 3 #define CP0C3_MT 2 #define CP0C3_SM 1 #define CP0C3_TL 0 @@ -443,6 +451,11 @@ #define CP0C4_M 31 #define CP0C4_IE 29 #define CP0C4_KScrExist 16 +#define CP0C4_MMUExtDef 14 +#define CP0C4_FTLBPageSize 8 +#define CP0C4_FTLBWays 4 +#define CP0C4_FTLBSets 0 +#define CP0C4_MMUSizeExt 0 uint32_t CP0_Config5; uint32_t CP0_Config5_rw_bitmask; #define CP0C5_M 31
diff --git a/target-mips/translate.c b/target-mips/translate.c index 2117ce8..f0b8e6f 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c
@@ -8104,6 +8104,7 @@ MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn, ctx->hflags, btarget); ctx->btarget = btarget; + ctx->hflags |= MIPS_HFLAG_BDS32; out: tcg_temp_free_i64(t0); @@ -13613,8 +13614,13 @@ check_insn(ctx, ASE_MIPS3D); /* Fall through */ do_cp1branch: - gen_compute_branch1(ctx, mips32_op, - (ctx->opcode >> 18) & 0x7, imm << 1); + if (env->CP0_Config1 & (1 << CP0C1_FP)) { + check_cp1_enabled(ctx); + gen_compute_branch1(ctx, mips32_op, + (ctx->opcode >> 18) & 0x7, imm << 1); + } else { + generate_exception_err(ctx, EXCP_CpU, 1); + } break; case BPOSGE64: case BPOSGE32: @@ -19106,7 +19112,7 @@ gen_io_end(); } if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) { - save_cpu_state(&ctx, ctx.bstate == BS_NONE); + save_cpu_state(&ctx, ctx.bstate != BS_EXCP); gen_helper_0e0i(raise_exception, EXCP_DEBUG); } else { switch (ctx.bstate) { @@ -19279,14 +19285,12 @@ regnames[i]); for (i = 0; i < 32; i++) { - int off = offsetof(CPUMIPSState, active_fpu.fpr[i]); - fpu_f64[i] = tcg_global_mem_new_i64(TCG_AREG0, off, fregnames[i]); - } - - for (i = 0; i < 32; i++) { int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); msa_wr_d[i * 2] = tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2]); + /* The scalar floating-point unit (FPU) registers are mapped on + * the MSA vector registers. */ + fpu_f64[i] = msa_wr_d[i * 2]; off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); msa_wr_d[i * 2 + 1] = tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2 + 1]);
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c index 4dee1ca..148b394 100644 --- a/target-mips/translate_init.c +++ b/target-mips/translate_init.c
@@ -333,7 +333,8 @@ (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_CA), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt) | (1 << CP0C3_DSPP), + .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) | + (0 << CP0C3_VInt), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 4, .SYNCI_Step = 32, @@ -376,7 +377,7 @@ (0x93 << FCR0_PRID), .SEGBITS = 32, .PABITS = 32, - .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2 | ASE_MSA, + .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA, .mmu_type = MMU_TYPE_R4000, }, #if defined(TARGET_MIPS64) @@ -601,7 +602,8 @@ (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), .CP0_Config2 = MIPS_CONFIG2, - .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA), + .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) | + (1 << CP0C3_DSPP) | (1 << CP0C3_LPA), .CP0_LLAddr_rw_bitmask = 0, .CP0_LLAddr_shift = 0, .SYNCI_Step = 32,