cpu: Move reset logging to CPUState x86 was using additional CPU_DUMP_* flags, so make that configurable in CPUClass::reset_dump_flags. This adds reset logging for alpha, unicore32 and xtensa. Acked-by: Michael Walle <michael@walle.cc> (for lm32) Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Andreas Färber <afaerber@suse.de>
diff --git a/include/qom/cpu.h b/include/qom/cpu.h index a08a8ab..147c256 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h
@@ -53,6 +53,7 @@ * @class_by_name: Callback to map -cpu command line model name to an * instantiatable CPU type. * @reset: Callback to reset the #CPUState to its initial state. + * @reset_dump_flags: #CPUDumpFlags to use for reset logging. * @do_interrupt: Callback for interrupt handling. * @do_unassigned_access: Callback for unassigned access handling. * @dump_state: Callback for dumping state. @@ -72,6 +73,7 @@ ObjectClass *(*class_by_name)(const char *cpu_model); void (*reset)(CPUState *cpu); + int reset_dump_flags; void (*do_interrupt)(CPUState *cpu); CPUUnassignedAccess do_unassigned_access; void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
diff --git a/qom/cpu.c b/qom/cpu.c index ee8f632..5c45ab5 100644 --- a/qom/cpu.c +++ b/qom/cpu.c
@@ -22,6 +22,7 @@ #include "qom/cpu.h" #include "sysemu/kvm.h" #include "qemu/notify.h" +#include "qemu/log.h" #include "sysemu/sysemu.h" typedef struct CPUExistsArgs { @@ -187,6 +188,13 @@ static void cpu_common_reset(CPUState *cpu) { + CPUClass *cc = CPU_GET_CLASS(cpu); + + if (qemu_loglevel_mask(CPU_LOG_RESET)) { + qemu_log("CPU Reset (CPU %d)\n", cpu->cpu_index); + log_cpu_state(cpu, cc->reset_dump_flags); + } + cpu->exit_request = 0; cpu->interrupt_request = 0; cpu->current_tb = NULL;
diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 84974a9..be26acc 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c
@@ -63,11 +63,6 @@ ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu); CPUARMState *env = &cpu->env; - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(s, 0); - } - acc->parent_reset(s); memset(env, 0, offsetof(CPUARMState, breakpoints));
diff --git a/target-cris/cpu.c b/target-cris/cpu.c index f6c4f3f..2abb57f 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c
@@ -34,11 +34,6 @@ CPUCRISState *env = &cpu->env; uint32_t vr; - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(s, 0); - } - ccc->parent_reset(s); vr = env->pregs[PR_VR];
diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 82a451b..e3f75a8 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c
@@ -2175,11 +2175,6 @@ CPUX86State *env = &cpu->env; int i; - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(s, CPU_DUMP_FPU | CPU_DUMP_CCOP); - } - xcc->parent_reset(s); @@ -2523,6 +2518,7 @@ xcc->parent_reset = cc->reset; cc->reset = x86_cpu_reset; + cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP; cc->do_interrupt = x86_cpu_do_interrupt; cc->dump_state = x86_cpu_dump_state;
diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index 6e44d45..04327ac 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c
@@ -29,11 +29,6 @@ LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu); CPULM32State *env = &cpu->env; - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(s, 0); - } - lcc->parent_reset(s); /* reset cpu state */
diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c index c9ac30f..1b6ef66 100644 --- a/target-m68k/cpu.c +++ b/target-m68k/cpu.c
@@ -35,11 +35,6 @@ M68kCPUClass *mcc = M68K_CPU_GET_CLASS(cpu); CPUM68KState *env = &cpu->env; - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(s, 0); - } - mcc->parent_reset(s); memset(env, 0, offsetof(CPUM68KState, breakpoints));
diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index d93519e..dce1c7e 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c
@@ -33,11 +33,6 @@ MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu); CPUMBState *env = &cpu->env; - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(s, 0); - } - mcc->parent_reset(s); memset(env, 0, offsetof(CPUMBState, breakpoints));
diff --git a/target-mips/cpu.c b/target-mips/cpu.c index cab9572..60a3faf 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c
@@ -29,11 +29,6 @@ MIPSCPUClass *mcc = MIPS_CPU_GET_CLASS(cpu); CPUMIPSState *env = &cpu->env; - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(s, 0); - } - mcc->parent_reset(s); memset(env, 0, offsetof(CPUMIPSState, breakpoints));
diff --git a/target-moxie/cpu.c b/target-moxie/cpu.c index 7314d4b..92ca594 100644 --- a/target-moxie/cpu.c +++ b/target-moxie/cpu.c
@@ -28,11 +28,6 @@ MoxieCPUClass *mcc = MOXIE_CPU_GET_CLASS(cpu); CPUMoxieState *env = &cpu->env; - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(s, 0); - } - mcc->parent_reset(s); memset(env, 0, offsetof(CPUMoxieState, breakpoints));
diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index 0dc60c9..6d40f1b 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c
@@ -26,11 +26,6 @@ OpenRISCCPU *cpu = OPENRISC_CPU(s); OpenRISCCPUClass *occ = OPENRISC_CPU_GET_CLASS(cpu); - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(s, 0); - } - occ->parent_reset(s); memset(&cpu->env, 0, offsetof(CPUOpenRISCState, breakpoints));
diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 43eec67..b62f04a 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c
@@ -8171,11 +8171,6 @@ CPUPPCState *env = &cpu->env; target_ulong msr; - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(s, 0); - } - pcc->parent_reset(s); msr = (target_ulong)0;
diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index 732d393..1ef2fc0 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c
@@ -65,11 +65,6 @@ S390CPUClass *scc = S390_CPU_GET_CLASS(cpu); CPUS390XState *env = &cpu->env; - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(s, 0); - } - s390_del_running_cpu(cpu); scc->parent_reset(s);
diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index 653acec..03487eb 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c
@@ -31,11 +31,6 @@ SuperHCPUClass *scc = SUPERH_CPU_GET_CLASS(cpu); CPUSH4State *env = &cpu->env; - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(s, 0); - } - scc->parent_reset(s); memset(env, 0, offsetof(CPUSH4State, breakpoints));
diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index 4cbb206..87c3a50 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c
@@ -30,11 +30,6 @@ SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(cpu); CPUSPARCState *env = &cpu->env; - if (qemu_loglevel_mask(CPU_LOG_RESET)) { - qemu_log("CPU Reset (CPU %d)\n", s->cpu_index); - log_cpu_state(s, 0); - } - scc->parent_reset(s); memset(env, 0, offsetof(CPUSPARCState, breakpoints));