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bellard664e0f12005-01-08 18:58:29 +00001/*
balrog222a3332008-10-04 03:27:44 +00002 * MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI support
ths5fafdf22007-09-16 21:08:06 +00003 *
bellard664e0f12005-01-08 18:58:29 +00004 * Copyright (c) 2005 Fabrice Bellard
balrog222a3332008-10-04 03:27:44 +00005 * Copyright (c) 2008 Intel Corporation <andrew.zaborowski@intel.com>
bellard664e0f12005-01-08 18:58:29 +00006 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
Blue Swirl8167ee82009-07-16 20:47:01 +000018 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
bellard664e0f12005-01-08 18:58:29 +000019 */
20#if SHIFT == 0
21#define Reg MMXReg
Blue Swirl001faf32009-05-13 17:53:17 +000022#define XMM_ONLY(...)
bellard664e0f12005-01-08 18:58:29 +000023#define B(n) MMX_B(n)
24#define W(n) MMX_W(n)
25#define L(n) MMX_L(n)
26#define Q(n) q
27#define SUFFIX _mmx
28#else
29#define Reg XMMReg
Blue Swirl001faf32009-05-13 17:53:17 +000030#define XMM_ONLY(...) __VA_ARGS__
bellard664e0f12005-01-08 18:58:29 +000031#define B(n) XMM_B(n)
32#define W(n) XMM_W(n)
33#define L(n) XMM_L(n)
34#define Q(n) XMM_Q(n)
35#define SUFFIX _xmm
36#endif
37
Blue Swirld3eb5ea2012-04-28 21:28:09 +000038void glue(helper_psrlw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +000039{
bellard664e0f12005-01-08 18:58:29 +000040 int shift;
41
bellard664e0f12005-01-08 18:58:29 +000042 if (s->Q(0) > 15) {
43 d->Q(0) = 0;
44#if SHIFT == 1
45 d->Q(1) = 0;
46#endif
47 } else {
48 shift = s->B(0);
49 d->W(0) >>= shift;
50 d->W(1) >>= shift;
51 d->W(2) >>= shift;
52 d->W(3) >>= shift;
53#if SHIFT == 1
54 d->W(4) >>= shift;
55 d->W(5) >>= shift;
56 d->W(6) >>= shift;
57 d->W(7) >>= shift;
58#endif
59 }
60}
61
Blue Swirld3eb5ea2012-04-28 21:28:09 +000062void glue(helper_psraw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +000063{
bellard664e0f12005-01-08 18:58:29 +000064 int shift;
65
bellard664e0f12005-01-08 18:58:29 +000066 if (s->Q(0) > 15) {
67 shift = 15;
68 } else {
69 shift = s->B(0);
70 }
71 d->W(0) = (int16_t)d->W(0) >> shift;
72 d->W(1) = (int16_t)d->W(1) >> shift;
73 d->W(2) = (int16_t)d->W(2) >> shift;
74 d->W(3) = (int16_t)d->W(3) >> shift;
75#if SHIFT == 1
76 d->W(4) = (int16_t)d->W(4) >> shift;
77 d->W(5) = (int16_t)d->W(5) >> shift;
78 d->W(6) = (int16_t)d->W(6) >> shift;
79 d->W(7) = (int16_t)d->W(7) >> shift;
80#endif
81}
82
Blue Swirld3eb5ea2012-04-28 21:28:09 +000083void glue(helper_psllw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +000084{
bellard664e0f12005-01-08 18:58:29 +000085 int shift;
86
bellard664e0f12005-01-08 18:58:29 +000087 if (s->Q(0) > 15) {
88 d->Q(0) = 0;
89#if SHIFT == 1
90 d->Q(1) = 0;
91#endif
92 } else {
93 shift = s->B(0);
94 d->W(0) <<= shift;
95 d->W(1) <<= shift;
96 d->W(2) <<= shift;
97 d->W(3) <<= shift;
98#if SHIFT == 1
99 d->W(4) <<= shift;
100 d->W(5) <<= shift;
101 d->W(6) <<= shift;
102 d->W(7) <<= shift;
103#endif
104 }
105}
106
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000107void glue(helper_psrld, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +0000108{
bellard664e0f12005-01-08 18:58:29 +0000109 int shift;
110
bellard664e0f12005-01-08 18:58:29 +0000111 if (s->Q(0) > 31) {
112 d->Q(0) = 0;
113#if SHIFT == 1
114 d->Q(1) = 0;
115#endif
116 } else {
117 shift = s->B(0);
118 d->L(0) >>= shift;
119 d->L(1) >>= shift;
120#if SHIFT == 1
121 d->L(2) >>= shift;
122 d->L(3) >>= shift;
123#endif
124 }
125}
126
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000127void glue(helper_psrad, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +0000128{
bellard664e0f12005-01-08 18:58:29 +0000129 int shift;
130
bellard664e0f12005-01-08 18:58:29 +0000131 if (s->Q(0) > 31) {
132 shift = 31;
133 } else {
134 shift = s->B(0);
135 }
136 d->L(0) = (int32_t)d->L(0) >> shift;
137 d->L(1) = (int32_t)d->L(1) >> shift;
138#if SHIFT == 1
139 d->L(2) = (int32_t)d->L(2) >> shift;
140 d->L(3) = (int32_t)d->L(3) >> shift;
141#endif
142}
143
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000144void glue(helper_pslld, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +0000145{
bellard664e0f12005-01-08 18:58:29 +0000146 int shift;
147
bellard664e0f12005-01-08 18:58:29 +0000148 if (s->Q(0) > 31) {
149 d->Q(0) = 0;
150#if SHIFT == 1
151 d->Q(1) = 0;
152#endif
153 } else {
154 shift = s->B(0);
155 d->L(0) <<= shift;
156 d->L(1) <<= shift;
157#if SHIFT == 1
158 d->L(2) <<= shift;
159 d->L(3) <<= shift;
160#endif
161 }
162}
163
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000164void glue(helper_psrlq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +0000165{
bellard664e0f12005-01-08 18:58:29 +0000166 int shift;
167
bellard664e0f12005-01-08 18:58:29 +0000168 if (s->Q(0) > 63) {
169 d->Q(0) = 0;
170#if SHIFT == 1
171 d->Q(1) = 0;
172#endif
173 } else {
174 shift = s->B(0);
175 d->Q(0) >>= shift;
176#if SHIFT == 1
177 d->Q(1) >>= shift;
178#endif
179 }
180}
181
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000182void glue(helper_psllq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +0000183{
bellard664e0f12005-01-08 18:58:29 +0000184 int shift;
185
bellard664e0f12005-01-08 18:58:29 +0000186 if (s->Q(0) > 63) {
187 d->Q(0) = 0;
188#if SHIFT == 1
189 d->Q(1) = 0;
190#endif
191 } else {
192 shift = s->B(0);
193 d->Q(0) <<= shift;
194#if SHIFT == 1
195 d->Q(1) <<= shift;
196#endif
197 }
198}
199
200#if SHIFT == 1
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000201void glue(helper_psrldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +0000202{
bellard664e0f12005-01-08 18:58:29 +0000203 int shift, i;
204
bellard664e0f12005-01-08 18:58:29 +0000205 shift = s->L(0);
Blue Swirle01d9d32012-04-29 08:54:44 +0000206 if (shift > 16) {
bellard664e0f12005-01-08 18:58:29 +0000207 shift = 16;
Blue Swirle01d9d32012-04-29 08:54:44 +0000208 }
209 for (i = 0; i < 16 - shift; i++) {
bellard664e0f12005-01-08 18:58:29 +0000210 d->B(i) = d->B(i + shift);
Blue Swirle01d9d32012-04-29 08:54:44 +0000211 }
212 for (i = 16 - shift; i < 16; i++) {
bellard664e0f12005-01-08 18:58:29 +0000213 d->B(i) = 0;
Blue Swirle01d9d32012-04-29 08:54:44 +0000214 }
bellard664e0f12005-01-08 18:58:29 +0000215}
216
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000217void glue(helper_pslldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +0000218{
bellard664e0f12005-01-08 18:58:29 +0000219 int shift, i;
220
bellard664e0f12005-01-08 18:58:29 +0000221 shift = s->L(0);
Blue Swirle01d9d32012-04-29 08:54:44 +0000222 if (shift > 16) {
bellard664e0f12005-01-08 18:58:29 +0000223 shift = 16;
Blue Swirle01d9d32012-04-29 08:54:44 +0000224 }
225 for (i = 15; i >= shift; i--) {
bellard664e0f12005-01-08 18:58:29 +0000226 d->B(i) = d->B(i - shift);
Blue Swirle01d9d32012-04-29 08:54:44 +0000227 }
228 for (i = 0; i < shift; i++) {
bellard664e0f12005-01-08 18:58:29 +0000229 d->B(i) = 0;
Blue Swirle01d9d32012-04-29 08:54:44 +0000230 }
bellard664e0f12005-01-08 18:58:29 +0000231}
232#endif
233
Blue Swirle01d9d32012-04-29 08:54:44 +0000234#define SSE_HELPER_B(name, F) \
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000235 void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
Blue Swirle01d9d32012-04-29 08:54:44 +0000236 { \
237 d->B(0) = F(d->B(0), s->B(0)); \
238 d->B(1) = F(d->B(1), s->B(1)); \
239 d->B(2) = F(d->B(2), s->B(2)); \
240 d->B(3) = F(d->B(3), s->B(3)); \
241 d->B(4) = F(d->B(4), s->B(4)); \
242 d->B(5) = F(d->B(5), s->B(5)); \
243 d->B(6) = F(d->B(6), s->B(6)); \
244 d->B(7) = F(d->B(7), s->B(7)); \
245 XMM_ONLY( \
246 d->B(8) = F(d->B(8), s->B(8)); \
247 d->B(9) = F(d->B(9), s->B(9)); \
248 d->B(10) = F(d->B(10), s->B(10)); \
249 d->B(11) = F(d->B(11), s->B(11)); \
250 d->B(12) = F(d->B(12), s->B(12)); \
251 d->B(13) = F(d->B(13), s->B(13)); \
252 d->B(14) = F(d->B(14), s->B(14)); \
253 d->B(15) = F(d->B(15), s->B(15)); \
254 ) \
255 }
bellard664e0f12005-01-08 18:58:29 +0000256
Blue Swirle01d9d32012-04-29 08:54:44 +0000257#define SSE_HELPER_W(name, F) \
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000258 void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
Blue Swirle01d9d32012-04-29 08:54:44 +0000259 { \
260 d->W(0) = F(d->W(0), s->W(0)); \
261 d->W(1) = F(d->W(1), s->W(1)); \
262 d->W(2) = F(d->W(2), s->W(2)); \
263 d->W(3) = F(d->W(3), s->W(3)); \
264 XMM_ONLY( \
265 d->W(4) = F(d->W(4), s->W(4)); \
266 d->W(5) = F(d->W(5), s->W(5)); \
267 d->W(6) = F(d->W(6), s->W(6)); \
268 d->W(7) = F(d->W(7), s->W(7)); \
269 ) \
270 }
bellard664e0f12005-01-08 18:58:29 +0000271
Blue Swirle01d9d32012-04-29 08:54:44 +0000272#define SSE_HELPER_L(name, F) \
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000273 void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
Blue Swirle01d9d32012-04-29 08:54:44 +0000274 { \
275 d->L(0) = F(d->L(0), s->L(0)); \
276 d->L(1) = F(d->L(1), s->L(1)); \
277 XMM_ONLY( \
278 d->L(2) = F(d->L(2), s->L(2)); \
279 d->L(3) = F(d->L(3), s->L(3)); \
280 ) \
281 }
bellard664e0f12005-01-08 18:58:29 +0000282
Blue Swirle01d9d32012-04-29 08:54:44 +0000283#define SSE_HELPER_Q(name, F) \
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000284 void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
Blue Swirle01d9d32012-04-29 08:54:44 +0000285 { \
286 d->Q(0) = F(d->Q(0), s->Q(0)); \
287 XMM_ONLY( \
288 d->Q(1) = F(d->Q(1), s->Q(1)); \
289 ) \
290 }
bellard664e0f12005-01-08 18:58:29 +0000291
292#if SHIFT == 0
293static inline int satub(int x)
294{
Blue Swirle01d9d32012-04-29 08:54:44 +0000295 if (x < 0) {
bellard664e0f12005-01-08 18:58:29 +0000296 return 0;
Blue Swirle01d9d32012-04-29 08:54:44 +0000297 } else if (x > 255) {
bellard664e0f12005-01-08 18:58:29 +0000298 return 255;
Blue Swirle01d9d32012-04-29 08:54:44 +0000299 } else {
bellard664e0f12005-01-08 18:58:29 +0000300 return x;
Blue Swirle01d9d32012-04-29 08:54:44 +0000301 }
bellard664e0f12005-01-08 18:58:29 +0000302}
303
304static inline int satuw(int x)
305{
Blue Swirle01d9d32012-04-29 08:54:44 +0000306 if (x < 0) {
bellard664e0f12005-01-08 18:58:29 +0000307 return 0;
Blue Swirle01d9d32012-04-29 08:54:44 +0000308 } else if (x > 65535) {
bellard664e0f12005-01-08 18:58:29 +0000309 return 65535;
Blue Swirle01d9d32012-04-29 08:54:44 +0000310 } else {
bellard664e0f12005-01-08 18:58:29 +0000311 return x;
Blue Swirle01d9d32012-04-29 08:54:44 +0000312 }
bellard664e0f12005-01-08 18:58:29 +0000313}
314
315static inline int satsb(int x)
316{
Blue Swirle01d9d32012-04-29 08:54:44 +0000317 if (x < -128) {
bellard664e0f12005-01-08 18:58:29 +0000318 return -128;
Blue Swirle01d9d32012-04-29 08:54:44 +0000319 } else if (x > 127) {
bellard664e0f12005-01-08 18:58:29 +0000320 return 127;
Blue Swirle01d9d32012-04-29 08:54:44 +0000321 } else {
bellard664e0f12005-01-08 18:58:29 +0000322 return x;
Blue Swirle01d9d32012-04-29 08:54:44 +0000323 }
bellard664e0f12005-01-08 18:58:29 +0000324}
325
326static inline int satsw(int x)
327{
Blue Swirle01d9d32012-04-29 08:54:44 +0000328 if (x < -32768) {
bellard664e0f12005-01-08 18:58:29 +0000329 return -32768;
Blue Swirle01d9d32012-04-29 08:54:44 +0000330 } else if (x > 32767) {
bellard664e0f12005-01-08 18:58:29 +0000331 return 32767;
Blue Swirle01d9d32012-04-29 08:54:44 +0000332 } else {
bellard664e0f12005-01-08 18:58:29 +0000333 return x;
Blue Swirle01d9d32012-04-29 08:54:44 +0000334 }
bellard664e0f12005-01-08 18:58:29 +0000335}
336
337#define FADD(a, b) ((a) + (b))
338#define FADDUB(a, b) satub((a) + (b))
339#define FADDUW(a, b) satuw((a) + (b))
340#define FADDSB(a, b) satsb((int8_t)(a) + (int8_t)(b))
341#define FADDSW(a, b) satsw((int16_t)(a) + (int16_t)(b))
342
343#define FSUB(a, b) ((a) - (b))
344#define FSUBUB(a, b) satub((a) - (b))
345#define FSUBUW(a, b) satuw((a) - (b))
346#define FSUBSB(a, b) satsb((int8_t)(a) - (int8_t)(b))
347#define FSUBSW(a, b) satsw((int16_t)(a) - (int16_t)(b))
348#define FMINUB(a, b) ((a) < (b)) ? (a) : (b)
349#define FMINSW(a, b) ((int16_t)(a) < (int16_t)(b)) ? (a) : (b)
350#define FMAXUB(a, b) ((a) > (b)) ? (a) : (b)
351#define FMAXSW(a, b) ((int16_t)(a) > (int16_t)(b)) ? (a) : (b)
352
Blue Swirle01d9d32012-04-29 08:54:44 +0000353#define FAND(a, b) ((a) & (b))
bellard664e0f12005-01-08 18:58:29 +0000354#define FANDN(a, b) ((~(a)) & (b))
Blue Swirle01d9d32012-04-29 08:54:44 +0000355#define FOR(a, b) ((a) | (b))
356#define FXOR(a, b) ((a) ^ (b))
bellard664e0f12005-01-08 18:58:29 +0000357
Blue Swirle01d9d32012-04-29 08:54:44 +0000358#define FCMPGTB(a, b) ((int8_t)(a) > (int8_t)(b) ? -1 : 0)
359#define FCMPGTW(a, b) ((int16_t)(a) > (int16_t)(b) ? -1 : 0)
360#define FCMPGTL(a, b) ((int32_t)(a) > (int32_t)(b) ? -1 : 0)
361#define FCMPEQ(a, b) ((a) == (b) ? -1 : 0)
bellard664e0f12005-01-08 18:58:29 +0000362
Blue Swirle01d9d32012-04-29 08:54:44 +0000363#define FMULLW(a, b) ((a) * (b))
364#define FMULHRW(a, b) (((int16_t)(a) * (int16_t)(b) + 0x8000) >> 16)
365#define FMULHUW(a, b) ((a) * (b) >> 16)
366#define FMULHW(a, b) ((int16_t)(a) * (int16_t)(b) >> 16)
bellard664e0f12005-01-08 18:58:29 +0000367
Blue Swirle01d9d32012-04-29 08:54:44 +0000368#define FAVG(a, b) (((a) + (b) + 1) >> 1)
bellard664e0f12005-01-08 18:58:29 +0000369#endif
370
bellard5af45182008-05-12 16:47:36 +0000371SSE_HELPER_B(helper_paddb, FADD)
372SSE_HELPER_W(helper_paddw, FADD)
373SSE_HELPER_L(helper_paddl, FADD)
374SSE_HELPER_Q(helper_paddq, FADD)
bellard664e0f12005-01-08 18:58:29 +0000375
bellard5af45182008-05-12 16:47:36 +0000376SSE_HELPER_B(helper_psubb, FSUB)
377SSE_HELPER_W(helper_psubw, FSUB)
378SSE_HELPER_L(helper_psubl, FSUB)
379SSE_HELPER_Q(helper_psubq, FSUB)
bellard664e0f12005-01-08 18:58:29 +0000380
bellard5af45182008-05-12 16:47:36 +0000381SSE_HELPER_B(helper_paddusb, FADDUB)
382SSE_HELPER_B(helper_paddsb, FADDSB)
383SSE_HELPER_B(helper_psubusb, FSUBUB)
384SSE_HELPER_B(helper_psubsb, FSUBSB)
bellard664e0f12005-01-08 18:58:29 +0000385
bellard5af45182008-05-12 16:47:36 +0000386SSE_HELPER_W(helper_paddusw, FADDUW)
387SSE_HELPER_W(helper_paddsw, FADDSW)
388SSE_HELPER_W(helper_psubusw, FSUBUW)
389SSE_HELPER_W(helper_psubsw, FSUBSW)
bellard664e0f12005-01-08 18:58:29 +0000390
bellard5af45182008-05-12 16:47:36 +0000391SSE_HELPER_B(helper_pminub, FMINUB)
392SSE_HELPER_B(helper_pmaxub, FMAXUB)
bellard664e0f12005-01-08 18:58:29 +0000393
bellard5af45182008-05-12 16:47:36 +0000394SSE_HELPER_W(helper_pminsw, FMINSW)
395SSE_HELPER_W(helper_pmaxsw, FMAXSW)
bellard664e0f12005-01-08 18:58:29 +0000396
bellard5af45182008-05-12 16:47:36 +0000397SSE_HELPER_Q(helper_pand, FAND)
398SSE_HELPER_Q(helper_pandn, FANDN)
399SSE_HELPER_Q(helper_por, FOR)
400SSE_HELPER_Q(helper_pxor, FXOR)
bellard664e0f12005-01-08 18:58:29 +0000401
bellard5af45182008-05-12 16:47:36 +0000402SSE_HELPER_B(helper_pcmpgtb, FCMPGTB)
403SSE_HELPER_W(helper_pcmpgtw, FCMPGTW)
404SSE_HELPER_L(helper_pcmpgtl, FCMPGTL)
bellard664e0f12005-01-08 18:58:29 +0000405
bellard5af45182008-05-12 16:47:36 +0000406SSE_HELPER_B(helper_pcmpeqb, FCMPEQ)
407SSE_HELPER_W(helper_pcmpeqw, FCMPEQ)
408SSE_HELPER_L(helper_pcmpeql, FCMPEQ)
bellard664e0f12005-01-08 18:58:29 +0000409
bellard5af45182008-05-12 16:47:36 +0000410SSE_HELPER_W(helper_pmullw, FMULLW)
aurel32a35f3ec2008-04-08 19:51:29 +0000411#if SHIFT == 0
bellard5af45182008-05-12 16:47:36 +0000412SSE_HELPER_W(helper_pmulhrw, FMULHRW)
aurel32a35f3ec2008-04-08 19:51:29 +0000413#endif
bellard5af45182008-05-12 16:47:36 +0000414SSE_HELPER_W(helper_pmulhuw, FMULHUW)
415SSE_HELPER_W(helper_pmulhw, FMULHW)
bellard664e0f12005-01-08 18:58:29 +0000416
bellard5af45182008-05-12 16:47:36 +0000417SSE_HELPER_B(helper_pavgb, FAVG)
418SSE_HELPER_W(helper_pavgw, FAVG)
bellard664e0f12005-01-08 18:58:29 +0000419
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000420void glue(helper_pmuludq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +0000421{
bellard664e0f12005-01-08 18:58:29 +0000422 d->Q(0) = (uint64_t)s->L(0) * (uint64_t)d->L(0);
423#if SHIFT == 1
424 d->Q(1) = (uint64_t)s->L(2) * (uint64_t)d->L(2);
425#endif
426}
427
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000428void glue(helper_pmaddwd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +0000429{
430 int i;
bellard664e0f12005-01-08 18:58:29 +0000431
Blue Swirle01d9d32012-04-29 08:54:44 +0000432 for (i = 0; i < (2 << SHIFT); i++) {
433 d->L(i) = (int16_t)s->W(2 * i) * (int16_t)d->W(2 * i) +
434 (int16_t)s->W(2 * i + 1) * (int16_t)d->W(2 * i + 1);
bellard664e0f12005-01-08 18:58:29 +0000435 }
436}
437
438#if SHIFT == 0
439static inline int abs1(int a)
440{
Blue Swirle01d9d32012-04-29 08:54:44 +0000441 if (a < 0) {
bellard664e0f12005-01-08 18:58:29 +0000442 return -a;
Blue Swirle01d9d32012-04-29 08:54:44 +0000443 } else {
bellard664e0f12005-01-08 18:58:29 +0000444 return a;
Blue Swirle01d9d32012-04-29 08:54:44 +0000445 }
bellard664e0f12005-01-08 18:58:29 +0000446}
447#endif
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000448void glue(helper_psadbw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +0000449{
450 unsigned int val;
bellard664e0f12005-01-08 18:58:29 +0000451
452 val = 0;
453 val += abs1(d->B(0) - s->B(0));
454 val += abs1(d->B(1) - s->B(1));
455 val += abs1(d->B(2) - s->B(2));
456 val += abs1(d->B(3) - s->B(3));
457 val += abs1(d->B(4) - s->B(4));
458 val += abs1(d->B(5) - s->B(5));
459 val += abs1(d->B(6) - s->B(6));
460 val += abs1(d->B(7) - s->B(7));
461 d->Q(0) = val;
462#if SHIFT == 1
463 val = 0;
464 val += abs1(d->B(8) - s->B(8));
465 val += abs1(d->B(9) - s->B(9));
466 val += abs1(d->B(10) - s->B(10));
467 val += abs1(d->B(11) - s->B(11));
468 val += abs1(d->B(12) - s->B(12));
469 val += abs1(d->B(13) - s->B(13));
470 val += abs1(d->B(14) - s->B(14));
471 val += abs1(d->B(15) - s->B(15));
472 d->Q(1) = val;
473#endif
474}
475
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000476void glue(helper_maskmov, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
477 target_ulong a0)
bellard664e0f12005-01-08 18:58:29 +0000478{
479 int i;
Blue Swirle01d9d32012-04-29 08:54:44 +0000480
481 for (i = 0; i < (8 << SHIFT); i++) {
482 if (s->B(i) & 0x80) {
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000483 cpu_stb_data(env, a0 + i, d->B(i));
Blue Swirle01d9d32012-04-29 08:54:44 +0000484 }
bellard664e0f12005-01-08 18:58:29 +0000485 }
486}
487
Blue Swirle01d9d32012-04-29 08:54:44 +0000488void glue(helper_movl_mm_T0, SUFFIX)(Reg *d, uint32_t val)
bellard664e0f12005-01-08 18:58:29 +0000489{
bellard5af45182008-05-12 16:47:36 +0000490 d->L(0) = val;
bellard664e0f12005-01-08 18:58:29 +0000491 d->L(1) = 0;
492#if SHIFT == 1
493 d->Q(1) = 0;
494#endif
495}
496
bellarddabd98d2007-01-16 19:28:58 +0000497#ifdef TARGET_X86_64
Blue Swirle01d9d32012-04-29 08:54:44 +0000498void glue(helper_movq_mm_T0, SUFFIX)(Reg *d, uint64_t val)
bellarddabd98d2007-01-16 19:28:58 +0000499{
bellard5af45182008-05-12 16:47:36 +0000500 d->Q(0) = val;
bellarddabd98d2007-01-16 19:28:58 +0000501#if SHIFT == 1
502 d->Q(1) = 0;
503#endif
504}
bellarddabd98d2007-01-16 19:28:58 +0000505#endif
506
bellard664e0f12005-01-08 18:58:29 +0000507#if SHIFT == 0
Blue Swirle01d9d32012-04-29 08:54:44 +0000508void glue(helper_pshufw, SUFFIX)(Reg *d, Reg *s, int order)
bellard664e0f12005-01-08 18:58:29 +0000509{
bellard5af45182008-05-12 16:47:36 +0000510 Reg r;
Blue Swirle01d9d32012-04-29 08:54:44 +0000511
bellard664e0f12005-01-08 18:58:29 +0000512 r.W(0) = s->W(order & 3);
513 r.W(1) = s->W((order >> 2) & 3);
514 r.W(2) = s->W((order >> 4) & 3);
515 r.W(3) = s->W((order >> 6) & 3);
516 *d = r;
517}
518#else
bellard5af45182008-05-12 16:47:36 +0000519void helper_shufps(Reg *d, Reg *s, int order)
bellardd52cf7a2005-01-16 01:07:28 +0000520{
bellard5af45182008-05-12 16:47:36 +0000521 Reg r;
Blue Swirle01d9d32012-04-29 08:54:44 +0000522
bellardd52cf7a2005-01-16 01:07:28 +0000523 r.L(0) = d->L(order & 3);
524 r.L(1) = d->L((order >> 2) & 3);
525 r.L(2) = s->L((order >> 4) & 3);
526 r.L(3) = s->L((order >> 6) & 3);
527 *d = r;
528}
529
bellard5af45182008-05-12 16:47:36 +0000530void helper_shufpd(Reg *d, Reg *s, int order)
bellard664e0f12005-01-08 18:58:29 +0000531{
bellard5af45182008-05-12 16:47:36 +0000532 Reg r;
Blue Swirle01d9d32012-04-29 08:54:44 +0000533
bellardd52cf7a2005-01-16 01:07:28 +0000534 r.Q(0) = d->Q(order & 1);
bellard664e0f12005-01-08 18:58:29 +0000535 r.Q(1) = s->Q((order >> 1) & 1);
536 *d = r;
537}
538
Blue Swirle01d9d32012-04-29 08:54:44 +0000539void glue(helper_pshufd, SUFFIX)(Reg *d, Reg *s, int order)
bellard664e0f12005-01-08 18:58:29 +0000540{
bellard5af45182008-05-12 16:47:36 +0000541 Reg r;
Blue Swirle01d9d32012-04-29 08:54:44 +0000542
bellard664e0f12005-01-08 18:58:29 +0000543 r.L(0) = s->L(order & 3);
544 r.L(1) = s->L((order >> 2) & 3);
545 r.L(2) = s->L((order >> 4) & 3);
546 r.L(3) = s->L((order >> 6) & 3);
547 *d = r;
548}
549
Blue Swirle01d9d32012-04-29 08:54:44 +0000550void glue(helper_pshuflw, SUFFIX)(Reg *d, Reg *s, int order)
bellard664e0f12005-01-08 18:58:29 +0000551{
bellard5af45182008-05-12 16:47:36 +0000552 Reg r;
Blue Swirle01d9d32012-04-29 08:54:44 +0000553
bellard664e0f12005-01-08 18:58:29 +0000554 r.W(0) = s->W(order & 3);
555 r.W(1) = s->W((order >> 2) & 3);
556 r.W(2) = s->W((order >> 4) & 3);
557 r.W(3) = s->W((order >> 6) & 3);
558 r.Q(1) = s->Q(1);
559 *d = r;
560}
561
Blue Swirle01d9d32012-04-29 08:54:44 +0000562void glue(helper_pshufhw, SUFFIX)(Reg *d, Reg *s, int order)
bellard664e0f12005-01-08 18:58:29 +0000563{
bellard5af45182008-05-12 16:47:36 +0000564 Reg r;
Blue Swirle01d9d32012-04-29 08:54:44 +0000565
bellard664e0f12005-01-08 18:58:29 +0000566 r.Q(0) = s->Q(0);
567 r.W(4) = s->W(4 + (order & 3));
568 r.W(5) = s->W(4 + ((order >> 2) & 3));
569 r.W(6) = s->W(4 + ((order >> 4) & 3));
570 r.W(7) = s->W(4 + ((order >> 6) & 3));
571 *d = r;
572}
573#endif
574
575#if SHIFT == 1
576/* FPU ops */
577/* XXX: not accurate */
578
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000579#define SSE_HELPER_S(name, F) \
580 void helper_ ## name ## ps(CPUX86State *env, Reg *d, Reg *s) \
581 { \
582 d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \
583 d->XMM_S(1) = F(32, d->XMM_S(1), s->XMM_S(1)); \
584 d->XMM_S(2) = F(32, d->XMM_S(2), s->XMM_S(2)); \
585 d->XMM_S(3) = F(32, d->XMM_S(3), s->XMM_S(3)); \
586 } \
587 \
588 void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *s) \
589 { \
590 d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \
591 } \
592 \
593 void helper_ ## name ## pd(CPUX86State *env, Reg *d, Reg *s) \
594 { \
595 d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \
596 d->XMM_D(1) = F(64, d->XMM_D(1), s->XMM_D(1)); \
597 } \
598 \
599 void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *s) \
600 { \
601 d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \
Blue Swirle01d9d32012-04-29 08:54:44 +0000602 }
bellard664e0f12005-01-08 18:58:29 +0000603
bellard7a0e1f42005-03-13 17:01:47 +0000604#define FPU_ADD(size, a, b) float ## size ## _add(a, b, &env->sse_status)
605#define FPU_SUB(size, a, b) float ## size ## _sub(a, b, &env->sse_status)
606#define FPU_MUL(size, a, b) float ## size ## _mul(a, b, &env->sse_status)
607#define FPU_DIV(size, a, b) float ## size ## _div(a, b, &env->sse_status)
bellard7a0e1f42005-03-13 17:01:47 +0000608#define FPU_SQRT(size, a, b) float ## size ## _sqrt(b, &env->sse_status)
bellard664e0f12005-01-08 18:58:29 +0000609
Aurelien Jarnoa4d1f142012-01-07 15:20:11 +0100610/* Note that the choice of comparison op here is important to get the
611 * special cases right: for min and max Intel specifies that (-0,0),
612 * (NaN, anything) and (anything, NaN) return the second argument.
613 */
Blue Swirle01d9d32012-04-29 08:54:44 +0000614#define FPU_MIN(size, a, b) \
615 (float ## size ## _lt(a, b, &env->sse_status) ? (a) : (b))
616#define FPU_MAX(size, a, b) \
617 (float ## size ## _lt(b, a, &env->sse_status) ? (a) : (b))
Aurelien Jarnoa4d1f142012-01-07 15:20:11 +0100618
bellard5af45182008-05-12 16:47:36 +0000619SSE_HELPER_S(add, FPU_ADD)
620SSE_HELPER_S(sub, FPU_SUB)
621SSE_HELPER_S(mul, FPU_MUL)
622SSE_HELPER_S(div, FPU_DIV)
623SSE_HELPER_S(min, FPU_MIN)
624SSE_HELPER_S(max, FPU_MAX)
625SSE_HELPER_S(sqrt, FPU_SQRT)
bellard664e0f12005-01-08 18:58:29 +0000626
627
628/* float to float conversions */
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000629void helper_cvtps2pd(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +0000630{
bellard8422b112005-03-20 10:39:24 +0000631 float32 s0, s1;
Blue Swirle01d9d32012-04-29 08:54:44 +0000632
bellard664e0f12005-01-08 18:58:29 +0000633 s0 = s->XMM_S(0);
634 s1 = s->XMM_S(1);
bellard7a0e1f42005-03-13 17:01:47 +0000635 d->XMM_D(0) = float32_to_float64(s0, &env->sse_status);
636 d->XMM_D(1) = float32_to_float64(s1, &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000637}
638
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000639void helper_cvtpd2ps(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +0000640{
bellard7a0e1f42005-03-13 17:01:47 +0000641 d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status);
642 d->XMM_S(1) = float64_to_float32(s->XMM_D(1), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000643 d->Q(1) = 0;
644}
645
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000646void helper_cvtss2sd(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +0000647{
bellard7a0e1f42005-03-13 17:01:47 +0000648 d->XMM_D(0) = float32_to_float64(s->XMM_S(0), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000649}
650
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000651void helper_cvtsd2ss(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +0000652{
bellard7a0e1f42005-03-13 17:01:47 +0000653 d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000654}
655
656/* integer to float */
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000657void helper_cvtdq2ps(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +0000658{
bellard7a0e1f42005-03-13 17:01:47 +0000659 d->XMM_S(0) = int32_to_float32(s->XMM_L(0), &env->sse_status);
660 d->XMM_S(1) = int32_to_float32(s->XMM_L(1), &env->sse_status);
661 d->XMM_S(2) = int32_to_float32(s->XMM_L(2), &env->sse_status);
662 d->XMM_S(3) = int32_to_float32(s->XMM_L(3), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000663}
664
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000665void helper_cvtdq2pd(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +0000666{
bellard664e0f12005-01-08 18:58:29 +0000667 int32_t l0, l1;
Blue Swirle01d9d32012-04-29 08:54:44 +0000668
bellard664e0f12005-01-08 18:58:29 +0000669 l0 = (int32_t)s->XMM_L(0);
670 l1 = (int32_t)s->XMM_L(1);
bellard7a0e1f42005-03-13 17:01:47 +0000671 d->XMM_D(0) = int32_to_float64(l0, &env->sse_status);
672 d->XMM_D(1) = int32_to_float64(l1, &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000673}
674
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000675void helper_cvtpi2ps(CPUX86State *env, XMMReg *d, MMXReg *s)
bellard664e0f12005-01-08 18:58:29 +0000676{
bellard7a0e1f42005-03-13 17:01:47 +0000677 d->XMM_S(0) = int32_to_float32(s->MMX_L(0), &env->sse_status);
678 d->XMM_S(1) = int32_to_float32(s->MMX_L(1), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000679}
680
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000681void helper_cvtpi2pd(CPUX86State *env, XMMReg *d, MMXReg *s)
bellard664e0f12005-01-08 18:58:29 +0000682{
bellard7a0e1f42005-03-13 17:01:47 +0000683 d->XMM_D(0) = int32_to_float64(s->MMX_L(0), &env->sse_status);
684 d->XMM_D(1) = int32_to_float64(s->MMX_L(1), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000685}
686
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000687void helper_cvtsi2ss(CPUX86State *env, XMMReg *d, uint32_t val)
bellard664e0f12005-01-08 18:58:29 +0000688{
bellard5af45182008-05-12 16:47:36 +0000689 d->XMM_S(0) = int32_to_float32(val, &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000690}
691
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000692void helper_cvtsi2sd(CPUX86State *env, XMMReg *d, uint32_t val)
bellard664e0f12005-01-08 18:58:29 +0000693{
bellard5af45182008-05-12 16:47:36 +0000694 d->XMM_D(0) = int32_to_float64(val, &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000695}
696
697#ifdef TARGET_X86_64
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000698void helper_cvtsq2ss(CPUX86State *env, XMMReg *d, uint64_t val)
bellard664e0f12005-01-08 18:58:29 +0000699{
bellard5af45182008-05-12 16:47:36 +0000700 d->XMM_S(0) = int64_to_float32(val, &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000701}
702
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000703void helper_cvtsq2sd(CPUX86State *env, XMMReg *d, uint64_t val)
bellard664e0f12005-01-08 18:58:29 +0000704{
bellard5af45182008-05-12 16:47:36 +0000705 d->XMM_D(0) = int64_to_float64(val, &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000706}
707#endif
708
709/* float to integer */
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000710void helper_cvtps2dq(CPUX86State *env, XMMReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000711{
bellard7a0e1f42005-03-13 17:01:47 +0000712 d->XMM_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status);
713 d->XMM_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status);
714 d->XMM_L(2) = float32_to_int32(s->XMM_S(2), &env->sse_status);
715 d->XMM_L(3) = float32_to_int32(s->XMM_S(3), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000716}
717
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000718void helper_cvtpd2dq(CPUX86State *env, XMMReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000719{
bellard7a0e1f42005-03-13 17:01:47 +0000720 d->XMM_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status);
721 d->XMM_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000722 d->XMM_Q(1) = 0;
723}
724
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000725void helper_cvtps2pi(CPUX86State *env, MMXReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000726{
bellard7a0e1f42005-03-13 17:01:47 +0000727 d->MMX_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status);
728 d->MMX_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000729}
730
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000731void helper_cvtpd2pi(CPUX86State *env, MMXReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000732{
bellard7a0e1f42005-03-13 17:01:47 +0000733 d->MMX_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status);
734 d->MMX_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000735}
736
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000737int32_t helper_cvtss2si(CPUX86State *env, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000738{
bellard5af45182008-05-12 16:47:36 +0000739 return float32_to_int32(s->XMM_S(0), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000740}
741
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000742int32_t helper_cvtsd2si(CPUX86State *env, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000743{
bellard5af45182008-05-12 16:47:36 +0000744 return float64_to_int32(s->XMM_D(0), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000745}
746
747#ifdef TARGET_X86_64
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000748int64_t helper_cvtss2sq(CPUX86State *env, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000749{
bellard5af45182008-05-12 16:47:36 +0000750 return float32_to_int64(s->XMM_S(0), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000751}
752
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000753int64_t helper_cvtsd2sq(CPUX86State *env, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000754{
bellard5af45182008-05-12 16:47:36 +0000755 return float64_to_int64(s->XMM_D(0), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000756}
757#endif
758
759/* float to integer truncated */
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000760void helper_cvttps2dq(CPUX86State *env, XMMReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000761{
bellard7a0e1f42005-03-13 17:01:47 +0000762 d->XMM_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
763 d->XMM_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status);
764 d->XMM_L(2) = float32_to_int32_round_to_zero(s->XMM_S(2), &env->sse_status);
765 d->XMM_L(3) = float32_to_int32_round_to_zero(s->XMM_S(3), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000766}
767
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000768void helper_cvttpd2dq(CPUX86State *env, XMMReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000769{
bellard7a0e1f42005-03-13 17:01:47 +0000770 d->XMM_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
771 d->XMM_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000772 d->XMM_Q(1) = 0;
773}
774
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000775void helper_cvttps2pi(CPUX86State *env, MMXReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000776{
bellard7a0e1f42005-03-13 17:01:47 +0000777 d->MMX_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
778 d->MMX_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000779}
780
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000781void helper_cvttpd2pi(CPUX86State *env, MMXReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000782{
bellard7a0e1f42005-03-13 17:01:47 +0000783 d->MMX_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
784 d->MMX_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000785}
786
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000787int32_t helper_cvttss2si(CPUX86State *env, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000788{
bellard5af45182008-05-12 16:47:36 +0000789 return float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000790}
791
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000792int32_t helper_cvttsd2si(CPUX86State *env, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000793{
bellard5af45182008-05-12 16:47:36 +0000794 return float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000795}
796
797#ifdef TARGET_X86_64
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000798int64_t helper_cvttss2sq(CPUX86State *env, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000799{
bellard5af45182008-05-12 16:47:36 +0000800 return float32_to_int64_round_to_zero(s->XMM_S(0), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000801}
802
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000803int64_t helper_cvttsd2sq(CPUX86State *env, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000804{
bellard5af45182008-05-12 16:47:36 +0000805 return float64_to_int64_round_to_zero(s->XMM_D(0), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000806}
807#endif
808
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000809void helper_rsqrtps(CPUX86State *env, XMMReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000810{
Aurelien Jarnoc2ef9a82011-04-20 13:04:23 +0200811 d->XMM_S(0) = float32_div(float32_one,
812 float32_sqrt(s->XMM_S(0), &env->sse_status),
813 &env->sse_status);
814 d->XMM_S(1) = float32_div(float32_one,
815 float32_sqrt(s->XMM_S(1), &env->sse_status),
816 &env->sse_status);
817 d->XMM_S(2) = float32_div(float32_one,
818 float32_sqrt(s->XMM_S(2), &env->sse_status),
819 &env->sse_status);
820 d->XMM_S(3) = float32_div(float32_one,
821 float32_sqrt(s->XMM_S(3), &env->sse_status),
822 &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000823}
824
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000825void helper_rsqrtss(CPUX86State *env, XMMReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000826{
Aurelien Jarnoc2ef9a82011-04-20 13:04:23 +0200827 d->XMM_S(0) = float32_div(float32_one,
828 float32_sqrt(s->XMM_S(0), &env->sse_status),
829 &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000830}
831
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000832void helper_rcpps(CPUX86State *env, XMMReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000833{
Aurelien Jarnoc2ef9a82011-04-20 13:04:23 +0200834 d->XMM_S(0) = float32_div(float32_one, s->XMM_S(0), &env->sse_status);
835 d->XMM_S(1) = float32_div(float32_one, s->XMM_S(1), &env->sse_status);
836 d->XMM_S(2) = float32_div(float32_one, s->XMM_S(2), &env->sse_status);
837 d->XMM_S(3) = float32_div(float32_one, s->XMM_S(3), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000838}
839
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000840void helper_rcpss(CPUX86State *env, XMMReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000841{
Aurelien Jarnoc2ef9a82011-04-20 13:04:23 +0200842 d->XMM_S(0) = float32_div(float32_one, s->XMM_S(0), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000843}
844
Andre Przywarad9f4bb22009-09-19 00:30:48 +0200845static inline uint64_t helper_extrq(uint64_t src, int shift, int len)
846{
847 uint64_t mask;
848
849 if (len == 0) {
850 mask = ~0LL;
851 } else {
852 mask = (1ULL << len) - 1;
853 }
854 return (src >> shift) & mask;
855}
856
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000857void helper_extrq_r(CPUX86State *env, XMMReg *d, XMMReg *s)
Andre Przywarad9f4bb22009-09-19 00:30:48 +0200858{
859 d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), s->XMM_B(1), s->XMM_B(0));
860}
861
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000862void helper_extrq_i(CPUX86State *env, XMMReg *d, int index, int length)
Andre Przywarad9f4bb22009-09-19 00:30:48 +0200863{
864 d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), index, length);
865}
866
867static inline uint64_t helper_insertq(uint64_t src, int shift, int len)
868{
869 uint64_t mask;
870
871 if (len == 0) {
872 mask = ~0ULL;
873 } else {
874 mask = (1ULL << len) - 1;
875 }
876 return (src & ~(mask << shift)) | ((src & mask) << shift);
877}
878
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000879void helper_insertq_r(CPUX86State *env, XMMReg *d, XMMReg *s)
Andre Przywarad9f4bb22009-09-19 00:30:48 +0200880{
881 d->XMM_Q(0) = helper_insertq(s->XMM_Q(0), s->XMM_B(9), s->XMM_B(8));
882}
883
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000884void helper_insertq_i(CPUX86State *env, XMMReg *d, int index, int length)
Andre Przywarad9f4bb22009-09-19 00:30:48 +0200885{
886 d->XMM_Q(0) = helper_insertq(d->XMM_Q(0), index, length);
887}
888
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000889void helper_haddps(CPUX86State *env, XMMReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000890{
bellard664e0f12005-01-08 18:58:29 +0000891 XMMReg r;
Blue Swirle01d9d32012-04-29 08:54:44 +0000892
Max Reitz5c6562c2011-09-16 17:29:04 +0200893 r.XMM_S(0) = float32_add(d->XMM_S(0), d->XMM_S(1), &env->sse_status);
894 r.XMM_S(1) = float32_add(d->XMM_S(2), d->XMM_S(3), &env->sse_status);
895 r.XMM_S(2) = float32_add(s->XMM_S(0), s->XMM_S(1), &env->sse_status);
896 r.XMM_S(3) = float32_add(s->XMM_S(2), s->XMM_S(3), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000897 *d = r;
898}
899
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000900void helper_haddpd(CPUX86State *env, XMMReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000901{
bellard664e0f12005-01-08 18:58:29 +0000902 XMMReg r;
Blue Swirle01d9d32012-04-29 08:54:44 +0000903
Max Reitz5c6562c2011-09-16 17:29:04 +0200904 r.XMM_D(0) = float64_add(d->XMM_D(0), d->XMM_D(1), &env->sse_status);
905 r.XMM_D(1) = float64_add(s->XMM_D(0), s->XMM_D(1), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000906 *d = r;
907}
908
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000909void helper_hsubps(CPUX86State *env, XMMReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000910{
bellard664e0f12005-01-08 18:58:29 +0000911 XMMReg r;
Blue Swirle01d9d32012-04-29 08:54:44 +0000912
Max Reitz5c6562c2011-09-16 17:29:04 +0200913 r.XMM_S(0) = float32_sub(d->XMM_S(0), d->XMM_S(1), &env->sse_status);
914 r.XMM_S(1) = float32_sub(d->XMM_S(2), d->XMM_S(3), &env->sse_status);
915 r.XMM_S(2) = float32_sub(s->XMM_S(0), s->XMM_S(1), &env->sse_status);
916 r.XMM_S(3) = float32_sub(s->XMM_S(2), s->XMM_S(3), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000917 *d = r;
918}
919
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000920void helper_hsubpd(CPUX86State *env, XMMReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000921{
bellard664e0f12005-01-08 18:58:29 +0000922 XMMReg r;
Blue Swirle01d9d32012-04-29 08:54:44 +0000923
Max Reitz5c6562c2011-09-16 17:29:04 +0200924 r.XMM_D(0) = float64_sub(d->XMM_D(0), d->XMM_D(1), &env->sse_status);
925 r.XMM_D(1) = float64_sub(s->XMM_D(0), s->XMM_D(1), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000926 *d = r;
927}
928
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000929void helper_addsubps(CPUX86State *env, XMMReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000930{
Max Reitz5c6562c2011-09-16 17:29:04 +0200931 d->XMM_S(0) = float32_sub(d->XMM_S(0), s->XMM_S(0), &env->sse_status);
932 d->XMM_S(1) = float32_add(d->XMM_S(1), s->XMM_S(1), &env->sse_status);
933 d->XMM_S(2) = float32_sub(d->XMM_S(2), s->XMM_S(2), &env->sse_status);
934 d->XMM_S(3) = float32_add(d->XMM_S(3), s->XMM_S(3), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000935}
936
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000937void helper_addsubpd(CPUX86State *env, XMMReg *d, XMMReg *s)
bellard664e0f12005-01-08 18:58:29 +0000938{
Max Reitz5c6562c2011-09-16 17:29:04 +0200939 d->XMM_D(0) = float64_sub(d->XMM_D(0), s->XMM_D(0), &env->sse_status);
940 d->XMM_D(1) = float64_add(d->XMM_D(1), s->XMM_D(1), &env->sse_status);
bellard664e0f12005-01-08 18:58:29 +0000941}
942
943/* XXX: unordered */
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000944#define SSE_HELPER_CMP(name, F) \
945 void helper_ ## name ## ps(CPUX86State *env, Reg *d, Reg *s) \
946 { \
947 d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \
948 d->XMM_L(1) = F(32, d->XMM_S(1), s->XMM_S(1)); \
949 d->XMM_L(2) = F(32, d->XMM_S(2), s->XMM_S(2)); \
950 d->XMM_L(3) = F(32, d->XMM_S(3), s->XMM_S(3)); \
951 } \
952 \
953 void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *s) \
954 { \
955 d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \
956 } \
957 \
958 void helper_ ## name ## pd(CPUX86State *env, Reg *d, Reg *s) \
959 { \
960 d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \
961 d->XMM_Q(1) = F(64, d->XMM_D(1), s->XMM_D(1)); \
962 } \
963 \
964 void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *s) \
965 { \
966 d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \
Blue Swirle01d9d32012-04-29 08:54:44 +0000967 }
bellard664e0f12005-01-08 18:58:29 +0000968
Blue Swirle01d9d32012-04-29 08:54:44 +0000969#define FPU_CMPEQ(size, a, b) \
970 (float ## size ## _eq_quiet(a, b, &env->sse_status) ? -1 : 0)
971#define FPU_CMPLT(size, a, b) \
972 (float ## size ## _lt(a, b, &env->sse_status) ? -1 : 0)
973#define FPU_CMPLE(size, a, b) \
974 (float ## size ## _le(a, b, &env->sse_status) ? -1 : 0)
975#define FPU_CMPUNORD(size, a, b) \
976 (float ## size ## _unordered_quiet(a, b, &env->sse_status) ? -1 : 0)
977#define FPU_CMPNEQ(size, a, b) \
978 (float ## size ## _eq_quiet(a, b, &env->sse_status) ? 0 : -1)
979#define FPU_CMPNLT(size, a, b) \
980 (float ## size ## _lt(a, b, &env->sse_status) ? 0 : -1)
981#define FPU_CMPNLE(size, a, b) \
982 (float ## size ## _le(a, b, &env->sse_status) ? 0 : -1)
983#define FPU_CMPORD(size, a, b) \
984 (float ## size ## _unordered_quiet(a, b, &env->sse_status) ? 0 : -1)
bellard664e0f12005-01-08 18:58:29 +0000985
bellard5af45182008-05-12 16:47:36 +0000986SSE_HELPER_CMP(cmpeq, FPU_CMPEQ)
987SSE_HELPER_CMP(cmplt, FPU_CMPLT)
988SSE_HELPER_CMP(cmple, FPU_CMPLE)
989SSE_HELPER_CMP(cmpunord, FPU_CMPUNORD)
990SSE_HELPER_CMP(cmpneq, FPU_CMPNEQ)
991SSE_HELPER_CMP(cmpnlt, FPU_CMPNLT)
992SSE_HELPER_CMP(cmpnle, FPU_CMPNLE)
993SSE_HELPER_CMP(cmpord, FPU_CMPORD)
bellard664e0f12005-01-08 18:58:29 +0000994
Blue Swirl1e6eec82009-09-05 10:14:07 +0000995static const int comis_eflags[4] = {CC_C, CC_Z, 0, CC_Z | CC_P | CC_C};
bellard43fb8232005-04-26 20:38:17 +0000996
Blue Swirld3eb5ea2012-04-28 21:28:09 +0000997void helper_ucomiss(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +0000998{
bellard43fb8232005-04-26 20:38:17 +0000999 int ret;
bellard8422b112005-03-20 10:39:24 +00001000 float32 s0, s1;
bellard664e0f12005-01-08 18:58:29 +00001001
1002 s0 = d->XMM_S(0);
1003 s1 = s->XMM_S(0);
bellard43fb8232005-04-26 20:38:17 +00001004 ret = float32_compare_quiet(s0, s1, &env->sse_status);
1005 CC_SRC = comis_eflags[ret + 1];
bellard664e0f12005-01-08 18:58:29 +00001006}
1007
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001008void helper_comiss(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +00001009{
bellard43fb8232005-04-26 20:38:17 +00001010 int ret;
bellard8422b112005-03-20 10:39:24 +00001011 float32 s0, s1;
bellard664e0f12005-01-08 18:58:29 +00001012
1013 s0 = d->XMM_S(0);
1014 s1 = s->XMM_S(0);
bellard43fb8232005-04-26 20:38:17 +00001015 ret = float32_compare(s0, s1, &env->sse_status);
1016 CC_SRC = comis_eflags[ret + 1];
bellard664e0f12005-01-08 18:58:29 +00001017}
1018
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001019void helper_ucomisd(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +00001020{
bellard43fb8232005-04-26 20:38:17 +00001021 int ret;
bellard8422b112005-03-20 10:39:24 +00001022 float64 d0, d1;
bellard664e0f12005-01-08 18:58:29 +00001023
1024 d0 = d->XMM_D(0);
1025 d1 = s->XMM_D(0);
bellard43fb8232005-04-26 20:38:17 +00001026 ret = float64_compare_quiet(d0, d1, &env->sse_status);
1027 CC_SRC = comis_eflags[ret + 1];
bellard664e0f12005-01-08 18:58:29 +00001028}
1029
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001030void helper_comisd(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +00001031{
bellard43fb8232005-04-26 20:38:17 +00001032 int ret;
bellard8422b112005-03-20 10:39:24 +00001033 float64 d0, d1;
bellard664e0f12005-01-08 18:58:29 +00001034
1035 d0 = d->XMM_D(0);
1036 d1 = s->XMM_D(0);
bellard43fb8232005-04-26 20:38:17 +00001037 ret = float64_compare(d0, d1, &env->sse_status);
1038 CC_SRC = comis_eflags[ret + 1];
bellard664e0f12005-01-08 18:58:29 +00001039}
1040
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001041uint32_t helper_movmskps(CPUX86State *env, Reg *s)
bellard664e0f12005-01-08 18:58:29 +00001042{
1043 int b0, b1, b2, b3;
Blue Swirle01d9d32012-04-29 08:54:44 +00001044
bellard664e0f12005-01-08 18:58:29 +00001045 b0 = s->XMM_L(0) >> 31;
1046 b1 = s->XMM_L(1) >> 31;
1047 b2 = s->XMM_L(2) >> 31;
1048 b3 = s->XMM_L(3) >> 31;
bellard5af45182008-05-12 16:47:36 +00001049 return b0 | (b1 << 1) | (b2 << 2) | (b3 << 3);
bellard664e0f12005-01-08 18:58:29 +00001050}
1051
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001052uint32_t helper_movmskpd(CPUX86State *env, Reg *s)
bellard664e0f12005-01-08 18:58:29 +00001053{
1054 int b0, b1;
Blue Swirle01d9d32012-04-29 08:54:44 +00001055
bellard664e0f12005-01-08 18:58:29 +00001056 b0 = s->XMM_L(1) >> 31;
1057 b1 = s->XMM_L(3) >> 31;
bellard5af45182008-05-12 16:47:36 +00001058 return b0 | (b1 << 1);
bellard664e0f12005-01-08 18:58:29 +00001059}
1060
1061#endif
1062
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001063uint32_t glue(helper_pmovmskb, SUFFIX)(CPUX86State *env, Reg *s)
bellard664e0f12005-01-08 18:58:29 +00001064{
bellard5af45182008-05-12 16:47:36 +00001065 uint32_t val;
Blue Swirle01d9d32012-04-29 08:54:44 +00001066
bellard5af45182008-05-12 16:47:36 +00001067 val = 0;
aurel3230913ba2008-11-16 19:15:15 +00001068 val |= (s->B(0) >> 7);
1069 val |= (s->B(1) >> 6) & 0x02;
1070 val |= (s->B(2) >> 5) & 0x04;
1071 val |= (s->B(3) >> 4) & 0x08;
1072 val |= (s->B(4) >> 3) & 0x10;
1073 val |= (s->B(5) >> 2) & 0x20;
1074 val |= (s->B(6) >> 1) & 0x40;
1075 val |= (s->B(7)) & 0x80;
bellard664e0f12005-01-08 18:58:29 +00001076#if SHIFT == 1
aurel3230913ba2008-11-16 19:15:15 +00001077 val |= (s->B(8) << 1) & 0x0100;
1078 val |= (s->B(9) << 2) & 0x0200;
1079 val |= (s->B(10) << 3) & 0x0400;
1080 val |= (s->B(11) << 4) & 0x0800;
1081 val |= (s->B(12) << 5) & 0x1000;
1082 val |= (s->B(13) << 6) & 0x2000;
1083 val |= (s->B(14) << 7) & 0x4000;
1084 val |= (s->B(15) << 8) & 0x8000;
bellard664e0f12005-01-08 18:58:29 +00001085#endif
bellard5af45182008-05-12 16:47:36 +00001086 return val;
bellard664e0f12005-01-08 18:58:29 +00001087}
1088
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001089void glue(helper_packsswb, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +00001090{
bellard5af45182008-05-12 16:47:36 +00001091 Reg r;
bellard664e0f12005-01-08 18:58:29 +00001092
1093 r.B(0) = satsb((int16_t)d->W(0));
1094 r.B(1) = satsb((int16_t)d->W(1));
1095 r.B(2) = satsb((int16_t)d->W(2));
1096 r.B(3) = satsb((int16_t)d->W(3));
1097#if SHIFT == 1
1098 r.B(4) = satsb((int16_t)d->W(4));
1099 r.B(5) = satsb((int16_t)d->W(5));
1100 r.B(6) = satsb((int16_t)d->W(6));
1101 r.B(7) = satsb((int16_t)d->W(7));
1102#endif
1103 r.B((4 << SHIFT) + 0) = satsb((int16_t)s->W(0));
1104 r.B((4 << SHIFT) + 1) = satsb((int16_t)s->W(1));
1105 r.B((4 << SHIFT) + 2) = satsb((int16_t)s->W(2));
1106 r.B((4 << SHIFT) + 3) = satsb((int16_t)s->W(3));
1107#if SHIFT == 1
1108 r.B(12) = satsb((int16_t)s->W(4));
1109 r.B(13) = satsb((int16_t)s->W(5));
1110 r.B(14) = satsb((int16_t)s->W(6));
1111 r.B(15) = satsb((int16_t)s->W(7));
1112#endif
1113 *d = r;
1114}
1115
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001116void glue(helper_packuswb, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +00001117{
bellard5af45182008-05-12 16:47:36 +00001118 Reg r;
bellard664e0f12005-01-08 18:58:29 +00001119
1120 r.B(0) = satub((int16_t)d->W(0));
1121 r.B(1) = satub((int16_t)d->W(1));
1122 r.B(2) = satub((int16_t)d->W(2));
1123 r.B(3) = satub((int16_t)d->W(3));
1124#if SHIFT == 1
1125 r.B(4) = satub((int16_t)d->W(4));
1126 r.B(5) = satub((int16_t)d->W(5));
1127 r.B(6) = satub((int16_t)d->W(6));
1128 r.B(7) = satub((int16_t)d->W(7));
1129#endif
1130 r.B((4 << SHIFT) + 0) = satub((int16_t)s->W(0));
1131 r.B((4 << SHIFT) + 1) = satub((int16_t)s->W(1));
1132 r.B((4 << SHIFT) + 2) = satub((int16_t)s->W(2));
1133 r.B((4 << SHIFT) + 3) = satub((int16_t)s->W(3));
1134#if SHIFT == 1
1135 r.B(12) = satub((int16_t)s->W(4));
1136 r.B(13) = satub((int16_t)s->W(5));
1137 r.B(14) = satub((int16_t)s->W(6));
1138 r.B(15) = satub((int16_t)s->W(7));
1139#endif
1140 *d = r;
1141}
1142
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001143void glue(helper_packssdw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
bellard664e0f12005-01-08 18:58:29 +00001144{
bellard5af45182008-05-12 16:47:36 +00001145 Reg r;
bellard664e0f12005-01-08 18:58:29 +00001146
1147 r.W(0) = satsw(d->L(0));
1148 r.W(1) = satsw(d->L(1));
1149#if SHIFT == 1
1150 r.W(2) = satsw(d->L(2));
1151 r.W(3) = satsw(d->L(3));
1152#endif
1153 r.W((2 << SHIFT) + 0) = satsw(s->L(0));
1154 r.W((2 << SHIFT) + 1) = satsw(s->L(1));
1155#if SHIFT == 1
1156 r.W(6) = satsw(s->L(2));
1157 r.W(7) = satsw(s->L(3));
1158#endif
1159 *d = r;
1160}
1161
Blue Swirle01d9d32012-04-29 08:54:44 +00001162#define UNPCK_OP(base_name, base) \
1163 \
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001164 void glue(helper_punpck ## base_name ## bw, SUFFIX)(CPUX86State *env,\
1165 Reg *d, Reg *s) \
Blue Swirle01d9d32012-04-29 08:54:44 +00001166 { \
1167 Reg r; \
1168 \
1169 r.B(0) = d->B((base << (SHIFT + 2)) + 0); \
1170 r.B(1) = s->B((base << (SHIFT + 2)) + 0); \
1171 r.B(2) = d->B((base << (SHIFT + 2)) + 1); \
1172 r.B(3) = s->B((base << (SHIFT + 2)) + 1); \
1173 r.B(4) = d->B((base << (SHIFT + 2)) + 2); \
1174 r.B(5) = s->B((base << (SHIFT + 2)) + 2); \
1175 r.B(6) = d->B((base << (SHIFT + 2)) + 3); \
1176 r.B(7) = s->B((base << (SHIFT + 2)) + 3); \
1177 XMM_ONLY( \
1178 r.B(8) = d->B((base << (SHIFT + 2)) + 4); \
1179 r.B(9) = s->B((base << (SHIFT + 2)) + 4); \
1180 r.B(10) = d->B((base << (SHIFT + 2)) + 5); \
1181 r.B(11) = s->B((base << (SHIFT + 2)) + 5); \
1182 r.B(12) = d->B((base << (SHIFT + 2)) + 6); \
1183 r.B(13) = s->B((base << (SHIFT + 2)) + 6); \
1184 r.B(14) = d->B((base << (SHIFT + 2)) + 7); \
1185 r.B(15) = s->B((base << (SHIFT + 2)) + 7); \
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001186 ) \
Blue Swirle01d9d32012-04-29 08:54:44 +00001187 *d = r; \
1188 } \
1189 \
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001190 void glue(helper_punpck ## base_name ## wd, SUFFIX)(CPUX86State *env,\
1191 Reg *d, Reg *s) \
Blue Swirle01d9d32012-04-29 08:54:44 +00001192 { \
1193 Reg r; \
1194 \
1195 r.W(0) = d->W((base << (SHIFT + 1)) + 0); \
1196 r.W(1) = s->W((base << (SHIFT + 1)) + 0); \
1197 r.W(2) = d->W((base << (SHIFT + 1)) + 1); \
1198 r.W(3) = s->W((base << (SHIFT + 1)) + 1); \
1199 XMM_ONLY( \
1200 r.W(4) = d->W((base << (SHIFT + 1)) + 2); \
1201 r.W(5) = s->W((base << (SHIFT + 1)) + 2); \
1202 r.W(6) = d->W((base << (SHIFT + 1)) + 3); \
1203 r.W(7) = s->W((base << (SHIFT + 1)) + 3); \
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001204 ) \
Blue Swirle01d9d32012-04-29 08:54:44 +00001205 *d = r; \
1206 } \
1207 \
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001208 void glue(helper_punpck ## base_name ## dq, SUFFIX)(CPUX86State *env,\
1209 Reg *d, Reg *s) \
Blue Swirle01d9d32012-04-29 08:54:44 +00001210 { \
1211 Reg r; \
1212 \
1213 r.L(0) = d->L((base << SHIFT) + 0); \
1214 r.L(1) = s->L((base << SHIFT) + 0); \
1215 XMM_ONLY( \
1216 r.L(2) = d->L((base << SHIFT) + 1); \
1217 r.L(3) = s->L((base << SHIFT) + 1); \
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001218 ) \
Blue Swirle01d9d32012-04-29 08:54:44 +00001219 *d = r; \
1220 } \
1221 \
1222 XMM_ONLY( \
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001223 void glue(helper_punpck ## base_name ## qdq, SUFFIX)(CPUX86State \
1224 *env, \
1225 Reg *d, \
Blue Swirle01d9d32012-04-29 08:54:44 +00001226 Reg *s) \
1227 { \
1228 Reg r; \
1229 \
1230 r.Q(0) = d->Q(base); \
1231 r.Q(1) = s->Q(base); \
1232 *d = r; \
1233 } \
1234 )
bellard664e0f12005-01-08 18:58:29 +00001235
1236UNPCK_OP(l, 0)
1237UNPCK_OP(h, 1)
1238
aurel32a35f3ec2008-04-08 19:51:29 +00001239/* 3DNow! float ops */
1240#if SHIFT == 0
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001241void helper_pi2fd(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001242{
aurel32a35f3ec2008-04-08 19:51:29 +00001243 d->MMX_S(0) = int32_to_float32(s->MMX_L(0), &env->mmx_status);
1244 d->MMX_S(1) = int32_to_float32(s->MMX_L(1), &env->mmx_status);
1245}
1246
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001247void helper_pi2fw(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001248{
aurel32a35f3ec2008-04-08 19:51:29 +00001249 d->MMX_S(0) = int32_to_float32((int16_t)s->MMX_W(0), &env->mmx_status);
1250 d->MMX_S(1) = int32_to_float32((int16_t)s->MMX_W(2), &env->mmx_status);
1251}
1252
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001253void helper_pf2id(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001254{
aurel32a35f3ec2008-04-08 19:51:29 +00001255 d->MMX_L(0) = float32_to_int32_round_to_zero(s->MMX_S(0), &env->mmx_status);
1256 d->MMX_L(1) = float32_to_int32_round_to_zero(s->MMX_S(1), &env->mmx_status);
1257}
1258
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001259void helper_pf2iw(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001260{
Blue Swirle01d9d32012-04-29 08:54:44 +00001261 d->MMX_L(0) = satsw(float32_to_int32_round_to_zero(s->MMX_S(0),
1262 &env->mmx_status));
1263 d->MMX_L(1) = satsw(float32_to_int32_round_to_zero(s->MMX_S(1),
1264 &env->mmx_status));
aurel32a35f3ec2008-04-08 19:51:29 +00001265}
1266
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001267void helper_pfacc(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001268{
aurel32a35f3ec2008-04-08 19:51:29 +00001269 MMXReg r;
Blue Swirle01d9d32012-04-29 08:54:44 +00001270
aurel32a35f3ec2008-04-08 19:51:29 +00001271 r.MMX_S(0) = float32_add(d->MMX_S(0), d->MMX_S(1), &env->mmx_status);
1272 r.MMX_S(1) = float32_add(s->MMX_S(0), s->MMX_S(1), &env->mmx_status);
1273 *d = r;
1274}
1275
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001276void helper_pfadd(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001277{
aurel32a35f3ec2008-04-08 19:51:29 +00001278 d->MMX_S(0) = float32_add(d->MMX_S(0), s->MMX_S(0), &env->mmx_status);
1279 d->MMX_S(1) = float32_add(d->MMX_S(1), s->MMX_S(1), &env->mmx_status);
1280}
1281
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001282void helper_pfcmpeq(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001283{
Blue Swirle01d9d32012-04-29 08:54:44 +00001284 d->MMX_L(0) = float32_eq_quiet(d->MMX_S(0), s->MMX_S(0),
1285 &env->mmx_status) ? -1 : 0;
1286 d->MMX_L(1) = float32_eq_quiet(d->MMX_S(1), s->MMX_S(1),
1287 &env->mmx_status) ? -1 : 0;
aurel32a35f3ec2008-04-08 19:51:29 +00001288}
1289
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001290void helper_pfcmpge(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001291{
Blue Swirle01d9d32012-04-29 08:54:44 +00001292 d->MMX_L(0) = float32_le(s->MMX_S(0), d->MMX_S(0),
1293 &env->mmx_status) ? -1 : 0;
1294 d->MMX_L(1) = float32_le(s->MMX_S(1), d->MMX_S(1),
1295 &env->mmx_status) ? -1 : 0;
aurel32a35f3ec2008-04-08 19:51:29 +00001296}
1297
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001298void helper_pfcmpgt(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001299{
Blue Swirle01d9d32012-04-29 08:54:44 +00001300 d->MMX_L(0) = float32_lt(s->MMX_S(0), d->MMX_S(0),
1301 &env->mmx_status) ? -1 : 0;
1302 d->MMX_L(1) = float32_lt(s->MMX_S(1), d->MMX_S(1),
1303 &env->mmx_status) ? -1 : 0;
aurel32a35f3ec2008-04-08 19:51:29 +00001304}
1305
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001306void helper_pfmax(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001307{
Blue Swirle01d9d32012-04-29 08:54:44 +00001308 if (float32_lt(d->MMX_S(0), s->MMX_S(0), &env->mmx_status)) {
aurel32a35f3ec2008-04-08 19:51:29 +00001309 d->MMX_S(0) = s->MMX_S(0);
Blue Swirle01d9d32012-04-29 08:54:44 +00001310 }
1311 if (float32_lt(d->MMX_S(1), s->MMX_S(1), &env->mmx_status)) {
aurel32a35f3ec2008-04-08 19:51:29 +00001312 d->MMX_S(1) = s->MMX_S(1);
Blue Swirle01d9d32012-04-29 08:54:44 +00001313 }
aurel32a35f3ec2008-04-08 19:51:29 +00001314}
1315
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001316void helper_pfmin(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001317{
Blue Swirle01d9d32012-04-29 08:54:44 +00001318 if (float32_lt(s->MMX_S(0), d->MMX_S(0), &env->mmx_status)) {
aurel32a35f3ec2008-04-08 19:51:29 +00001319 d->MMX_S(0) = s->MMX_S(0);
Blue Swirle01d9d32012-04-29 08:54:44 +00001320 }
1321 if (float32_lt(s->MMX_S(1), d->MMX_S(1), &env->mmx_status)) {
aurel32a35f3ec2008-04-08 19:51:29 +00001322 d->MMX_S(1) = s->MMX_S(1);
Blue Swirle01d9d32012-04-29 08:54:44 +00001323 }
aurel32a35f3ec2008-04-08 19:51:29 +00001324}
1325
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001326void helper_pfmul(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001327{
aurel32a35f3ec2008-04-08 19:51:29 +00001328 d->MMX_S(0) = float32_mul(d->MMX_S(0), s->MMX_S(0), &env->mmx_status);
1329 d->MMX_S(1) = float32_mul(d->MMX_S(1), s->MMX_S(1), &env->mmx_status);
1330}
1331
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001332void helper_pfnacc(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001333{
aurel32a35f3ec2008-04-08 19:51:29 +00001334 MMXReg r;
Blue Swirle01d9d32012-04-29 08:54:44 +00001335
aurel32a35f3ec2008-04-08 19:51:29 +00001336 r.MMX_S(0) = float32_sub(d->MMX_S(0), d->MMX_S(1), &env->mmx_status);
1337 r.MMX_S(1) = float32_sub(s->MMX_S(0), s->MMX_S(1), &env->mmx_status);
1338 *d = r;
1339}
1340
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001341void helper_pfpnacc(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001342{
aurel32a35f3ec2008-04-08 19:51:29 +00001343 MMXReg r;
Blue Swirle01d9d32012-04-29 08:54:44 +00001344
aurel32a35f3ec2008-04-08 19:51:29 +00001345 r.MMX_S(0) = float32_sub(d->MMX_S(0), d->MMX_S(1), &env->mmx_status);
1346 r.MMX_S(1) = float32_add(s->MMX_S(0), s->MMX_S(1), &env->mmx_status);
1347 *d = r;
1348}
1349
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001350void helper_pfrcp(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001351{
Aurelien Jarnoc2ef9a82011-04-20 13:04:23 +02001352 d->MMX_S(0) = float32_div(float32_one, s->MMX_S(0), &env->mmx_status);
aurel32a35f3ec2008-04-08 19:51:29 +00001353 d->MMX_S(1) = d->MMX_S(0);
1354}
1355
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001356void helper_pfrsqrt(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001357{
aurel32a35f3ec2008-04-08 19:51:29 +00001358 d->MMX_L(1) = s->MMX_L(0) & 0x7fffffff;
Aurelien Jarnoc2ef9a82011-04-20 13:04:23 +02001359 d->MMX_S(1) = float32_div(float32_one,
1360 float32_sqrt(d->MMX_S(1), &env->mmx_status),
1361 &env->mmx_status);
aurel32a35f3ec2008-04-08 19:51:29 +00001362 d->MMX_L(1) |= s->MMX_L(0) & 0x80000000;
1363 d->MMX_L(0) = d->MMX_L(1);
1364}
1365
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001366void helper_pfsub(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001367{
aurel32a35f3ec2008-04-08 19:51:29 +00001368 d->MMX_S(0) = float32_sub(d->MMX_S(0), s->MMX_S(0), &env->mmx_status);
1369 d->MMX_S(1) = float32_sub(d->MMX_S(1), s->MMX_S(1), &env->mmx_status);
1370}
1371
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001372void helper_pfsubr(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001373{
aurel32a35f3ec2008-04-08 19:51:29 +00001374 d->MMX_S(0) = float32_sub(s->MMX_S(0), d->MMX_S(0), &env->mmx_status);
1375 d->MMX_S(1) = float32_sub(s->MMX_S(1), d->MMX_S(1), &env->mmx_status);
1376}
1377
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001378void helper_pswapd(CPUX86State *env, MMXReg *d, MMXReg *s)
aurel32a35f3ec2008-04-08 19:51:29 +00001379{
aurel32a35f3ec2008-04-08 19:51:29 +00001380 MMXReg r;
Blue Swirle01d9d32012-04-29 08:54:44 +00001381
aurel32a35f3ec2008-04-08 19:51:29 +00001382 r.MMX_L(0) = s->MMX_L(1);
1383 r.MMX_L(1) = s->MMX_L(0);
1384 *d = r;
1385}
1386#endif
1387
balrog4242b1b2008-09-25 18:01:46 +00001388/* SSSE3 op helpers */
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001389void glue(helper_pshufb, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
balrog4242b1b2008-09-25 18:01:46 +00001390{
1391 int i;
1392 Reg r;
1393
Blue Swirle01d9d32012-04-29 08:54:44 +00001394 for (i = 0; i < (8 << SHIFT); i++) {
balrog4242b1b2008-09-25 18:01:46 +00001395 r.B(i) = (s->B(i) & 0x80) ? 0 : (d->B(s->B(i) & ((8 << SHIFT) - 1)));
Blue Swirle01d9d32012-04-29 08:54:44 +00001396 }
balrog4242b1b2008-09-25 18:01:46 +00001397
1398 *d = r;
1399}
1400
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001401void glue(helper_phaddw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
balrog4242b1b2008-09-25 18:01:46 +00001402{
1403 d->W(0) = (int16_t)d->W(0) + (int16_t)d->W(1);
1404 d->W(1) = (int16_t)d->W(2) + (int16_t)d->W(3);
1405 XMM_ONLY(d->W(2) = (int16_t)d->W(4) + (int16_t)d->W(5));
1406 XMM_ONLY(d->W(3) = (int16_t)d->W(6) + (int16_t)d->W(7));
1407 d->W((2 << SHIFT) + 0) = (int16_t)s->W(0) + (int16_t)s->W(1);
1408 d->W((2 << SHIFT) + 1) = (int16_t)s->W(2) + (int16_t)s->W(3);
1409 XMM_ONLY(d->W(6) = (int16_t)s->W(4) + (int16_t)s->W(5));
1410 XMM_ONLY(d->W(7) = (int16_t)s->W(6) + (int16_t)s->W(7));
1411}
1412
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001413void glue(helper_phaddd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
balrog4242b1b2008-09-25 18:01:46 +00001414{
1415 d->L(0) = (int32_t)d->L(0) + (int32_t)d->L(1);
1416 XMM_ONLY(d->L(1) = (int32_t)d->L(2) + (int32_t)d->L(3));
1417 d->L((1 << SHIFT) + 0) = (int32_t)s->L(0) + (int32_t)s->L(1);
1418 XMM_ONLY(d->L(3) = (int32_t)s->L(2) + (int32_t)s->L(3));
1419}
1420
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001421void glue(helper_phaddsw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
balrog4242b1b2008-09-25 18:01:46 +00001422{
1423 d->W(0) = satsw((int16_t)d->W(0) + (int16_t)d->W(1));
1424 d->W(1) = satsw((int16_t)d->W(2) + (int16_t)d->W(3));
1425 XMM_ONLY(d->W(2) = satsw((int16_t)d->W(4) + (int16_t)d->W(5)));
1426 XMM_ONLY(d->W(3) = satsw((int16_t)d->W(6) + (int16_t)d->W(7)));
1427 d->W((2 << SHIFT) + 0) = satsw((int16_t)s->W(0) + (int16_t)s->W(1));
1428 d->W((2 << SHIFT) + 1) = satsw((int16_t)s->W(2) + (int16_t)s->W(3));
1429 XMM_ONLY(d->W(6) = satsw((int16_t)s->W(4) + (int16_t)s->W(5)));
1430 XMM_ONLY(d->W(7) = satsw((int16_t)s->W(6) + (int16_t)s->W(7)));
1431}
1432
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001433void glue(helper_pmaddubsw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
balrog4242b1b2008-09-25 18:01:46 +00001434{
Blue Swirle01d9d32012-04-29 08:54:44 +00001435 d->W(0) = satsw((int8_t)s->B(0) * (uint8_t)d->B(0) +
1436 (int8_t)s->B(1) * (uint8_t)d->B(1));
1437 d->W(1) = satsw((int8_t)s->B(2) * (uint8_t)d->B(2) +
1438 (int8_t)s->B(3) * (uint8_t)d->B(3));
1439 d->W(2) = satsw((int8_t)s->B(4) * (uint8_t)d->B(4) +
1440 (int8_t)s->B(5) * (uint8_t)d->B(5));
1441 d->W(3) = satsw((int8_t)s->B(6) * (uint8_t)d->B(6) +
1442 (int8_t)s->B(7) * (uint8_t)d->B(7));
balrog4242b1b2008-09-25 18:01:46 +00001443#if SHIFT == 1
Blue Swirle01d9d32012-04-29 08:54:44 +00001444 d->W(4) = satsw((int8_t)s->B(8) * (uint8_t)d->B(8) +
1445 (int8_t)s->B(9) * (uint8_t)d->B(9));
balrog4242b1b2008-09-25 18:01:46 +00001446 d->W(5) = satsw((int8_t)s->B(10) * (uint8_t)d->B(10) +
1447 (int8_t)s->B(11) * (uint8_t)d->B(11));
1448 d->W(6) = satsw((int8_t)s->B(12) * (uint8_t)d->B(12) +
1449 (int8_t)s->B(13) * (uint8_t)d->B(13));
1450 d->W(7) = satsw((int8_t)s->B(14) * (uint8_t)d->B(14) +
1451 (int8_t)s->B(15) * (uint8_t)d->B(15));
1452#endif
1453}
1454
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001455void glue(helper_phsubw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
balrog4242b1b2008-09-25 18:01:46 +00001456{
1457 d->W(0) = (int16_t)d->W(0) - (int16_t)d->W(1);
1458 d->W(1) = (int16_t)d->W(2) - (int16_t)d->W(3);
1459 XMM_ONLY(d->W(2) = (int16_t)d->W(4) - (int16_t)d->W(5));
1460 XMM_ONLY(d->W(3) = (int16_t)d->W(6) - (int16_t)d->W(7));
1461 d->W((2 << SHIFT) + 0) = (int16_t)s->W(0) - (int16_t)s->W(1);
1462 d->W((2 << SHIFT) + 1) = (int16_t)s->W(2) - (int16_t)s->W(3);
1463 XMM_ONLY(d->W(6) = (int16_t)s->W(4) - (int16_t)s->W(5));
1464 XMM_ONLY(d->W(7) = (int16_t)s->W(6) - (int16_t)s->W(7));
1465}
1466
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001467void glue(helper_phsubd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
balrog4242b1b2008-09-25 18:01:46 +00001468{
1469 d->L(0) = (int32_t)d->L(0) - (int32_t)d->L(1);
1470 XMM_ONLY(d->L(1) = (int32_t)d->L(2) - (int32_t)d->L(3));
1471 d->L((1 << SHIFT) + 0) = (int32_t)s->L(0) - (int32_t)s->L(1);
1472 XMM_ONLY(d->L(3) = (int32_t)s->L(2) - (int32_t)s->L(3));
1473}
1474
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001475void glue(helper_phsubsw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
balrog4242b1b2008-09-25 18:01:46 +00001476{
1477 d->W(0) = satsw((int16_t)d->W(0) - (int16_t)d->W(1));
1478 d->W(1) = satsw((int16_t)d->W(2) - (int16_t)d->W(3));
1479 XMM_ONLY(d->W(2) = satsw((int16_t)d->W(4) - (int16_t)d->W(5)));
1480 XMM_ONLY(d->W(3) = satsw((int16_t)d->W(6) - (int16_t)d->W(7)));
1481 d->W((2 << SHIFT) + 0) = satsw((int16_t)s->W(0) - (int16_t)s->W(1));
1482 d->W((2 << SHIFT) + 1) = satsw((int16_t)s->W(2) - (int16_t)s->W(3));
1483 XMM_ONLY(d->W(6) = satsw((int16_t)s->W(4) - (int16_t)s->W(5)));
1484 XMM_ONLY(d->W(7) = satsw((int16_t)s->W(6) - (int16_t)s->W(7)));
1485}
1486
Blue Swirle01d9d32012-04-29 08:54:44 +00001487#define FABSB(_, x) (x > INT8_MAX ? -(int8_t)x : x)
1488#define FABSW(_, x) (x > INT16_MAX ? -(int16_t)x : x)
1489#define FABSL(_, x) (x > INT32_MAX ? -(int32_t)x : x)
balrog4242b1b2008-09-25 18:01:46 +00001490SSE_HELPER_B(helper_pabsb, FABSB)
1491SSE_HELPER_W(helper_pabsw, FABSW)
1492SSE_HELPER_L(helper_pabsd, FABSL)
1493
Blue Swirle01d9d32012-04-29 08:54:44 +00001494#define FMULHRSW(d, s) (((int16_t) d * (int16_t)s + 0x4000) >> 15)
balrog4242b1b2008-09-25 18:01:46 +00001495SSE_HELPER_W(helper_pmulhrsw, FMULHRSW)
1496
Blue Swirle01d9d32012-04-29 08:54:44 +00001497#define FSIGNB(d, s) (s <= INT8_MAX ? s ? d : 0 : -(int8_t)d)
1498#define FSIGNW(d, s) (s <= INT16_MAX ? s ? d : 0 : -(int16_t)d)
1499#define FSIGNL(d, s) (s <= INT32_MAX ? s ? d : 0 : -(int32_t)d)
balrog4242b1b2008-09-25 18:01:46 +00001500SSE_HELPER_B(helper_psignb, FSIGNB)
1501SSE_HELPER_W(helper_psignw, FSIGNW)
1502SSE_HELPER_L(helper_psignd, FSIGNL)
1503
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001504void glue(helper_palignr, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
1505 int32_t shift)
balrog4242b1b2008-09-25 18:01:46 +00001506{
1507 Reg r;
1508
1509 /* XXX could be checked during translation */
1510 if (shift >= (16 << SHIFT)) {
1511 r.Q(0) = 0;
1512 XMM_ONLY(r.Q(1) = 0);
1513 } else {
1514 shift <<= 3;
1515#define SHR(v, i) (i < 64 && i > -64 ? i > 0 ? v >> (i) : (v << -(i)) : 0)
1516#if SHIFT == 0
Blue Swirle01d9d32012-04-29 08:54:44 +00001517 r.Q(0) = SHR(s->Q(0), shift - 0) |
1518 SHR(d->Q(0), shift - 64);
balrog4242b1b2008-09-25 18:01:46 +00001519#else
Blue Swirle01d9d32012-04-29 08:54:44 +00001520 r.Q(0) = SHR(s->Q(0), shift - 0) |
1521 SHR(s->Q(1), shift - 64) |
1522 SHR(d->Q(0), shift - 128) |
1523 SHR(d->Q(1), shift - 192);
1524 r.Q(1) = SHR(s->Q(0), shift + 64) |
1525 SHR(s->Q(1), shift - 0) |
1526 SHR(d->Q(0), shift - 64) |
1527 SHR(d->Q(1), shift - 128);
balrog4242b1b2008-09-25 18:01:46 +00001528#endif
1529#undef SHR
1530 }
1531
1532 *d = r;
1533}
1534
Blue Swirle01d9d32012-04-29 08:54:44 +00001535#define XMM0 (env->xmm_regs[0])
balrog222a3332008-10-04 03:27:44 +00001536
1537#if SHIFT == 1
Blue Swirle01d9d32012-04-29 08:54:44 +00001538#define SSE_HELPER_V(name, elem, num, F) \
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001539 void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
Blue Swirle01d9d32012-04-29 08:54:44 +00001540 { \
1541 d->elem(0) = F(d->elem(0), s->elem(0), XMM0.elem(0)); \
1542 d->elem(1) = F(d->elem(1), s->elem(1), XMM0.elem(1)); \
1543 if (num > 2) { \
1544 d->elem(2) = F(d->elem(2), s->elem(2), XMM0.elem(2)); \
1545 d->elem(3) = F(d->elem(3), s->elem(3), XMM0.elem(3)); \
1546 if (num > 4) { \
1547 d->elem(4) = F(d->elem(4), s->elem(4), XMM0.elem(4)); \
1548 d->elem(5) = F(d->elem(5), s->elem(5), XMM0.elem(5)); \
1549 d->elem(6) = F(d->elem(6), s->elem(6), XMM0.elem(6)); \
1550 d->elem(7) = F(d->elem(7), s->elem(7), XMM0.elem(7)); \
1551 if (num > 8) { \
1552 d->elem(8) = F(d->elem(8), s->elem(8), XMM0.elem(8)); \
1553 d->elem(9) = F(d->elem(9), s->elem(9), XMM0.elem(9)); \
1554 d->elem(10) = F(d->elem(10), s->elem(10), XMM0.elem(10)); \
1555 d->elem(11) = F(d->elem(11), s->elem(11), XMM0.elem(11)); \
1556 d->elem(12) = F(d->elem(12), s->elem(12), XMM0.elem(12)); \
1557 d->elem(13) = F(d->elem(13), s->elem(13), XMM0.elem(13)); \
1558 d->elem(14) = F(d->elem(14), s->elem(14), XMM0.elem(14)); \
1559 d->elem(15) = F(d->elem(15), s->elem(15), XMM0.elem(15)); \
1560 } \
1561 } \
1562 } \
1563 }
balrog222a3332008-10-04 03:27:44 +00001564
Blue Swirle01d9d32012-04-29 08:54:44 +00001565#define SSE_HELPER_I(name, elem, num, F) \
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001566 void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t imm) \
Blue Swirle01d9d32012-04-29 08:54:44 +00001567 { \
1568 d->elem(0) = F(d->elem(0), s->elem(0), ((imm >> 0) & 1)); \
1569 d->elem(1) = F(d->elem(1), s->elem(1), ((imm >> 1) & 1)); \
1570 if (num > 2) { \
1571 d->elem(2) = F(d->elem(2), s->elem(2), ((imm >> 2) & 1)); \
1572 d->elem(3) = F(d->elem(3), s->elem(3), ((imm >> 3) & 1)); \
1573 if (num > 4) { \
1574 d->elem(4) = F(d->elem(4), s->elem(4), ((imm >> 4) & 1)); \
1575 d->elem(5) = F(d->elem(5), s->elem(5), ((imm >> 5) & 1)); \
1576 d->elem(6) = F(d->elem(6), s->elem(6), ((imm >> 6) & 1)); \
1577 d->elem(7) = F(d->elem(7), s->elem(7), ((imm >> 7) & 1)); \
1578 if (num > 8) { \
1579 d->elem(8) = F(d->elem(8), s->elem(8), ((imm >> 8) & 1)); \
1580 d->elem(9) = F(d->elem(9), s->elem(9), ((imm >> 9) & 1)); \
1581 d->elem(10) = F(d->elem(10), s->elem(10), \
1582 ((imm >> 10) & 1)); \
1583 d->elem(11) = F(d->elem(11), s->elem(11), \
1584 ((imm >> 11) & 1)); \
1585 d->elem(12) = F(d->elem(12), s->elem(12), \
1586 ((imm >> 12) & 1)); \
1587 d->elem(13) = F(d->elem(13), s->elem(13), \
1588 ((imm >> 13) & 1)); \
1589 d->elem(14) = F(d->elem(14), s->elem(14), \
1590 ((imm >> 14) & 1)); \
1591 d->elem(15) = F(d->elem(15), s->elem(15), \
1592 ((imm >> 15) & 1)); \
1593 } \
1594 } \
1595 } \
1596 }
balrog222a3332008-10-04 03:27:44 +00001597
1598/* SSE4.1 op helpers */
Blue Swirle01d9d32012-04-29 08:54:44 +00001599#define FBLENDVB(d, s, m) ((m & 0x80) ? s : d)
1600#define FBLENDVPS(d, s, m) ((m & 0x80000000) ? s : d)
1601#define FBLENDVPD(d, s, m) ((m & 0x8000000000000000LL) ? s : d)
balrog222a3332008-10-04 03:27:44 +00001602SSE_HELPER_V(helper_pblendvb, B, 16, FBLENDVB)
1603SSE_HELPER_V(helper_blendvps, L, 4, FBLENDVPS)
1604SSE_HELPER_V(helper_blendvpd, Q, 2, FBLENDVPD)
1605
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001606void glue(helper_ptest, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
balrog222a3332008-10-04 03:27:44 +00001607{
1608 uint64_t zf = (s->Q(0) & d->Q(0)) | (s->Q(1) & d->Q(1));
1609 uint64_t cf = (s->Q(0) & ~d->Q(0)) | (s->Q(1) & ~d->Q(1));
1610
1611 CC_SRC = (zf ? 0 : CC_Z) | (cf ? 0 : CC_C);
1612}
1613
Blue Swirle01d9d32012-04-29 08:54:44 +00001614#define SSE_HELPER_F(name, elem, num, F) \
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001615 void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \
Blue Swirle01d9d32012-04-29 08:54:44 +00001616 { \
1617 d->elem(0) = F(0); \
1618 d->elem(1) = F(1); \
1619 if (num > 2) { \
1620 d->elem(2) = F(2); \
1621 d->elem(3) = F(3); \
1622 if (num > 4) { \
1623 d->elem(4) = F(4); \
1624 d->elem(5) = F(5); \
1625 d->elem(6) = F(6); \
1626 d->elem(7) = F(7); \
1627 } \
1628 } \
1629 }
balrog222a3332008-10-04 03:27:44 +00001630
1631SSE_HELPER_F(helper_pmovsxbw, W, 8, (int8_t) s->B)
1632SSE_HELPER_F(helper_pmovsxbd, L, 4, (int8_t) s->B)
1633SSE_HELPER_F(helper_pmovsxbq, Q, 2, (int8_t) s->B)
1634SSE_HELPER_F(helper_pmovsxwd, L, 4, (int16_t) s->W)
1635SSE_HELPER_F(helper_pmovsxwq, Q, 2, (int16_t) s->W)
1636SSE_HELPER_F(helper_pmovsxdq, Q, 2, (int32_t) s->L)
1637SSE_HELPER_F(helper_pmovzxbw, W, 8, s->B)
1638SSE_HELPER_F(helper_pmovzxbd, L, 4, s->B)
1639SSE_HELPER_F(helper_pmovzxbq, Q, 2, s->B)
1640SSE_HELPER_F(helper_pmovzxwd, L, 4, s->W)
1641SSE_HELPER_F(helper_pmovzxwq, Q, 2, s->W)
1642SSE_HELPER_F(helper_pmovzxdq, Q, 2, s->L)
1643
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001644void glue(helper_pmuldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
balrog222a3332008-10-04 03:27:44 +00001645{
Blue Swirle01d9d32012-04-29 08:54:44 +00001646 d->Q(0) = (int64_t)(int32_t) d->L(0) * (int32_t) s->L(0);
1647 d->Q(1) = (int64_t)(int32_t) d->L(2) * (int32_t) s->L(2);
balrog222a3332008-10-04 03:27:44 +00001648}
1649
Blue Swirle01d9d32012-04-29 08:54:44 +00001650#define FCMPEQQ(d, s) (d == s ? -1 : 0)
balrog222a3332008-10-04 03:27:44 +00001651SSE_HELPER_Q(helper_pcmpeqq, FCMPEQQ)
1652
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001653void glue(helper_packusdw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
balrog222a3332008-10-04 03:27:44 +00001654{
1655 d->W(0) = satuw((int32_t) d->L(0));
1656 d->W(1) = satuw((int32_t) d->L(1));
1657 d->W(2) = satuw((int32_t) d->L(2));
1658 d->W(3) = satuw((int32_t) d->L(3));
1659 d->W(4) = satuw((int32_t) s->L(0));
1660 d->W(5) = satuw((int32_t) s->L(1));
1661 d->W(6) = satuw((int32_t) s->L(2));
1662 d->W(7) = satuw((int32_t) s->L(3));
1663}
1664
Blue Swirle01d9d32012-04-29 08:54:44 +00001665#define FMINSB(d, s) MIN((int8_t)d, (int8_t)s)
1666#define FMINSD(d, s) MIN((int32_t)d, (int32_t)s)
1667#define FMAXSB(d, s) MAX((int8_t)d, (int8_t)s)
1668#define FMAXSD(d, s) MAX((int32_t)d, (int32_t)s)
balrog222a3332008-10-04 03:27:44 +00001669SSE_HELPER_B(helper_pminsb, FMINSB)
1670SSE_HELPER_L(helper_pminsd, FMINSD)
1671SSE_HELPER_W(helper_pminuw, MIN)
1672SSE_HELPER_L(helper_pminud, MIN)
1673SSE_HELPER_B(helper_pmaxsb, FMAXSB)
1674SSE_HELPER_L(helper_pmaxsd, FMAXSD)
1675SSE_HELPER_W(helper_pmaxuw, MAX)
1676SSE_HELPER_L(helper_pmaxud, MAX)
1677
Blue Swirle01d9d32012-04-29 08:54:44 +00001678#define FMULLD(d, s) ((int32_t)d * (int32_t)s)
balrog222a3332008-10-04 03:27:44 +00001679SSE_HELPER_L(helper_pmulld, FMULLD)
1680
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001681void glue(helper_phminposuw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s)
balrog222a3332008-10-04 03:27:44 +00001682{
1683 int idx = 0;
1684
Blue Swirle01d9d32012-04-29 08:54:44 +00001685 if (s->W(1) < s->W(idx)) {
balrog222a3332008-10-04 03:27:44 +00001686 idx = 1;
Blue Swirle01d9d32012-04-29 08:54:44 +00001687 }
1688 if (s->W(2) < s->W(idx)) {
balrog222a3332008-10-04 03:27:44 +00001689 idx = 2;
Blue Swirle01d9d32012-04-29 08:54:44 +00001690 }
1691 if (s->W(3) < s->W(idx)) {
balrog222a3332008-10-04 03:27:44 +00001692 idx = 3;
Blue Swirle01d9d32012-04-29 08:54:44 +00001693 }
1694 if (s->W(4) < s->W(idx)) {
balrog222a3332008-10-04 03:27:44 +00001695 idx = 4;
Blue Swirle01d9d32012-04-29 08:54:44 +00001696 }
1697 if (s->W(5) < s->W(idx)) {
balrog222a3332008-10-04 03:27:44 +00001698 idx = 5;
Blue Swirle01d9d32012-04-29 08:54:44 +00001699 }
1700 if (s->W(6) < s->W(idx)) {
balrog222a3332008-10-04 03:27:44 +00001701 idx = 6;
Blue Swirle01d9d32012-04-29 08:54:44 +00001702 }
1703 if (s->W(7) < s->W(idx)) {
balrog222a3332008-10-04 03:27:44 +00001704 idx = 7;
Blue Swirle01d9d32012-04-29 08:54:44 +00001705 }
balrog222a3332008-10-04 03:27:44 +00001706
1707 d->Q(1) = 0;
1708 d->L(1) = 0;
1709 d->W(1) = idx;
1710 d->W(0) = s->W(idx);
1711}
1712
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001713void glue(helper_roundps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
1714 uint32_t mode)
balrog222a3332008-10-04 03:27:44 +00001715{
1716 signed char prev_rounding_mode;
1717
1718 prev_rounding_mode = env->sse_status.float_rounding_mode;
Blue Swirle01d9d32012-04-29 08:54:44 +00001719 if (!(mode & (1 << 2))) {
balrog222a3332008-10-04 03:27:44 +00001720 switch (mode & 3) {
1721 case 0:
1722 set_float_rounding_mode(float_round_nearest_even, &env->sse_status);
1723 break;
1724 case 1:
1725 set_float_rounding_mode(float_round_down, &env->sse_status);
1726 break;
1727 case 2:
1728 set_float_rounding_mode(float_round_up, &env->sse_status);
1729 break;
1730 case 3:
1731 set_float_rounding_mode(float_round_to_zero, &env->sse_status);
1732 break;
1733 }
Blue Swirle01d9d32012-04-29 08:54:44 +00001734 }
balrog222a3332008-10-04 03:27:44 +00001735
Aurelien Jarnoadc71662012-01-07 15:20:11 +01001736 d->XMM_S(0) = float32_round_to_int(s->XMM_S(0), &env->sse_status);
1737 d->XMM_S(1) = float32_round_to_int(s->XMM_S(1), &env->sse_status);
1738 d->XMM_S(2) = float32_round_to_int(s->XMM_S(2), &env->sse_status);
1739 d->XMM_S(3) = float32_round_to_int(s->XMM_S(3), &env->sse_status);
balrog222a3332008-10-04 03:27:44 +00001740
1741#if 0 /* TODO */
Blue Swirle01d9d32012-04-29 08:54:44 +00001742 if (mode & (1 << 3)) {
1743 set_float_exception_flags(get_float_exception_flags(&env->sse_status) &
1744 ~float_flag_inexact,
1745 &env->sse_status);
1746 }
balrog222a3332008-10-04 03:27:44 +00001747#endif
1748 env->sse_status.float_rounding_mode = prev_rounding_mode;
1749}
1750
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001751void glue(helper_roundpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
1752 uint32_t mode)
balrog222a3332008-10-04 03:27:44 +00001753{
1754 signed char prev_rounding_mode;
1755
1756 prev_rounding_mode = env->sse_status.float_rounding_mode;
Blue Swirle01d9d32012-04-29 08:54:44 +00001757 if (!(mode & (1 << 2))) {
balrog222a3332008-10-04 03:27:44 +00001758 switch (mode & 3) {
1759 case 0:
1760 set_float_rounding_mode(float_round_nearest_even, &env->sse_status);
1761 break;
1762 case 1:
1763 set_float_rounding_mode(float_round_down, &env->sse_status);
1764 break;
1765 case 2:
1766 set_float_rounding_mode(float_round_up, &env->sse_status);
1767 break;
1768 case 3:
1769 set_float_rounding_mode(float_round_to_zero, &env->sse_status);
1770 break;
1771 }
Blue Swirle01d9d32012-04-29 08:54:44 +00001772 }
balrog222a3332008-10-04 03:27:44 +00001773
Aurelien Jarnoadc71662012-01-07 15:20:11 +01001774 d->XMM_D(0) = float64_round_to_int(s->XMM_D(0), &env->sse_status);
1775 d->XMM_D(1) = float64_round_to_int(s->XMM_D(1), &env->sse_status);
balrog222a3332008-10-04 03:27:44 +00001776
1777#if 0 /* TODO */
Blue Swirle01d9d32012-04-29 08:54:44 +00001778 if (mode & (1 << 3)) {
1779 set_float_exception_flags(get_float_exception_flags(&env->sse_status) &
1780 ~float_flag_inexact,
1781 &env->sse_status);
1782 }
balrog222a3332008-10-04 03:27:44 +00001783#endif
1784 env->sse_status.float_rounding_mode = prev_rounding_mode;
1785}
1786
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001787void glue(helper_roundss, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
1788 uint32_t mode)
balrog222a3332008-10-04 03:27:44 +00001789{
1790 signed char prev_rounding_mode;
1791
1792 prev_rounding_mode = env->sse_status.float_rounding_mode;
Blue Swirle01d9d32012-04-29 08:54:44 +00001793 if (!(mode & (1 << 2))) {
balrog222a3332008-10-04 03:27:44 +00001794 switch (mode & 3) {
1795 case 0:
1796 set_float_rounding_mode(float_round_nearest_even, &env->sse_status);
1797 break;
1798 case 1:
1799 set_float_rounding_mode(float_round_down, &env->sse_status);
1800 break;
1801 case 2:
1802 set_float_rounding_mode(float_round_up, &env->sse_status);
1803 break;
1804 case 3:
1805 set_float_rounding_mode(float_round_to_zero, &env->sse_status);
1806 break;
1807 }
Blue Swirle01d9d32012-04-29 08:54:44 +00001808 }
balrog222a3332008-10-04 03:27:44 +00001809
Aurelien Jarnoadc71662012-01-07 15:20:11 +01001810 d->XMM_S(0) = float32_round_to_int(s->XMM_S(0), &env->sse_status);
balrog222a3332008-10-04 03:27:44 +00001811
1812#if 0 /* TODO */
Blue Swirle01d9d32012-04-29 08:54:44 +00001813 if (mode & (1 << 3)) {
1814 set_float_exception_flags(get_float_exception_flags(&env->sse_status) &
1815 ~float_flag_inexact,
1816 &env->sse_status);
1817 }
balrog222a3332008-10-04 03:27:44 +00001818#endif
1819 env->sse_status.float_rounding_mode = prev_rounding_mode;
1820}
1821
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001822void glue(helper_roundsd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
1823 uint32_t mode)
balrog222a3332008-10-04 03:27:44 +00001824{
1825 signed char prev_rounding_mode;
1826
1827 prev_rounding_mode = env->sse_status.float_rounding_mode;
Blue Swirle01d9d32012-04-29 08:54:44 +00001828 if (!(mode & (1 << 2))) {
balrog222a3332008-10-04 03:27:44 +00001829 switch (mode & 3) {
1830 case 0:
1831 set_float_rounding_mode(float_round_nearest_even, &env->sse_status);
1832 break;
1833 case 1:
1834 set_float_rounding_mode(float_round_down, &env->sse_status);
1835 break;
1836 case 2:
1837 set_float_rounding_mode(float_round_up, &env->sse_status);
1838 break;
1839 case 3:
1840 set_float_rounding_mode(float_round_to_zero, &env->sse_status);
1841 break;
1842 }
Blue Swirle01d9d32012-04-29 08:54:44 +00001843 }
balrog222a3332008-10-04 03:27:44 +00001844
Aurelien Jarnoadc71662012-01-07 15:20:11 +01001845 d->XMM_D(0) = float64_round_to_int(s->XMM_D(0), &env->sse_status);
balrog222a3332008-10-04 03:27:44 +00001846
1847#if 0 /* TODO */
Blue Swirle01d9d32012-04-29 08:54:44 +00001848 if (mode & (1 << 3)) {
1849 set_float_exception_flags(get_float_exception_flags(&env->sse_status) &
1850 ~float_flag_inexact,
1851 &env->sse_status);
1852 }
balrog222a3332008-10-04 03:27:44 +00001853#endif
1854 env->sse_status.float_rounding_mode = prev_rounding_mode;
1855}
1856
Blue Swirle01d9d32012-04-29 08:54:44 +00001857#define FBLENDP(d, s, m) (m ? s : d)
balrog222a3332008-10-04 03:27:44 +00001858SSE_HELPER_I(helper_blendps, L, 4, FBLENDP)
1859SSE_HELPER_I(helper_blendpd, Q, 2, FBLENDP)
1860SSE_HELPER_I(helper_pblendw, W, 8, FBLENDP)
1861
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001862void glue(helper_dpps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mask)
balrog222a3332008-10-04 03:27:44 +00001863{
Aurelien Jarno170d5b42012-01-07 15:20:12 +01001864 float32 iresult = float32_zero;
balrog222a3332008-10-04 03:27:44 +00001865
Blue Swirle01d9d32012-04-29 08:54:44 +00001866 if (mask & (1 << 4)) {
balrog222a3332008-10-04 03:27:44 +00001867 iresult = float32_add(iresult,
Blue Swirle01d9d32012-04-29 08:54:44 +00001868 float32_mul(d->XMM_S(0), s->XMM_S(0),
1869 &env->sse_status),
1870 &env->sse_status);
1871 }
1872 if (mask & (1 << 5)) {
balrog222a3332008-10-04 03:27:44 +00001873 iresult = float32_add(iresult,
Blue Swirle01d9d32012-04-29 08:54:44 +00001874 float32_mul(d->XMM_S(1), s->XMM_S(1),
1875 &env->sse_status),
1876 &env->sse_status);
1877 }
1878 if (mask & (1 << 6)) {
balrog222a3332008-10-04 03:27:44 +00001879 iresult = float32_add(iresult,
Blue Swirle01d9d32012-04-29 08:54:44 +00001880 float32_mul(d->XMM_S(2), s->XMM_S(2),
1881 &env->sse_status),
1882 &env->sse_status);
1883 }
1884 if (mask & (1 << 7)) {
balrog222a3332008-10-04 03:27:44 +00001885 iresult = float32_add(iresult,
Blue Swirle01d9d32012-04-29 08:54:44 +00001886 float32_mul(d->XMM_S(3), s->XMM_S(3),
1887 &env->sse_status),
1888 &env->sse_status);
1889 }
Aurelien Jarno170d5b42012-01-07 15:20:12 +01001890 d->XMM_S(0) = (mask & (1 << 0)) ? iresult : float32_zero;
1891 d->XMM_S(1) = (mask & (1 << 1)) ? iresult : float32_zero;
1892 d->XMM_S(2) = (mask & (1 << 2)) ? iresult : float32_zero;
1893 d->XMM_S(3) = (mask & (1 << 3)) ? iresult : float32_zero;
balrog222a3332008-10-04 03:27:44 +00001894}
1895
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001896void glue(helper_dppd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mask)
balrog222a3332008-10-04 03:27:44 +00001897{
Aurelien Jarno170d5b42012-01-07 15:20:12 +01001898 float64 iresult = float64_zero;
balrog222a3332008-10-04 03:27:44 +00001899
Blue Swirle01d9d32012-04-29 08:54:44 +00001900 if (mask & (1 << 4)) {
balrog222a3332008-10-04 03:27:44 +00001901 iresult = float64_add(iresult,
Blue Swirle01d9d32012-04-29 08:54:44 +00001902 float64_mul(d->XMM_D(0), s->XMM_D(0),
1903 &env->sse_status),
1904 &env->sse_status);
1905 }
1906 if (mask & (1 << 5)) {
balrog222a3332008-10-04 03:27:44 +00001907 iresult = float64_add(iresult,
Blue Swirle01d9d32012-04-29 08:54:44 +00001908 float64_mul(d->XMM_D(1), s->XMM_D(1),
1909 &env->sse_status),
1910 &env->sse_status);
1911 }
Aurelien Jarno170d5b42012-01-07 15:20:12 +01001912 d->XMM_D(0) = (mask & (1 << 0)) ? iresult : float64_zero;
1913 d->XMM_D(1) = (mask & (1 << 1)) ? iresult : float64_zero;
balrog222a3332008-10-04 03:27:44 +00001914}
1915
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001916void glue(helper_mpsadbw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
1917 uint32_t offset)
balrog222a3332008-10-04 03:27:44 +00001918{
1919 int s0 = (offset & 3) << 2;
1920 int d0 = (offset & 4) << 0;
1921 int i;
1922 Reg r;
1923
1924 for (i = 0; i < 8; i++, d0++) {
1925 r.W(i) = 0;
1926 r.W(i) += abs1(d->B(d0 + 0) - s->B(s0 + 0));
1927 r.W(i) += abs1(d->B(d0 + 1) - s->B(s0 + 1));
1928 r.W(i) += abs1(d->B(d0 + 2) - s->B(s0 + 2));
1929 r.W(i) += abs1(d->B(d0 + 3) - s->B(s0 + 3));
1930 }
1931
1932 *d = r;
1933}
1934
1935/* SSE4.2 op helpers */
1936/* it's unclear whether signed or unsigned */
Blue Swirle01d9d32012-04-29 08:54:44 +00001937#define FCMPGTQ(d, s) (d > s ? -1 : 0)
balrog222a3332008-10-04 03:27:44 +00001938SSE_HELPER_Q(helper_pcmpgtq, FCMPGTQ)
1939
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001940static inline int pcmp_elen(CPUX86State *env, int reg, uint32_t ctrl)
balrog222a3332008-10-04 03:27:44 +00001941{
1942 int val;
1943
1944 /* Presence of REX.W is indicated by a bit higher than 7 set */
Blue Swirle01d9d32012-04-29 08:54:44 +00001945 if (ctrl >> 8) {
1946 val = abs1((int64_t)env->regs[reg]);
1947 } else {
1948 val = abs1((int32_t)env->regs[reg]);
1949 }
balrog222a3332008-10-04 03:27:44 +00001950
1951 if (ctrl & 1) {
Blue Swirle01d9d32012-04-29 08:54:44 +00001952 if (val > 8) {
balrog222a3332008-10-04 03:27:44 +00001953 return 8;
Blue Swirle01d9d32012-04-29 08:54:44 +00001954 }
1955 } else {
1956 if (val > 16) {
balrog222a3332008-10-04 03:27:44 +00001957 return 16;
Blue Swirle01d9d32012-04-29 08:54:44 +00001958 }
1959 }
balrog222a3332008-10-04 03:27:44 +00001960 return val;
1961}
1962
1963static inline int pcmp_ilen(Reg *r, uint8_t ctrl)
1964{
1965 int val = 0;
1966
1967 if (ctrl & 1) {
Blue Swirle01d9d32012-04-29 08:54:44 +00001968 while (val < 8 && r->W(val)) {
balrog222a3332008-10-04 03:27:44 +00001969 val++;
Blue Swirle01d9d32012-04-29 08:54:44 +00001970 }
1971 } else {
1972 while (val < 16 && r->B(val)) {
balrog222a3332008-10-04 03:27:44 +00001973 val++;
Blue Swirle01d9d32012-04-29 08:54:44 +00001974 }
1975 }
balrog222a3332008-10-04 03:27:44 +00001976
1977 return val;
1978}
1979
1980static inline int pcmp_val(Reg *r, uint8_t ctrl, int i)
1981{
1982 switch ((ctrl >> 0) & 3) {
1983 case 0:
1984 return r->B(i);
1985 case 1:
1986 return r->W(i);
1987 case 2:
Blue Swirle01d9d32012-04-29 08:54:44 +00001988 return (int8_t)r->B(i);
balrog222a3332008-10-04 03:27:44 +00001989 case 3:
1990 default:
Blue Swirle01d9d32012-04-29 08:54:44 +00001991 return (int16_t)r->W(i);
balrog222a3332008-10-04 03:27:44 +00001992 }
1993}
1994
Blue Swirld3eb5ea2012-04-28 21:28:09 +00001995static inline unsigned pcmpxstrx(CPUX86State *env, Reg *d, Reg *s,
Blue Swirle01d9d32012-04-29 08:54:44 +00001996 int8_t ctrl, int valids, int validd)
balrog222a3332008-10-04 03:27:44 +00001997{
1998 unsigned int res = 0;
1999 int v;
2000 int j, i;
2001 int upper = (ctrl & 1) ? 7 : 15;
2002
2003 valids--;
2004 validd--;
2005
2006 CC_SRC = (valids < upper ? CC_Z : 0) | (validd < upper ? CC_S : 0);
2007
2008 switch ((ctrl >> 2) & 3) {
2009 case 0:
2010 for (j = valids; j >= 0; j--) {
2011 res <<= 1;
2012 v = pcmp_val(s, ctrl, j);
Blue Swirle01d9d32012-04-29 08:54:44 +00002013 for (i = validd; i >= 0; i--) {
balrog222a3332008-10-04 03:27:44 +00002014 res |= (v == pcmp_val(d, ctrl, i));
Blue Swirle01d9d32012-04-29 08:54:44 +00002015 }
balrog222a3332008-10-04 03:27:44 +00002016 }
2017 break;
2018 case 1:
2019 for (j = valids; j >= 0; j--) {
2020 res <<= 1;
2021 v = pcmp_val(s, ctrl, j);
Blue Swirle01d9d32012-04-29 08:54:44 +00002022 for (i = ((validd - 1) | 1); i >= 0; i -= 2) {
balrog222a3332008-10-04 03:27:44 +00002023 res |= (pcmp_val(d, ctrl, i - 0) <= v &&
2024 pcmp_val(d, ctrl, i - 1) >= v);
Blue Swirle01d9d32012-04-29 08:54:44 +00002025 }
balrog222a3332008-10-04 03:27:44 +00002026 }
2027 break;
2028 case 2:
2029 res = (2 << (upper - MAX(valids, validd))) - 1;
2030 res <<= MAX(valids, validd) - MIN(valids, validd);
2031 for (i = MIN(valids, validd); i >= 0; i--) {
2032 res <<= 1;
2033 v = pcmp_val(s, ctrl, i);
2034 res |= (v == pcmp_val(d, ctrl, i));
2035 }
2036 break;
2037 case 3:
2038 for (j = valids - validd; j >= 0; j--) {
2039 res <<= 1;
2040 res |= 1;
Blue Swirle01d9d32012-04-29 08:54:44 +00002041 for (i = MIN(upper - j, validd); i >= 0; i--) {
balrog222a3332008-10-04 03:27:44 +00002042 res &= (pcmp_val(s, ctrl, i + j) == pcmp_val(d, ctrl, i));
Blue Swirle01d9d32012-04-29 08:54:44 +00002043 }
balrog222a3332008-10-04 03:27:44 +00002044 }
2045 break;
2046 }
2047
2048 switch ((ctrl >> 4) & 3) {
2049 case 1:
2050 res ^= (2 << upper) - 1;
2051 break;
2052 case 3:
2053 res ^= (2 << valids) - 1;
2054 break;
2055 }
2056
Blue Swirle01d9d32012-04-29 08:54:44 +00002057 if (res) {
2058 CC_SRC |= CC_C;
2059 }
2060 if (res & 1) {
2061 CC_SRC |= CC_O;
2062 }
balrog222a3332008-10-04 03:27:44 +00002063
2064 return res;
2065}
2066
2067static inline int rffs1(unsigned int val)
2068{
2069 int ret = 1, hi;
2070
Blue Swirle01d9d32012-04-29 08:54:44 +00002071 for (hi = sizeof(val) * 4; hi; hi /= 2) {
balrog222a3332008-10-04 03:27:44 +00002072 if (val >> hi) {
2073 val >>= hi;
2074 ret += hi;
2075 }
Blue Swirle01d9d32012-04-29 08:54:44 +00002076 }
balrog222a3332008-10-04 03:27:44 +00002077
2078 return ret;
2079}
2080
2081static inline int ffs1(unsigned int val)
2082{
2083 int ret = 1, hi;
2084
Blue Swirle01d9d32012-04-29 08:54:44 +00002085 for (hi = sizeof(val) * 4; hi; hi /= 2) {
balrog222a3332008-10-04 03:27:44 +00002086 if (val << hi) {
2087 val <<= hi;
2088 ret += hi;
2089 }
Blue Swirle01d9d32012-04-29 08:54:44 +00002090 }
balrog222a3332008-10-04 03:27:44 +00002091
2092 return ret;
2093}
2094
Blue Swirld3eb5ea2012-04-28 21:28:09 +00002095void glue(helper_pcmpestri, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
2096 uint32_t ctrl)
balrog222a3332008-10-04 03:27:44 +00002097{
Blue Swirld3eb5ea2012-04-28 21:28:09 +00002098 unsigned int res = pcmpxstrx(env, d, s, ctrl,
2099 pcmp_elen(env, R_EDX, ctrl),
2100 pcmp_elen(env, R_EAX, ctrl));
balrog222a3332008-10-04 03:27:44 +00002101
Blue Swirle01d9d32012-04-29 08:54:44 +00002102 if (res) {
balrog222a3332008-10-04 03:27:44 +00002103 env->regs[R_ECX] = ((ctrl & (1 << 6)) ? rffs1 : ffs1)(res) - 1;
Blue Swirle01d9d32012-04-29 08:54:44 +00002104 } else {
balrog222a3332008-10-04 03:27:44 +00002105 env->regs[R_ECX] = 16 >> (ctrl & (1 << 0));
Blue Swirle01d9d32012-04-29 08:54:44 +00002106 }
balrog222a3332008-10-04 03:27:44 +00002107}
2108
Blue Swirld3eb5ea2012-04-28 21:28:09 +00002109void glue(helper_pcmpestrm, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
2110 uint32_t ctrl)
balrog222a3332008-10-04 03:27:44 +00002111{
2112 int i;
Blue Swirld3eb5ea2012-04-28 21:28:09 +00002113 unsigned int res = pcmpxstrx(env, d, s, ctrl,
2114 pcmp_elen(env, R_EDX, ctrl),
2115 pcmp_elen(env, R_EAX, ctrl));
balrog222a3332008-10-04 03:27:44 +00002116
2117 if ((ctrl >> 6) & 1) {
Blue Swirle01d9d32012-04-29 08:54:44 +00002118 if (ctrl & 1) {
Blue Swirlbc426892011-11-13 11:11:52 +00002119 for (i = 0; i < 8; i++, res >>= 1) {
balrog222a3332008-10-04 03:27:44 +00002120 d->W(i) = (res & 1) ? ~0 : 0;
Blue Swirlbc426892011-11-13 11:11:52 +00002121 }
Blue Swirle01d9d32012-04-29 08:54:44 +00002122 } else {
Blue Swirlbc426892011-11-13 11:11:52 +00002123 for (i = 0; i < 16; i++, res >>= 1) {
balrog222a3332008-10-04 03:27:44 +00002124 d->B(i) = (res & 1) ? ~0 : 0;
Blue Swirlbc426892011-11-13 11:11:52 +00002125 }
Blue Swirle01d9d32012-04-29 08:54:44 +00002126 }
balrog222a3332008-10-04 03:27:44 +00002127 } else {
2128 d->Q(1) = 0;
2129 d->Q(0) = res;
2130 }
2131}
2132
Blue Swirld3eb5ea2012-04-28 21:28:09 +00002133void glue(helper_pcmpistri, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
2134 uint32_t ctrl)
balrog222a3332008-10-04 03:27:44 +00002135{
Blue Swirld3eb5ea2012-04-28 21:28:09 +00002136 unsigned int res = pcmpxstrx(env, d, s, ctrl,
Blue Swirle01d9d32012-04-29 08:54:44 +00002137 pcmp_ilen(s, ctrl),
2138 pcmp_ilen(d, ctrl));
balrog222a3332008-10-04 03:27:44 +00002139
Blue Swirle01d9d32012-04-29 08:54:44 +00002140 if (res) {
balrog222a3332008-10-04 03:27:44 +00002141 env->regs[R_ECX] = ((ctrl & (1 << 6)) ? rffs1 : ffs1)(res) - 1;
Blue Swirle01d9d32012-04-29 08:54:44 +00002142 } else {
balrog222a3332008-10-04 03:27:44 +00002143 env->regs[R_ECX] = 16 >> (ctrl & (1 << 0));
Blue Swirle01d9d32012-04-29 08:54:44 +00002144 }
balrog222a3332008-10-04 03:27:44 +00002145}
2146
Blue Swirld3eb5ea2012-04-28 21:28:09 +00002147void glue(helper_pcmpistrm, SUFFIX)(CPUX86State *env, Reg *d, Reg *s,
2148 uint32_t ctrl)
balrog222a3332008-10-04 03:27:44 +00002149{
2150 int i;
Blue Swirld3eb5ea2012-04-28 21:28:09 +00002151 unsigned int res = pcmpxstrx(env, d, s, ctrl,
Blue Swirle01d9d32012-04-29 08:54:44 +00002152 pcmp_ilen(s, ctrl),
2153 pcmp_ilen(d, ctrl));
balrog222a3332008-10-04 03:27:44 +00002154
2155 if ((ctrl >> 6) & 1) {
Blue Swirle01d9d32012-04-29 08:54:44 +00002156 if (ctrl & 1) {
Blue Swirlbc426892011-11-13 11:11:52 +00002157 for (i = 0; i < 8; i++, res >>= 1) {
balrog222a3332008-10-04 03:27:44 +00002158 d->W(i) = (res & 1) ? ~0 : 0;
Blue Swirlbc426892011-11-13 11:11:52 +00002159 }
Blue Swirle01d9d32012-04-29 08:54:44 +00002160 } else {
Blue Swirlbc426892011-11-13 11:11:52 +00002161 for (i = 0; i < 16; i++, res >>= 1) {
balrog222a3332008-10-04 03:27:44 +00002162 d->B(i) = (res & 1) ? ~0 : 0;
Blue Swirlbc426892011-11-13 11:11:52 +00002163 }
Blue Swirle01d9d32012-04-29 08:54:44 +00002164 }
balrog222a3332008-10-04 03:27:44 +00002165 } else {
2166 d->Q(1) = 0;
2167 d->Q(0) = res;
2168 }
2169}
2170
2171#define CRCPOLY 0x1edc6f41
2172#define CRCPOLY_BITREV 0x82f63b78
2173target_ulong helper_crc32(uint32_t crc1, target_ulong msg, uint32_t len)
2174{
2175 target_ulong crc = (msg & ((target_ulong) -1 >>
Blue Swirle01d9d32012-04-29 08:54:44 +00002176 (TARGET_LONG_BITS - len))) ^ crc1;
balrog222a3332008-10-04 03:27:44 +00002177
Blue Swirle01d9d32012-04-29 08:54:44 +00002178 while (len--) {
balrog222a3332008-10-04 03:27:44 +00002179 crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_BITREV : 0);
Blue Swirle01d9d32012-04-29 08:54:44 +00002180 }
balrog222a3332008-10-04 03:27:44 +00002181
2182 return crc;
2183}
2184
2185#define POPMASK(i) ((target_ulong) -1 / ((1LL << (1 << i)) + 1))
Blue Swirle01d9d32012-04-29 08:54:44 +00002186#define POPCOUNT(n, i) ((n & POPMASK(i)) + ((n >> (1 << i)) & POPMASK(i)))
Blue Swirld3eb5ea2012-04-28 21:28:09 +00002187target_ulong helper_popcnt(CPUX86State *env, target_ulong n, uint32_t type)
balrog222a3332008-10-04 03:27:44 +00002188{
2189 CC_SRC = n ? 0 : CC_Z;
2190
2191 n = POPCOUNT(n, 0);
2192 n = POPCOUNT(n, 1);
2193 n = POPCOUNT(n, 2);
2194 n = POPCOUNT(n, 3);
Blue Swirle01d9d32012-04-29 08:54:44 +00002195 if (type == 1) {
balrog222a3332008-10-04 03:27:44 +00002196 return n & 0xff;
Blue Swirle01d9d32012-04-29 08:54:44 +00002197 }
balrog222a3332008-10-04 03:27:44 +00002198
2199 n = POPCOUNT(n, 4);
2200#ifndef TARGET_X86_64
2201 return n;
2202#else
Blue Swirle01d9d32012-04-29 08:54:44 +00002203 if (type == 2) {
balrog222a3332008-10-04 03:27:44 +00002204 return n & 0xff;
Blue Swirle01d9d32012-04-29 08:54:44 +00002205 }
balrog222a3332008-10-04 03:27:44 +00002206
2207 return POPCOUNT(n, 5);
2208#endif
2209}
2210#endif
2211
bellard664e0f12005-01-08 18:58:29 +00002212#undef SHIFT
2213#undef XMM_ONLY
2214#undef Reg
2215#undef B
2216#undef W
2217#undef L
2218#undef Q
2219#undef SUFFIX