bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1 | /* |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2 | * MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI support |
ths | 5fafdf2 | 2007-09-16 21:08:06 +0000 | [diff] [blame] | 3 | * |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 4 | * Copyright (c) 2005 Fabrice Bellard |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 5 | * Copyright (c) 2008 Intel Corporation <andrew.zaborowski@intel.com> |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 6 | * |
| 7 | * This library is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU Lesser General Public |
| 9 | * License as published by the Free Software Foundation; either |
| 10 | * version 2 of the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This library is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 15 | * Lesser General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU Lesser General Public |
Blue Swirl | 8167ee8 | 2009-07-16 20:47:01 +0000 | [diff] [blame] | 18 | * License along with this library; if not, see <http://www.gnu.org/licenses/>. |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 19 | */ |
| 20 | #if SHIFT == 0 |
| 21 | #define Reg MMXReg |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 22 | #define XMM_ONLY(...) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 23 | #define B(n) MMX_B(n) |
| 24 | #define W(n) MMX_W(n) |
| 25 | #define L(n) MMX_L(n) |
| 26 | #define Q(n) q |
| 27 | #define SUFFIX _mmx |
| 28 | #else |
| 29 | #define Reg XMMReg |
Blue Swirl | 001faf3 | 2009-05-13 17:53:17 +0000 | [diff] [blame] | 30 | #define XMM_ONLY(...) __VA_ARGS__ |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 31 | #define B(n) XMM_B(n) |
| 32 | #define W(n) XMM_W(n) |
| 33 | #define L(n) XMM_L(n) |
| 34 | #define Q(n) XMM_Q(n) |
| 35 | #define SUFFIX _xmm |
| 36 | #endif |
| 37 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 38 | void glue(helper_psrlw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 39 | { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 40 | int shift; |
| 41 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 42 | if (s->Q(0) > 15) { |
| 43 | d->Q(0) = 0; |
| 44 | #if SHIFT == 1 |
| 45 | d->Q(1) = 0; |
| 46 | #endif |
| 47 | } else { |
| 48 | shift = s->B(0); |
| 49 | d->W(0) >>= shift; |
| 50 | d->W(1) >>= shift; |
| 51 | d->W(2) >>= shift; |
| 52 | d->W(3) >>= shift; |
| 53 | #if SHIFT == 1 |
| 54 | d->W(4) >>= shift; |
| 55 | d->W(5) >>= shift; |
| 56 | d->W(6) >>= shift; |
| 57 | d->W(7) >>= shift; |
| 58 | #endif |
| 59 | } |
| 60 | } |
| 61 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 62 | void glue(helper_psraw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 63 | { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 64 | int shift; |
| 65 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 66 | if (s->Q(0) > 15) { |
| 67 | shift = 15; |
| 68 | } else { |
| 69 | shift = s->B(0); |
| 70 | } |
| 71 | d->W(0) = (int16_t)d->W(0) >> shift; |
| 72 | d->W(1) = (int16_t)d->W(1) >> shift; |
| 73 | d->W(2) = (int16_t)d->W(2) >> shift; |
| 74 | d->W(3) = (int16_t)d->W(3) >> shift; |
| 75 | #if SHIFT == 1 |
| 76 | d->W(4) = (int16_t)d->W(4) >> shift; |
| 77 | d->W(5) = (int16_t)d->W(5) >> shift; |
| 78 | d->W(6) = (int16_t)d->W(6) >> shift; |
| 79 | d->W(7) = (int16_t)d->W(7) >> shift; |
| 80 | #endif |
| 81 | } |
| 82 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 83 | void glue(helper_psllw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 84 | { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 85 | int shift; |
| 86 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 87 | if (s->Q(0) > 15) { |
| 88 | d->Q(0) = 0; |
| 89 | #if SHIFT == 1 |
| 90 | d->Q(1) = 0; |
| 91 | #endif |
| 92 | } else { |
| 93 | shift = s->B(0); |
| 94 | d->W(0) <<= shift; |
| 95 | d->W(1) <<= shift; |
| 96 | d->W(2) <<= shift; |
| 97 | d->W(3) <<= shift; |
| 98 | #if SHIFT == 1 |
| 99 | d->W(4) <<= shift; |
| 100 | d->W(5) <<= shift; |
| 101 | d->W(6) <<= shift; |
| 102 | d->W(7) <<= shift; |
| 103 | #endif |
| 104 | } |
| 105 | } |
| 106 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 107 | void glue(helper_psrld, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 108 | { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 109 | int shift; |
| 110 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 111 | if (s->Q(0) > 31) { |
| 112 | d->Q(0) = 0; |
| 113 | #if SHIFT == 1 |
| 114 | d->Q(1) = 0; |
| 115 | #endif |
| 116 | } else { |
| 117 | shift = s->B(0); |
| 118 | d->L(0) >>= shift; |
| 119 | d->L(1) >>= shift; |
| 120 | #if SHIFT == 1 |
| 121 | d->L(2) >>= shift; |
| 122 | d->L(3) >>= shift; |
| 123 | #endif |
| 124 | } |
| 125 | } |
| 126 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 127 | void glue(helper_psrad, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 128 | { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 129 | int shift; |
| 130 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 131 | if (s->Q(0) > 31) { |
| 132 | shift = 31; |
| 133 | } else { |
| 134 | shift = s->B(0); |
| 135 | } |
| 136 | d->L(0) = (int32_t)d->L(0) >> shift; |
| 137 | d->L(1) = (int32_t)d->L(1) >> shift; |
| 138 | #if SHIFT == 1 |
| 139 | d->L(2) = (int32_t)d->L(2) >> shift; |
| 140 | d->L(3) = (int32_t)d->L(3) >> shift; |
| 141 | #endif |
| 142 | } |
| 143 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 144 | void glue(helper_pslld, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 145 | { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 146 | int shift; |
| 147 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 148 | if (s->Q(0) > 31) { |
| 149 | d->Q(0) = 0; |
| 150 | #if SHIFT == 1 |
| 151 | d->Q(1) = 0; |
| 152 | #endif |
| 153 | } else { |
| 154 | shift = s->B(0); |
| 155 | d->L(0) <<= shift; |
| 156 | d->L(1) <<= shift; |
| 157 | #if SHIFT == 1 |
| 158 | d->L(2) <<= shift; |
| 159 | d->L(3) <<= shift; |
| 160 | #endif |
| 161 | } |
| 162 | } |
| 163 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 164 | void glue(helper_psrlq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 165 | { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 166 | int shift; |
| 167 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 168 | if (s->Q(0) > 63) { |
| 169 | d->Q(0) = 0; |
| 170 | #if SHIFT == 1 |
| 171 | d->Q(1) = 0; |
| 172 | #endif |
| 173 | } else { |
| 174 | shift = s->B(0); |
| 175 | d->Q(0) >>= shift; |
| 176 | #if SHIFT == 1 |
| 177 | d->Q(1) >>= shift; |
| 178 | #endif |
| 179 | } |
| 180 | } |
| 181 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 182 | void glue(helper_psllq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 183 | { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 184 | int shift; |
| 185 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 186 | if (s->Q(0) > 63) { |
| 187 | d->Q(0) = 0; |
| 188 | #if SHIFT == 1 |
| 189 | d->Q(1) = 0; |
| 190 | #endif |
| 191 | } else { |
| 192 | shift = s->B(0); |
| 193 | d->Q(0) <<= shift; |
| 194 | #if SHIFT == 1 |
| 195 | d->Q(1) <<= shift; |
| 196 | #endif |
| 197 | } |
| 198 | } |
| 199 | |
| 200 | #if SHIFT == 1 |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 201 | void glue(helper_psrldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 202 | { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 203 | int shift, i; |
| 204 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 205 | shift = s->L(0); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 206 | if (shift > 16) { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 207 | shift = 16; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 208 | } |
| 209 | for (i = 0; i < 16 - shift; i++) { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 210 | d->B(i) = d->B(i + shift); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 211 | } |
| 212 | for (i = 16 - shift; i < 16; i++) { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 213 | d->B(i) = 0; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 214 | } |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 215 | } |
| 216 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 217 | void glue(helper_pslldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 218 | { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 219 | int shift, i; |
| 220 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 221 | shift = s->L(0); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 222 | if (shift > 16) { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 223 | shift = 16; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 224 | } |
| 225 | for (i = 15; i >= shift; i--) { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 226 | d->B(i) = d->B(i - shift); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 227 | } |
| 228 | for (i = 0; i < shift; i++) { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 229 | d->B(i) = 0; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 230 | } |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 231 | } |
| 232 | #endif |
| 233 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 234 | #define SSE_HELPER_B(name, F) \ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 235 | void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 236 | { \ |
| 237 | d->B(0) = F(d->B(0), s->B(0)); \ |
| 238 | d->B(1) = F(d->B(1), s->B(1)); \ |
| 239 | d->B(2) = F(d->B(2), s->B(2)); \ |
| 240 | d->B(3) = F(d->B(3), s->B(3)); \ |
| 241 | d->B(4) = F(d->B(4), s->B(4)); \ |
| 242 | d->B(5) = F(d->B(5), s->B(5)); \ |
| 243 | d->B(6) = F(d->B(6), s->B(6)); \ |
| 244 | d->B(7) = F(d->B(7), s->B(7)); \ |
| 245 | XMM_ONLY( \ |
| 246 | d->B(8) = F(d->B(8), s->B(8)); \ |
| 247 | d->B(9) = F(d->B(9), s->B(9)); \ |
| 248 | d->B(10) = F(d->B(10), s->B(10)); \ |
| 249 | d->B(11) = F(d->B(11), s->B(11)); \ |
| 250 | d->B(12) = F(d->B(12), s->B(12)); \ |
| 251 | d->B(13) = F(d->B(13), s->B(13)); \ |
| 252 | d->B(14) = F(d->B(14), s->B(14)); \ |
| 253 | d->B(15) = F(d->B(15), s->B(15)); \ |
| 254 | ) \ |
| 255 | } |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 256 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 257 | #define SSE_HELPER_W(name, F) \ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 258 | void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 259 | { \ |
| 260 | d->W(0) = F(d->W(0), s->W(0)); \ |
| 261 | d->W(1) = F(d->W(1), s->W(1)); \ |
| 262 | d->W(2) = F(d->W(2), s->W(2)); \ |
| 263 | d->W(3) = F(d->W(3), s->W(3)); \ |
| 264 | XMM_ONLY( \ |
| 265 | d->W(4) = F(d->W(4), s->W(4)); \ |
| 266 | d->W(5) = F(d->W(5), s->W(5)); \ |
| 267 | d->W(6) = F(d->W(6), s->W(6)); \ |
| 268 | d->W(7) = F(d->W(7), s->W(7)); \ |
| 269 | ) \ |
| 270 | } |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 271 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 272 | #define SSE_HELPER_L(name, F) \ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 273 | void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 274 | { \ |
| 275 | d->L(0) = F(d->L(0), s->L(0)); \ |
| 276 | d->L(1) = F(d->L(1), s->L(1)); \ |
| 277 | XMM_ONLY( \ |
| 278 | d->L(2) = F(d->L(2), s->L(2)); \ |
| 279 | d->L(3) = F(d->L(3), s->L(3)); \ |
| 280 | ) \ |
| 281 | } |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 282 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 283 | #define SSE_HELPER_Q(name, F) \ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 284 | void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 285 | { \ |
| 286 | d->Q(0) = F(d->Q(0), s->Q(0)); \ |
| 287 | XMM_ONLY( \ |
| 288 | d->Q(1) = F(d->Q(1), s->Q(1)); \ |
| 289 | ) \ |
| 290 | } |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 291 | |
| 292 | #if SHIFT == 0 |
| 293 | static inline int satub(int x) |
| 294 | { |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 295 | if (x < 0) { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 296 | return 0; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 297 | } else if (x > 255) { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 298 | return 255; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 299 | } else { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 300 | return x; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 301 | } |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 302 | } |
| 303 | |
| 304 | static inline int satuw(int x) |
| 305 | { |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 306 | if (x < 0) { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 307 | return 0; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 308 | } else if (x > 65535) { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 309 | return 65535; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 310 | } else { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 311 | return x; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 312 | } |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 313 | } |
| 314 | |
| 315 | static inline int satsb(int x) |
| 316 | { |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 317 | if (x < -128) { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 318 | return -128; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 319 | } else if (x > 127) { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 320 | return 127; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 321 | } else { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 322 | return x; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 323 | } |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 324 | } |
| 325 | |
| 326 | static inline int satsw(int x) |
| 327 | { |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 328 | if (x < -32768) { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 329 | return -32768; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 330 | } else if (x > 32767) { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 331 | return 32767; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 332 | } else { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 333 | return x; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 334 | } |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 335 | } |
| 336 | |
| 337 | #define FADD(a, b) ((a) + (b)) |
| 338 | #define FADDUB(a, b) satub((a) + (b)) |
| 339 | #define FADDUW(a, b) satuw((a) + (b)) |
| 340 | #define FADDSB(a, b) satsb((int8_t)(a) + (int8_t)(b)) |
| 341 | #define FADDSW(a, b) satsw((int16_t)(a) + (int16_t)(b)) |
| 342 | |
| 343 | #define FSUB(a, b) ((a) - (b)) |
| 344 | #define FSUBUB(a, b) satub((a) - (b)) |
| 345 | #define FSUBUW(a, b) satuw((a) - (b)) |
| 346 | #define FSUBSB(a, b) satsb((int8_t)(a) - (int8_t)(b)) |
| 347 | #define FSUBSW(a, b) satsw((int16_t)(a) - (int16_t)(b)) |
| 348 | #define FMINUB(a, b) ((a) < (b)) ? (a) : (b) |
| 349 | #define FMINSW(a, b) ((int16_t)(a) < (int16_t)(b)) ? (a) : (b) |
| 350 | #define FMAXUB(a, b) ((a) > (b)) ? (a) : (b) |
| 351 | #define FMAXSW(a, b) ((int16_t)(a) > (int16_t)(b)) ? (a) : (b) |
| 352 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 353 | #define FAND(a, b) ((a) & (b)) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 354 | #define FANDN(a, b) ((~(a)) & (b)) |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 355 | #define FOR(a, b) ((a) | (b)) |
| 356 | #define FXOR(a, b) ((a) ^ (b)) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 357 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 358 | #define FCMPGTB(a, b) ((int8_t)(a) > (int8_t)(b) ? -1 : 0) |
| 359 | #define FCMPGTW(a, b) ((int16_t)(a) > (int16_t)(b) ? -1 : 0) |
| 360 | #define FCMPGTL(a, b) ((int32_t)(a) > (int32_t)(b) ? -1 : 0) |
| 361 | #define FCMPEQ(a, b) ((a) == (b) ? -1 : 0) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 362 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 363 | #define FMULLW(a, b) ((a) * (b)) |
| 364 | #define FMULHRW(a, b) (((int16_t)(a) * (int16_t)(b) + 0x8000) >> 16) |
| 365 | #define FMULHUW(a, b) ((a) * (b) >> 16) |
| 366 | #define FMULHW(a, b) ((int16_t)(a) * (int16_t)(b) >> 16) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 367 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 368 | #define FAVG(a, b) (((a) + (b) + 1) >> 1) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 369 | #endif |
| 370 | |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 371 | SSE_HELPER_B(helper_paddb, FADD) |
| 372 | SSE_HELPER_W(helper_paddw, FADD) |
| 373 | SSE_HELPER_L(helper_paddl, FADD) |
| 374 | SSE_HELPER_Q(helper_paddq, FADD) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 375 | |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 376 | SSE_HELPER_B(helper_psubb, FSUB) |
| 377 | SSE_HELPER_W(helper_psubw, FSUB) |
| 378 | SSE_HELPER_L(helper_psubl, FSUB) |
| 379 | SSE_HELPER_Q(helper_psubq, FSUB) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 380 | |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 381 | SSE_HELPER_B(helper_paddusb, FADDUB) |
| 382 | SSE_HELPER_B(helper_paddsb, FADDSB) |
| 383 | SSE_HELPER_B(helper_psubusb, FSUBUB) |
| 384 | SSE_HELPER_B(helper_psubsb, FSUBSB) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 385 | |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 386 | SSE_HELPER_W(helper_paddusw, FADDUW) |
| 387 | SSE_HELPER_W(helper_paddsw, FADDSW) |
| 388 | SSE_HELPER_W(helper_psubusw, FSUBUW) |
| 389 | SSE_HELPER_W(helper_psubsw, FSUBSW) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 390 | |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 391 | SSE_HELPER_B(helper_pminub, FMINUB) |
| 392 | SSE_HELPER_B(helper_pmaxub, FMAXUB) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 393 | |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 394 | SSE_HELPER_W(helper_pminsw, FMINSW) |
| 395 | SSE_HELPER_W(helper_pmaxsw, FMAXSW) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 396 | |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 397 | SSE_HELPER_Q(helper_pand, FAND) |
| 398 | SSE_HELPER_Q(helper_pandn, FANDN) |
| 399 | SSE_HELPER_Q(helper_por, FOR) |
| 400 | SSE_HELPER_Q(helper_pxor, FXOR) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 401 | |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 402 | SSE_HELPER_B(helper_pcmpgtb, FCMPGTB) |
| 403 | SSE_HELPER_W(helper_pcmpgtw, FCMPGTW) |
| 404 | SSE_HELPER_L(helper_pcmpgtl, FCMPGTL) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 405 | |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 406 | SSE_HELPER_B(helper_pcmpeqb, FCMPEQ) |
| 407 | SSE_HELPER_W(helper_pcmpeqw, FCMPEQ) |
| 408 | SSE_HELPER_L(helper_pcmpeql, FCMPEQ) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 409 | |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 410 | SSE_HELPER_W(helper_pmullw, FMULLW) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 411 | #if SHIFT == 0 |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 412 | SSE_HELPER_W(helper_pmulhrw, FMULHRW) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 413 | #endif |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 414 | SSE_HELPER_W(helper_pmulhuw, FMULHUW) |
| 415 | SSE_HELPER_W(helper_pmulhw, FMULHW) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 416 | |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 417 | SSE_HELPER_B(helper_pavgb, FAVG) |
| 418 | SSE_HELPER_W(helper_pavgw, FAVG) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 419 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 420 | void glue(helper_pmuludq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 421 | { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 422 | d->Q(0) = (uint64_t)s->L(0) * (uint64_t)d->L(0); |
| 423 | #if SHIFT == 1 |
| 424 | d->Q(1) = (uint64_t)s->L(2) * (uint64_t)d->L(2); |
| 425 | #endif |
| 426 | } |
| 427 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 428 | void glue(helper_pmaddwd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 429 | { |
| 430 | int i; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 431 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 432 | for (i = 0; i < (2 << SHIFT); i++) { |
| 433 | d->L(i) = (int16_t)s->W(2 * i) * (int16_t)d->W(2 * i) + |
| 434 | (int16_t)s->W(2 * i + 1) * (int16_t)d->W(2 * i + 1); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 435 | } |
| 436 | } |
| 437 | |
| 438 | #if SHIFT == 0 |
| 439 | static inline int abs1(int a) |
| 440 | { |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 441 | if (a < 0) { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 442 | return -a; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 443 | } else { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 444 | return a; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 445 | } |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 446 | } |
| 447 | #endif |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 448 | void glue(helper_psadbw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 449 | { |
| 450 | unsigned int val; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 451 | |
| 452 | val = 0; |
| 453 | val += abs1(d->B(0) - s->B(0)); |
| 454 | val += abs1(d->B(1) - s->B(1)); |
| 455 | val += abs1(d->B(2) - s->B(2)); |
| 456 | val += abs1(d->B(3) - s->B(3)); |
| 457 | val += abs1(d->B(4) - s->B(4)); |
| 458 | val += abs1(d->B(5) - s->B(5)); |
| 459 | val += abs1(d->B(6) - s->B(6)); |
| 460 | val += abs1(d->B(7) - s->B(7)); |
| 461 | d->Q(0) = val; |
| 462 | #if SHIFT == 1 |
| 463 | val = 0; |
| 464 | val += abs1(d->B(8) - s->B(8)); |
| 465 | val += abs1(d->B(9) - s->B(9)); |
| 466 | val += abs1(d->B(10) - s->B(10)); |
| 467 | val += abs1(d->B(11) - s->B(11)); |
| 468 | val += abs1(d->B(12) - s->B(12)); |
| 469 | val += abs1(d->B(13) - s->B(13)); |
| 470 | val += abs1(d->B(14) - s->B(14)); |
| 471 | val += abs1(d->B(15) - s->B(15)); |
| 472 | d->Q(1) = val; |
| 473 | #endif |
| 474 | } |
| 475 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 476 | void glue(helper_maskmov, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, |
| 477 | target_ulong a0) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 478 | { |
| 479 | int i; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 480 | |
| 481 | for (i = 0; i < (8 << SHIFT); i++) { |
| 482 | if (s->B(i) & 0x80) { |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 483 | cpu_stb_data(env, a0 + i, d->B(i)); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 484 | } |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 485 | } |
| 486 | } |
| 487 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 488 | void glue(helper_movl_mm_T0, SUFFIX)(Reg *d, uint32_t val) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 489 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 490 | d->L(0) = val; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 491 | d->L(1) = 0; |
| 492 | #if SHIFT == 1 |
| 493 | d->Q(1) = 0; |
| 494 | #endif |
| 495 | } |
| 496 | |
bellard | dabd98d | 2007-01-16 19:28:58 +0000 | [diff] [blame] | 497 | #ifdef TARGET_X86_64 |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 498 | void glue(helper_movq_mm_T0, SUFFIX)(Reg *d, uint64_t val) |
bellard | dabd98d | 2007-01-16 19:28:58 +0000 | [diff] [blame] | 499 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 500 | d->Q(0) = val; |
bellard | dabd98d | 2007-01-16 19:28:58 +0000 | [diff] [blame] | 501 | #if SHIFT == 1 |
| 502 | d->Q(1) = 0; |
| 503 | #endif |
| 504 | } |
bellard | dabd98d | 2007-01-16 19:28:58 +0000 | [diff] [blame] | 505 | #endif |
| 506 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 507 | #if SHIFT == 0 |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 508 | void glue(helper_pshufw, SUFFIX)(Reg *d, Reg *s, int order) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 509 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 510 | Reg r; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 511 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 512 | r.W(0) = s->W(order & 3); |
| 513 | r.W(1) = s->W((order >> 2) & 3); |
| 514 | r.W(2) = s->W((order >> 4) & 3); |
| 515 | r.W(3) = s->W((order >> 6) & 3); |
| 516 | *d = r; |
| 517 | } |
| 518 | #else |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 519 | void helper_shufps(Reg *d, Reg *s, int order) |
bellard | d52cf7a | 2005-01-16 01:07:28 +0000 | [diff] [blame] | 520 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 521 | Reg r; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 522 | |
bellard | d52cf7a | 2005-01-16 01:07:28 +0000 | [diff] [blame] | 523 | r.L(0) = d->L(order & 3); |
| 524 | r.L(1) = d->L((order >> 2) & 3); |
| 525 | r.L(2) = s->L((order >> 4) & 3); |
| 526 | r.L(3) = s->L((order >> 6) & 3); |
| 527 | *d = r; |
| 528 | } |
| 529 | |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 530 | void helper_shufpd(Reg *d, Reg *s, int order) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 531 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 532 | Reg r; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 533 | |
bellard | d52cf7a | 2005-01-16 01:07:28 +0000 | [diff] [blame] | 534 | r.Q(0) = d->Q(order & 1); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 535 | r.Q(1) = s->Q((order >> 1) & 1); |
| 536 | *d = r; |
| 537 | } |
| 538 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 539 | void glue(helper_pshufd, SUFFIX)(Reg *d, Reg *s, int order) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 540 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 541 | Reg r; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 542 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 543 | r.L(0) = s->L(order & 3); |
| 544 | r.L(1) = s->L((order >> 2) & 3); |
| 545 | r.L(2) = s->L((order >> 4) & 3); |
| 546 | r.L(3) = s->L((order >> 6) & 3); |
| 547 | *d = r; |
| 548 | } |
| 549 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 550 | void glue(helper_pshuflw, SUFFIX)(Reg *d, Reg *s, int order) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 551 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 552 | Reg r; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 553 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 554 | r.W(0) = s->W(order & 3); |
| 555 | r.W(1) = s->W((order >> 2) & 3); |
| 556 | r.W(2) = s->W((order >> 4) & 3); |
| 557 | r.W(3) = s->W((order >> 6) & 3); |
| 558 | r.Q(1) = s->Q(1); |
| 559 | *d = r; |
| 560 | } |
| 561 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 562 | void glue(helper_pshufhw, SUFFIX)(Reg *d, Reg *s, int order) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 563 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 564 | Reg r; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 565 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 566 | r.Q(0) = s->Q(0); |
| 567 | r.W(4) = s->W(4 + (order & 3)); |
| 568 | r.W(5) = s->W(4 + ((order >> 2) & 3)); |
| 569 | r.W(6) = s->W(4 + ((order >> 4) & 3)); |
| 570 | r.W(7) = s->W(4 + ((order >> 6) & 3)); |
| 571 | *d = r; |
| 572 | } |
| 573 | #endif |
| 574 | |
| 575 | #if SHIFT == 1 |
| 576 | /* FPU ops */ |
| 577 | /* XXX: not accurate */ |
| 578 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 579 | #define SSE_HELPER_S(name, F) \ |
| 580 | void helper_ ## name ## ps(CPUX86State *env, Reg *d, Reg *s) \ |
| 581 | { \ |
| 582 | d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \ |
| 583 | d->XMM_S(1) = F(32, d->XMM_S(1), s->XMM_S(1)); \ |
| 584 | d->XMM_S(2) = F(32, d->XMM_S(2), s->XMM_S(2)); \ |
| 585 | d->XMM_S(3) = F(32, d->XMM_S(3), s->XMM_S(3)); \ |
| 586 | } \ |
| 587 | \ |
| 588 | void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *s) \ |
| 589 | { \ |
| 590 | d->XMM_S(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \ |
| 591 | } \ |
| 592 | \ |
| 593 | void helper_ ## name ## pd(CPUX86State *env, Reg *d, Reg *s) \ |
| 594 | { \ |
| 595 | d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \ |
| 596 | d->XMM_D(1) = F(64, d->XMM_D(1), s->XMM_D(1)); \ |
| 597 | } \ |
| 598 | \ |
| 599 | void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *s) \ |
| 600 | { \ |
| 601 | d->XMM_D(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 602 | } |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 603 | |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 604 | #define FPU_ADD(size, a, b) float ## size ## _add(a, b, &env->sse_status) |
| 605 | #define FPU_SUB(size, a, b) float ## size ## _sub(a, b, &env->sse_status) |
| 606 | #define FPU_MUL(size, a, b) float ## size ## _mul(a, b, &env->sse_status) |
| 607 | #define FPU_DIV(size, a, b) float ## size ## _div(a, b, &env->sse_status) |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 608 | #define FPU_SQRT(size, a, b) float ## size ## _sqrt(b, &env->sse_status) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 609 | |
Aurelien Jarno | a4d1f14 | 2012-01-07 15:20:11 +0100 | [diff] [blame] | 610 | /* Note that the choice of comparison op here is important to get the |
| 611 | * special cases right: for min and max Intel specifies that (-0,0), |
| 612 | * (NaN, anything) and (anything, NaN) return the second argument. |
| 613 | */ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 614 | #define FPU_MIN(size, a, b) \ |
| 615 | (float ## size ## _lt(a, b, &env->sse_status) ? (a) : (b)) |
| 616 | #define FPU_MAX(size, a, b) \ |
| 617 | (float ## size ## _lt(b, a, &env->sse_status) ? (a) : (b)) |
Aurelien Jarno | a4d1f14 | 2012-01-07 15:20:11 +0100 | [diff] [blame] | 618 | |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 619 | SSE_HELPER_S(add, FPU_ADD) |
| 620 | SSE_HELPER_S(sub, FPU_SUB) |
| 621 | SSE_HELPER_S(mul, FPU_MUL) |
| 622 | SSE_HELPER_S(div, FPU_DIV) |
| 623 | SSE_HELPER_S(min, FPU_MIN) |
| 624 | SSE_HELPER_S(max, FPU_MAX) |
| 625 | SSE_HELPER_S(sqrt, FPU_SQRT) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 626 | |
| 627 | |
| 628 | /* float to float conversions */ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 629 | void helper_cvtps2pd(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 630 | { |
bellard | 8422b11 | 2005-03-20 10:39:24 +0000 | [diff] [blame] | 631 | float32 s0, s1; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 632 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 633 | s0 = s->XMM_S(0); |
| 634 | s1 = s->XMM_S(1); |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 635 | d->XMM_D(0) = float32_to_float64(s0, &env->sse_status); |
| 636 | d->XMM_D(1) = float32_to_float64(s1, &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 637 | } |
| 638 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 639 | void helper_cvtpd2ps(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 640 | { |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 641 | d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status); |
| 642 | d->XMM_S(1) = float64_to_float32(s->XMM_D(1), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 643 | d->Q(1) = 0; |
| 644 | } |
| 645 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 646 | void helper_cvtss2sd(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 647 | { |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 648 | d->XMM_D(0) = float32_to_float64(s->XMM_S(0), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 649 | } |
| 650 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 651 | void helper_cvtsd2ss(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 652 | { |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 653 | d->XMM_S(0) = float64_to_float32(s->XMM_D(0), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 654 | } |
| 655 | |
| 656 | /* integer to float */ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 657 | void helper_cvtdq2ps(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 658 | { |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 659 | d->XMM_S(0) = int32_to_float32(s->XMM_L(0), &env->sse_status); |
| 660 | d->XMM_S(1) = int32_to_float32(s->XMM_L(1), &env->sse_status); |
| 661 | d->XMM_S(2) = int32_to_float32(s->XMM_L(2), &env->sse_status); |
| 662 | d->XMM_S(3) = int32_to_float32(s->XMM_L(3), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 663 | } |
| 664 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 665 | void helper_cvtdq2pd(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 666 | { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 667 | int32_t l0, l1; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 668 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 669 | l0 = (int32_t)s->XMM_L(0); |
| 670 | l1 = (int32_t)s->XMM_L(1); |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 671 | d->XMM_D(0) = int32_to_float64(l0, &env->sse_status); |
| 672 | d->XMM_D(1) = int32_to_float64(l1, &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 673 | } |
| 674 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 675 | void helper_cvtpi2ps(CPUX86State *env, XMMReg *d, MMXReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 676 | { |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 677 | d->XMM_S(0) = int32_to_float32(s->MMX_L(0), &env->sse_status); |
| 678 | d->XMM_S(1) = int32_to_float32(s->MMX_L(1), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 679 | } |
| 680 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 681 | void helper_cvtpi2pd(CPUX86State *env, XMMReg *d, MMXReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 682 | { |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 683 | d->XMM_D(0) = int32_to_float64(s->MMX_L(0), &env->sse_status); |
| 684 | d->XMM_D(1) = int32_to_float64(s->MMX_L(1), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 685 | } |
| 686 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 687 | void helper_cvtsi2ss(CPUX86State *env, XMMReg *d, uint32_t val) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 688 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 689 | d->XMM_S(0) = int32_to_float32(val, &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 690 | } |
| 691 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 692 | void helper_cvtsi2sd(CPUX86State *env, XMMReg *d, uint32_t val) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 693 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 694 | d->XMM_D(0) = int32_to_float64(val, &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 695 | } |
| 696 | |
| 697 | #ifdef TARGET_X86_64 |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 698 | void helper_cvtsq2ss(CPUX86State *env, XMMReg *d, uint64_t val) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 699 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 700 | d->XMM_S(0) = int64_to_float32(val, &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 701 | } |
| 702 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 703 | void helper_cvtsq2sd(CPUX86State *env, XMMReg *d, uint64_t val) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 704 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 705 | d->XMM_D(0) = int64_to_float64(val, &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 706 | } |
| 707 | #endif |
| 708 | |
| 709 | /* float to integer */ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 710 | void helper_cvtps2dq(CPUX86State *env, XMMReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 711 | { |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 712 | d->XMM_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status); |
| 713 | d->XMM_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status); |
| 714 | d->XMM_L(2) = float32_to_int32(s->XMM_S(2), &env->sse_status); |
| 715 | d->XMM_L(3) = float32_to_int32(s->XMM_S(3), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 716 | } |
| 717 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 718 | void helper_cvtpd2dq(CPUX86State *env, XMMReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 719 | { |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 720 | d->XMM_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status); |
| 721 | d->XMM_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 722 | d->XMM_Q(1) = 0; |
| 723 | } |
| 724 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 725 | void helper_cvtps2pi(CPUX86State *env, MMXReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 726 | { |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 727 | d->MMX_L(0) = float32_to_int32(s->XMM_S(0), &env->sse_status); |
| 728 | d->MMX_L(1) = float32_to_int32(s->XMM_S(1), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 729 | } |
| 730 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 731 | void helper_cvtpd2pi(CPUX86State *env, MMXReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 732 | { |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 733 | d->MMX_L(0) = float64_to_int32(s->XMM_D(0), &env->sse_status); |
| 734 | d->MMX_L(1) = float64_to_int32(s->XMM_D(1), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 735 | } |
| 736 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 737 | int32_t helper_cvtss2si(CPUX86State *env, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 738 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 739 | return float32_to_int32(s->XMM_S(0), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 740 | } |
| 741 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 742 | int32_t helper_cvtsd2si(CPUX86State *env, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 743 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 744 | return float64_to_int32(s->XMM_D(0), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 745 | } |
| 746 | |
| 747 | #ifdef TARGET_X86_64 |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 748 | int64_t helper_cvtss2sq(CPUX86State *env, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 749 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 750 | return float32_to_int64(s->XMM_S(0), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 751 | } |
| 752 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 753 | int64_t helper_cvtsd2sq(CPUX86State *env, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 754 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 755 | return float64_to_int64(s->XMM_D(0), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 756 | } |
| 757 | #endif |
| 758 | |
| 759 | /* float to integer truncated */ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 760 | void helper_cvttps2dq(CPUX86State *env, XMMReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 761 | { |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 762 | d->XMM_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); |
| 763 | d->XMM_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status); |
| 764 | d->XMM_L(2) = float32_to_int32_round_to_zero(s->XMM_S(2), &env->sse_status); |
| 765 | d->XMM_L(3) = float32_to_int32_round_to_zero(s->XMM_S(3), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 766 | } |
| 767 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 768 | void helper_cvttpd2dq(CPUX86State *env, XMMReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 769 | { |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 770 | d->XMM_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); |
| 771 | d->XMM_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 772 | d->XMM_Q(1) = 0; |
| 773 | } |
| 774 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 775 | void helper_cvttps2pi(CPUX86State *env, MMXReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 776 | { |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 777 | d->MMX_L(0) = float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); |
| 778 | d->MMX_L(1) = float32_to_int32_round_to_zero(s->XMM_S(1), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 779 | } |
| 780 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 781 | void helper_cvttpd2pi(CPUX86State *env, MMXReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 782 | { |
bellard | 7a0e1f4 | 2005-03-13 17:01:47 +0000 | [diff] [blame] | 783 | d->MMX_L(0) = float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); |
| 784 | d->MMX_L(1) = float64_to_int32_round_to_zero(s->XMM_D(1), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 785 | } |
| 786 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 787 | int32_t helper_cvttss2si(CPUX86State *env, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 788 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 789 | return float32_to_int32_round_to_zero(s->XMM_S(0), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 790 | } |
| 791 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 792 | int32_t helper_cvttsd2si(CPUX86State *env, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 793 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 794 | return float64_to_int32_round_to_zero(s->XMM_D(0), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 795 | } |
| 796 | |
| 797 | #ifdef TARGET_X86_64 |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 798 | int64_t helper_cvttss2sq(CPUX86State *env, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 799 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 800 | return float32_to_int64_round_to_zero(s->XMM_S(0), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 801 | } |
| 802 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 803 | int64_t helper_cvttsd2sq(CPUX86State *env, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 804 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 805 | return float64_to_int64_round_to_zero(s->XMM_D(0), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 806 | } |
| 807 | #endif |
| 808 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 809 | void helper_rsqrtps(CPUX86State *env, XMMReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 810 | { |
Aurelien Jarno | c2ef9a8 | 2011-04-20 13:04:23 +0200 | [diff] [blame] | 811 | d->XMM_S(0) = float32_div(float32_one, |
| 812 | float32_sqrt(s->XMM_S(0), &env->sse_status), |
| 813 | &env->sse_status); |
| 814 | d->XMM_S(1) = float32_div(float32_one, |
| 815 | float32_sqrt(s->XMM_S(1), &env->sse_status), |
| 816 | &env->sse_status); |
| 817 | d->XMM_S(2) = float32_div(float32_one, |
| 818 | float32_sqrt(s->XMM_S(2), &env->sse_status), |
| 819 | &env->sse_status); |
| 820 | d->XMM_S(3) = float32_div(float32_one, |
| 821 | float32_sqrt(s->XMM_S(3), &env->sse_status), |
| 822 | &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 823 | } |
| 824 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 825 | void helper_rsqrtss(CPUX86State *env, XMMReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 826 | { |
Aurelien Jarno | c2ef9a8 | 2011-04-20 13:04:23 +0200 | [diff] [blame] | 827 | d->XMM_S(0) = float32_div(float32_one, |
| 828 | float32_sqrt(s->XMM_S(0), &env->sse_status), |
| 829 | &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 830 | } |
| 831 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 832 | void helper_rcpps(CPUX86State *env, XMMReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 833 | { |
Aurelien Jarno | c2ef9a8 | 2011-04-20 13:04:23 +0200 | [diff] [blame] | 834 | d->XMM_S(0) = float32_div(float32_one, s->XMM_S(0), &env->sse_status); |
| 835 | d->XMM_S(1) = float32_div(float32_one, s->XMM_S(1), &env->sse_status); |
| 836 | d->XMM_S(2) = float32_div(float32_one, s->XMM_S(2), &env->sse_status); |
| 837 | d->XMM_S(3) = float32_div(float32_one, s->XMM_S(3), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 838 | } |
| 839 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 840 | void helper_rcpss(CPUX86State *env, XMMReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 841 | { |
Aurelien Jarno | c2ef9a8 | 2011-04-20 13:04:23 +0200 | [diff] [blame] | 842 | d->XMM_S(0) = float32_div(float32_one, s->XMM_S(0), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 843 | } |
| 844 | |
Andre Przywara | d9f4bb2 | 2009-09-19 00:30:48 +0200 | [diff] [blame] | 845 | static inline uint64_t helper_extrq(uint64_t src, int shift, int len) |
| 846 | { |
| 847 | uint64_t mask; |
| 848 | |
| 849 | if (len == 0) { |
| 850 | mask = ~0LL; |
| 851 | } else { |
| 852 | mask = (1ULL << len) - 1; |
| 853 | } |
| 854 | return (src >> shift) & mask; |
| 855 | } |
| 856 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 857 | void helper_extrq_r(CPUX86State *env, XMMReg *d, XMMReg *s) |
Andre Przywara | d9f4bb2 | 2009-09-19 00:30:48 +0200 | [diff] [blame] | 858 | { |
| 859 | d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), s->XMM_B(1), s->XMM_B(0)); |
| 860 | } |
| 861 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 862 | void helper_extrq_i(CPUX86State *env, XMMReg *d, int index, int length) |
Andre Przywara | d9f4bb2 | 2009-09-19 00:30:48 +0200 | [diff] [blame] | 863 | { |
| 864 | d->XMM_Q(0) = helper_extrq(d->XMM_Q(0), index, length); |
| 865 | } |
| 866 | |
| 867 | static inline uint64_t helper_insertq(uint64_t src, int shift, int len) |
| 868 | { |
| 869 | uint64_t mask; |
| 870 | |
| 871 | if (len == 0) { |
| 872 | mask = ~0ULL; |
| 873 | } else { |
| 874 | mask = (1ULL << len) - 1; |
| 875 | } |
| 876 | return (src & ~(mask << shift)) | ((src & mask) << shift); |
| 877 | } |
| 878 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 879 | void helper_insertq_r(CPUX86State *env, XMMReg *d, XMMReg *s) |
Andre Przywara | d9f4bb2 | 2009-09-19 00:30:48 +0200 | [diff] [blame] | 880 | { |
| 881 | d->XMM_Q(0) = helper_insertq(s->XMM_Q(0), s->XMM_B(9), s->XMM_B(8)); |
| 882 | } |
| 883 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 884 | void helper_insertq_i(CPUX86State *env, XMMReg *d, int index, int length) |
Andre Przywara | d9f4bb2 | 2009-09-19 00:30:48 +0200 | [diff] [blame] | 885 | { |
| 886 | d->XMM_Q(0) = helper_insertq(d->XMM_Q(0), index, length); |
| 887 | } |
| 888 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 889 | void helper_haddps(CPUX86State *env, XMMReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 890 | { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 891 | XMMReg r; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 892 | |
Max Reitz | 5c6562c | 2011-09-16 17:29:04 +0200 | [diff] [blame] | 893 | r.XMM_S(0) = float32_add(d->XMM_S(0), d->XMM_S(1), &env->sse_status); |
| 894 | r.XMM_S(1) = float32_add(d->XMM_S(2), d->XMM_S(3), &env->sse_status); |
| 895 | r.XMM_S(2) = float32_add(s->XMM_S(0), s->XMM_S(1), &env->sse_status); |
| 896 | r.XMM_S(3) = float32_add(s->XMM_S(2), s->XMM_S(3), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 897 | *d = r; |
| 898 | } |
| 899 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 900 | void helper_haddpd(CPUX86State *env, XMMReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 901 | { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 902 | XMMReg r; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 903 | |
Max Reitz | 5c6562c | 2011-09-16 17:29:04 +0200 | [diff] [blame] | 904 | r.XMM_D(0) = float64_add(d->XMM_D(0), d->XMM_D(1), &env->sse_status); |
| 905 | r.XMM_D(1) = float64_add(s->XMM_D(0), s->XMM_D(1), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 906 | *d = r; |
| 907 | } |
| 908 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 909 | void helper_hsubps(CPUX86State *env, XMMReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 910 | { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 911 | XMMReg r; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 912 | |
Max Reitz | 5c6562c | 2011-09-16 17:29:04 +0200 | [diff] [blame] | 913 | r.XMM_S(0) = float32_sub(d->XMM_S(0), d->XMM_S(1), &env->sse_status); |
| 914 | r.XMM_S(1) = float32_sub(d->XMM_S(2), d->XMM_S(3), &env->sse_status); |
| 915 | r.XMM_S(2) = float32_sub(s->XMM_S(0), s->XMM_S(1), &env->sse_status); |
| 916 | r.XMM_S(3) = float32_sub(s->XMM_S(2), s->XMM_S(3), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 917 | *d = r; |
| 918 | } |
| 919 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 920 | void helper_hsubpd(CPUX86State *env, XMMReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 921 | { |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 922 | XMMReg r; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 923 | |
Max Reitz | 5c6562c | 2011-09-16 17:29:04 +0200 | [diff] [blame] | 924 | r.XMM_D(0) = float64_sub(d->XMM_D(0), d->XMM_D(1), &env->sse_status); |
| 925 | r.XMM_D(1) = float64_sub(s->XMM_D(0), s->XMM_D(1), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 926 | *d = r; |
| 927 | } |
| 928 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 929 | void helper_addsubps(CPUX86State *env, XMMReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 930 | { |
Max Reitz | 5c6562c | 2011-09-16 17:29:04 +0200 | [diff] [blame] | 931 | d->XMM_S(0) = float32_sub(d->XMM_S(0), s->XMM_S(0), &env->sse_status); |
| 932 | d->XMM_S(1) = float32_add(d->XMM_S(1), s->XMM_S(1), &env->sse_status); |
| 933 | d->XMM_S(2) = float32_sub(d->XMM_S(2), s->XMM_S(2), &env->sse_status); |
| 934 | d->XMM_S(3) = float32_add(d->XMM_S(3), s->XMM_S(3), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 935 | } |
| 936 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 937 | void helper_addsubpd(CPUX86State *env, XMMReg *d, XMMReg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 938 | { |
Max Reitz | 5c6562c | 2011-09-16 17:29:04 +0200 | [diff] [blame] | 939 | d->XMM_D(0) = float64_sub(d->XMM_D(0), s->XMM_D(0), &env->sse_status); |
| 940 | d->XMM_D(1) = float64_add(d->XMM_D(1), s->XMM_D(1), &env->sse_status); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 941 | } |
| 942 | |
| 943 | /* XXX: unordered */ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 944 | #define SSE_HELPER_CMP(name, F) \ |
| 945 | void helper_ ## name ## ps(CPUX86State *env, Reg *d, Reg *s) \ |
| 946 | { \ |
| 947 | d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \ |
| 948 | d->XMM_L(1) = F(32, d->XMM_S(1), s->XMM_S(1)); \ |
| 949 | d->XMM_L(2) = F(32, d->XMM_S(2), s->XMM_S(2)); \ |
| 950 | d->XMM_L(3) = F(32, d->XMM_S(3), s->XMM_S(3)); \ |
| 951 | } \ |
| 952 | \ |
| 953 | void helper_ ## name ## ss(CPUX86State *env, Reg *d, Reg *s) \ |
| 954 | { \ |
| 955 | d->XMM_L(0) = F(32, d->XMM_S(0), s->XMM_S(0)); \ |
| 956 | } \ |
| 957 | \ |
| 958 | void helper_ ## name ## pd(CPUX86State *env, Reg *d, Reg *s) \ |
| 959 | { \ |
| 960 | d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \ |
| 961 | d->XMM_Q(1) = F(64, d->XMM_D(1), s->XMM_D(1)); \ |
| 962 | } \ |
| 963 | \ |
| 964 | void helper_ ## name ## sd(CPUX86State *env, Reg *d, Reg *s) \ |
| 965 | { \ |
| 966 | d->XMM_Q(0) = F(64, d->XMM_D(0), s->XMM_D(0)); \ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 967 | } |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 968 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 969 | #define FPU_CMPEQ(size, a, b) \ |
| 970 | (float ## size ## _eq_quiet(a, b, &env->sse_status) ? -1 : 0) |
| 971 | #define FPU_CMPLT(size, a, b) \ |
| 972 | (float ## size ## _lt(a, b, &env->sse_status) ? -1 : 0) |
| 973 | #define FPU_CMPLE(size, a, b) \ |
| 974 | (float ## size ## _le(a, b, &env->sse_status) ? -1 : 0) |
| 975 | #define FPU_CMPUNORD(size, a, b) \ |
| 976 | (float ## size ## _unordered_quiet(a, b, &env->sse_status) ? -1 : 0) |
| 977 | #define FPU_CMPNEQ(size, a, b) \ |
| 978 | (float ## size ## _eq_quiet(a, b, &env->sse_status) ? 0 : -1) |
| 979 | #define FPU_CMPNLT(size, a, b) \ |
| 980 | (float ## size ## _lt(a, b, &env->sse_status) ? 0 : -1) |
| 981 | #define FPU_CMPNLE(size, a, b) \ |
| 982 | (float ## size ## _le(a, b, &env->sse_status) ? 0 : -1) |
| 983 | #define FPU_CMPORD(size, a, b) \ |
| 984 | (float ## size ## _unordered_quiet(a, b, &env->sse_status) ? 0 : -1) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 985 | |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 986 | SSE_HELPER_CMP(cmpeq, FPU_CMPEQ) |
| 987 | SSE_HELPER_CMP(cmplt, FPU_CMPLT) |
| 988 | SSE_HELPER_CMP(cmple, FPU_CMPLE) |
| 989 | SSE_HELPER_CMP(cmpunord, FPU_CMPUNORD) |
| 990 | SSE_HELPER_CMP(cmpneq, FPU_CMPNEQ) |
| 991 | SSE_HELPER_CMP(cmpnlt, FPU_CMPNLT) |
| 992 | SSE_HELPER_CMP(cmpnle, FPU_CMPNLE) |
| 993 | SSE_HELPER_CMP(cmpord, FPU_CMPORD) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 994 | |
Blue Swirl | 1e6eec8 | 2009-09-05 10:14:07 +0000 | [diff] [blame] | 995 | static const int comis_eflags[4] = {CC_C, CC_Z, 0, CC_Z | CC_P | CC_C}; |
bellard | 43fb823 | 2005-04-26 20:38:17 +0000 | [diff] [blame] | 996 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 997 | void helper_ucomiss(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 998 | { |
bellard | 43fb823 | 2005-04-26 20:38:17 +0000 | [diff] [blame] | 999 | int ret; |
bellard | 8422b11 | 2005-03-20 10:39:24 +0000 | [diff] [blame] | 1000 | float32 s0, s1; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1001 | |
| 1002 | s0 = d->XMM_S(0); |
| 1003 | s1 = s->XMM_S(0); |
bellard | 43fb823 | 2005-04-26 20:38:17 +0000 | [diff] [blame] | 1004 | ret = float32_compare_quiet(s0, s1, &env->sse_status); |
| 1005 | CC_SRC = comis_eflags[ret + 1]; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1006 | } |
| 1007 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1008 | void helper_comiss(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1009 | { |
bellard | 43fb823 | 2005-04-26 20:38:17 +0000 | [diff] [blame] | 1010 | int ret; |
bellard | 8422b11 | 2005-03-20 10:39:24 +0000 | [diff] [blame] | 1011 | float32 s0, s1; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1012 | |
| 1013 | s0 = d->XMM_S(0); |
| 1014 | s1 = s->XMM_S(0); |
bellard | 43fb823 | 2005-04-26 20:38:17 +0000 | [diff] [blame] | 1015 | ret = float32_compare(s0, s1, &env->sse_status); |
| 1016 | CC_SRC = comis_eflags[ret + 1]; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1017 | } |
| 1018 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1019 | void helper_ucomisd(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1020 | { |
bellard | 43fb823 | 2005-04-26 20:38:17 +0000 | [diff] [blame] | 1021 | int ret; |
bellard | 8422b11 | 2005-03-20 10:39:24 +0000 | [diff] [blame] | 1022 | float64 d0, d1; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1023 | |
| 1024 | d0 = d->XMM_D(0); |
| 1025 | d1 = s->XMM_D(0); |
bellard | 43fb823 | 2005-04-26 20:38:17 +0000 | [diff] [blame] | 1026 | ret = float64_compare_quiet(d0, d1, &env->sse_status); |
| 1027 | CC_SRC = comis_eflags[ret + 1]; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1028 | } |
| 1029 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1030 | void helper_comisd(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1031 | { |
bellard | 43fb823 | 2005-04-26 20:38:17 +0000 | [diff] [blame] | 1032 | int ret; |
bellard | 8422b11 | 2005-03-20 10:39:24 +0000 | [diff] [blame] | 1033 | float64 d0, d1; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1034 | |
| 1035 | d0 = d->XMM_D(0); |
| 1036 | d1 = s->XMM_D(0); |
bellard | 43fb823 | 2005-04-26 20:38:17 +0000 | [diff] [blame] | 1037 | ret = float64_compare(d0, d1, &env->sse_status); |
| 1038 | CC_SRC = comis_eflags[ret + 1]; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1039 | } |
| 1040 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1041 | uint32_t helper_movmskps(CPUX86State *env, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1042 | { |
| 1043 | int b0, b1, b2, b3; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1044 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1045 | b0 = s->XMM_L(0) >> 31; |
| 1046 | b1 = s->XMM_L(1) >> 31; |
| 1047 | b2 = s->XMM_L(2) >> 31; |
| 1048 | b3 = s->XMM_L(3) >> 31; |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 1049 | return b0 | (b1 << 1) | (b2 << 2) | (b3 << 3); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1050 | } |
| 1051 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1052 | uint32_t helper_movmskpd(CPUX86State *env, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1053 | { |
| 1054 | int b0, b1; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1055 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1056 | b0 = s->XMM_L(1) >> 31; |
| 1057 | b1 = s->XMM_L(3) >> 31; |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 1058 | return b0 | (b1 << 1); |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1059 | } |
| 1060 | |
| 1061 | #endif |
| 1062 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1063 | uint32_t glue(helper_pmovmskb, SUFFIX)(CPUX86State *env, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1064 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 1065 | uint32_t val; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1066 | |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 1067 | val = 0; |
aurel32 | 30913ba | 2008-11-16 19:15:15 +0000 | [diff] [blame] | 1068 | val |= (s->B(0) >> 7); |
| 1069 | val |= (s->B(1) >> 6) & 0x02; |
| 1070 | val |= (s->B(2) >> 5) & 0x04; |
| 1071 | val |= (s->B(3) >> 4) & 0x08; |
| 1072 | val |= (s->B(4) >> 3) & 0x10; |
| 1073 | val |= (s->B(5) >> 2) & 0x20; |
| 1074 | val |= (s->B(6) >> 1) & 0x40; |
| 1075 | val |= (s->B(7)) & 0x80; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1076 | #if SHIFT == 1 |
aurel32 | 30913ba | 2008-11-16 19:15:15 +0000 | [diff] [blame] | 1077 | val |= (s->B(8) << 1) & 0x0100; |
| 1078 | val |= (s->B(9) << 2) & 0x0200; |
| 1079 | val |= (s->B(10) << 3) & 0x0400; |
| 1080 | val |= (s->B(11) << 4) & 0x0800; |
| 1081 | val |= (s->B(12) << 5) & 0x1000; |
| 1082 | val |= (s->B(13) << 6) & 0x2000; |
| 1083 | val |= (s->B(14) << 7) & 0x4000; |
| 1084 | val |= (s->B(15) << 8) & 0x8000; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1085 | #endif |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 1086 | return val; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1087 | } |
| 1088 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1089 | void glue(helper_packsswb, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1090 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 1091 | Reg r; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1092 | |
| 1093 | r.B(0) = satsb((int16_t)d->W(0)); |
| 1094 | r.B(1) = satsb((int16_t)d->W(1)); |
| 1095 | r.B(2) = satsb((int16_t)d->W(2)); |
| 1096 | r.B(3) = satsb((int16_t)d->W(3)); |
| 1097 | #if SHIFT == 1 |
| 1098 | r.B(4) = satsb((int16_t)d->W(4)); |
| 1099 | r.B(5) = satsb((int16_t)d->W(5)); |
| 1100 | r.B(6) = satsb((int16_t)d->W(6)); |
| 1101 | r.B(7) = satsb((int16_t)d->W(7)); |
| 1102 | #endif |
| 1103 | r.B((4 << SHIFT) + 0) = satsb((int16_t)s->W(0)); |
| 1104 | r.B((4 << SHIFT) + 1) = satsb((int16_t)s->W(1)); |
| 1105 | r.B((4 << SHIFT) + 2) = satsb((int16_t)s->W(2)); |
| 1106 | r.B((4 << SHIFT) + 3) = satsb((int16_t)s->W(3)); |
| 1107 | #if SHIFT == 1 |
| 1108 | r.B(12) = satsb((int16_t)s->W(4)); |
| 1109 | r.B(13) = satsb((int16_t)s->W(5)); |
| 1110 | r.B(14) = satsb((int16_t)s->W(6)); |
| 1111 | r.B(15) = satsb((int16_t)s->W(7)); |
| 1112 | #endif |
| 1113 | *d = r; |
| 1114 | } |
| 1115 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1116 | void glue(helper_packuswb, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1117 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 1118 | Reg r; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1119 | |
| 1120 | r.B(0) = satub((int16_t)d->W(0)); |
| 1121 | r.B(1) = satub((int16_t)d->W(1)); |
| 1122 | r.B(2) = satub((int16_t)d->W(2)); |
| 1123 | r.B(3) = satub((int16_t)d->W(3)); |
| 1124 | #if SHIFT == 1 |
| 1125 | r.B(4) = satub((int16_t)d->W(4)); |
| 1126 | r.B(5) = satub((int16_t)d->W(5)); |
| 1127 | r.B(6) = satub((int16_t)d->W(6)); |
| 1128 | r.B(7) = satub((int16_t)d->W(7)); |
| 1129 | #endif |
| 1130 | r.B((4 << SHIFT) + 0) = satub((int16_t)s->W(0)); |
| 1131 | r.B((4 << SHIFT) + 1) = satub((int16_t)s->W(1)); |
| 1132 | r.B((4 << SHIFT) + 2) = satub((int16_t)s->W(2)); |
| 1133 | r.B((4 << SHIFT) + 3) = satub((int16_t)s->W(3)); |
| 1134 | #if SHIFT == 1 |
| 1135 | r.B(12) = satub((int16_t)s->W(4)); |
| 1136 | r.B(13) = satub((int16_t)s->W(5)); |
| 1137 | r.B(14) = satub((int16_t)s->W(6)); |
| 1138 | r.B(15) = satub((int16_t)s->W(7)); |
| 1139 | #endif |
| 1140 | *d = r; |
| 1141 | } |
| 1142 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1143 | void glue(helper_packssdw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1144 | { |
bellard | 5af4518 | 2008-05-12 16:47:36 +0000 | [diff] [blame] | 1145 | Reg r; |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1146 | |
| 1147 | r.W(0) = satsw(d->L(0)); |
| 1148 | r.W(1) = satsw(d->L(1)); |
| 1149 | #if SHIFT == 1 |
| 1150 | r.W(2) = satsw(d->L(2)); |
| 1151 | r.W(3) = satsw(d->L(3)); |
| 1152 | #endif |
| 1153 | r.W((2 << SHIFT) + 0) = satsw(s->L(0)); |
| 1154 | r.W((2 << SHIFT) + 1) = satsw(s->L(1)); |
| 1155 | #if SHIFT == 1 |
| 1156 | r.W(6) = satsw(s->L(2)); |
| 1157 | r.W(7) = satsw(s->L(3)); |
| 1158 | #endif |
| 1159 | *d = r; |
| 1160 | } |
| 1161 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1162 | #define UNPCK_OP(base_name, base) \ |
| 1163 | \ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1164 | void glue(helper_punpck ## base_name ## bw, SUFFIX)(CPUX86State *env,\ |
| 1165 | Reg *d, Reg *s) \ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1166 | { \ |
| 1167 | Reg r; \ |
| 1168 | \ |
| 1169 | r.B(0) = d->B((base << (SHIFT + 2)) + 0); \ |
| 1170 | r.B(1) = s->B((base << (SHIFT + 2)) + 0); \ |
| 1171 | r.B(2) = d->B((base << (SHIFT + 2)) + 1); \ |
| 1172 | r.B(3) = s->B((base << (SHIFT + 2)) + 1); \ |
| 1173 | r.B(4) = d->B((base << (SHIFT + 2)) + 2); \ |
| 1174 | r.B(5) = s->B((base << (SHIFT + 2)) + 2); \ |
| 1175 | r.B(6) = d->B((base << (SHIFT + 2)) + 3); \ |
| 1176 | r.B(7) = s->B((base << (SHIFT + 2)) + 3); \ |
| 1177 | XMM_ONLY( \ |
| 1178 | r.B(8) = d->B((base << (SHIFT + 2)) + 4); \ |
| 1179 | r.B(9) = s->B((base << (SHIFT + 2)) + 4); \ |
| 1180 | r.B(10) = d->B((base << (SHIFT + 2)) + 5); \ |
| 1181 | r.B(11) = s->B((base << (SHIFT + 2)) + 5); \ |
| 1182 | r.B(12) = d->B((base << (SHIFT + 2)) + 6); \ |
| 1183 | r.B(13) = s->B((base << (SHIFT + 2)) + 6); \ |
| 1184 | r.B(14) = d->B((base << (SHIFT + 2)) + 7); \ |
| 1185 | r.B(15) = s->B((base << (SHIFT + 2)) + 7); \ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1186 | ) \ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1187 | *d = r; \ |
| 1188 | } \ |
| 1189 | \ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1190 | void glue(helper_punpck ## base_name ## wd, SUFFIX)(CPUX86State *env,\ |
| 1191 | Reg *d, Reg *s) \ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1192 | { \ |
| 1193 | Reg r; \ |
| 1194 | \ |
| 1195 | r.W(0) = d->W((base << (SHIFT + 1)) + 0); \ |
| 1196 | r.W(1) = s->W((base << (SHIFT + 1)) + 0); \ |
| 1197 | r.W(2) = d->W((base << (SHIFT + 1)) + 1); \ |
| 1198 | r.W(3) = s->W((base << (SHIFT + 1)) + 1); \ |
| 1199 | XMM_ONLY( \ |
| 1200 | r.W(4) = d->W((base << (SHIFT + 1)) + 2); \ |
| 1201 | r.W(5) = s->W((base << (SHIFT + 1)) + 2); \ |
| 1202 | r.W(6) = d->W((base << (SHIFT + 1)) + 3); \ |
| 1203 | r.W(7) = s->W((base << (SHIFT + 1)) + 3); \ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1204 | ) \ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1205 | *d = r; \ |
| 1206 | } \ |
| 1207 | \ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1208 | void glue(helper_punpck ## base_name ## dq, SUFFIX)(CPUX86State *env,\ |
| 1209 | Reg *d, Reg *s) \ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1210 | { \ |
| 1211 | Reg r; \ |
| 1212 | \ |
| 1213 | r.L(0) = d->L((base << SHIFT) + 0); \ |
| 1214 | r.L(1) = s->L((base << SHIFT) + 0); \ |
| 1215 | XMM_ONLY( \ |
| 1216 | r.L(2) = d->L((base << SHIFT) + 1); \ |
| 1217 | r.L(3) = s->L((base << SHIFT) + 1); \ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1218 | ) \ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1219 | *d = r; \ |
| 1220 | } \ |
| 1221 | \ |
| 1222 | XMM_ONLY( \ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1223 | void glue(helper_punpck ## base_name ## qdq, SUFFIX)(CPUX86State \ |
| 1224 | *env, \ |
| 1225 | Reg *d, \ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1226 | Reg *s) \ |
| 1227 | { \ |
| 1228 | Reg r; \ |
| 1229 | \ |
| 1230 | r.Q(0) = d->Q(base); \ |
| 1231 | r.Q(1) = s->Q(base); \ |
| 1232 | *d = r; \ |
| 1233 | } \ |
| 1234 | ) |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 1235 | |
| 1236 | UNPCK_OP(l, 0) |
| 1237 | UNPCK_OP(h, 1) |
| 1238 | |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1239 | /* 3DNow! float ops */ |
| 1240 | #if SHIFT == 0 |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1241 | void helper_pi2fd(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1242 | { |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1243 | d->MMX_S(0) = int32_to_float32(s->MMX_L(0), &env->mmx_status); |
| 1244 | d->MMX_S(1) = int32_to_float32(s->MMX_L(1), &env->mmx_status); |
| 1245 | } |
| 1246 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1247 | void helper_pi2fw(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1248 | { |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1249 | d->MMX_S(0) = int32_to_float32((int16_t)s->MMX_W(0), &env->mmx_status); |
| 1250 | d->MMX_S(1) = int32_to_float32((int16_t)s->MMX_W(2), &env->mmx_status); |
| 1251 | } |
| 1252 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1253 | void helper_pf2id(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1254 | { |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1255 | d->MMX_L(0) = float32_to_int32_round_to_zero(s->MMX_S(0), &env->mmx_status); |
| 1256 | d->MMX_L(1) = float32_to_int32_round_to_zero(s->MMX_S(1), &env->mmx_status); |
| 1257 | } |
| 1258 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1259 | void helper_pf2iw(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1260 | { |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1261 | d->MMX_L(0) = satsw(float32_to_int32_round_to_zero(s->MMX_S(0), |
| 1262 | &env->mmx_status)); |
| 1263 | d->MMX_L(1) = satsw(float32_to_int32_round_to_zero(s->MMX_S(1), |
| 1264 | &env->mmx_status)); |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1265 | } |
| 1266 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1267 | void helper_pfacc(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1268 | { |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1269 | MMXReg r; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1270 | |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1271 | r.MMX_S(0) = float32_add(d->MMX_S(0), d->MMX_S(1), &env->mmx_status); |
| 1272 | r.MMX_S(1) = float32_add(s->MMX_S(0), s->MMX_S(1), &env->mmx_status); |
| 1273 | *d = r; |
| 1274 | } |
| 1275 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1276 | void helper_pfadd(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1277 | { |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1278 | d->MMX_S(0) = float32_add(d->MMX_S(0), s->MMX_S(0), &env->mmx_status); |
| 1279 | d->MMX_S(1) = float32_add(d->MMX_S(1), s->MMX_S(1), &env->mmx_status); |
| 1280 | } |
| 1281 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1282 | void helper_pfcmpeq(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1283 | { |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1284 | d->MMX_L(0) = float32_eq_quiet(d->MMX_S(0), s->MMX_S(0), |
| 1285 | &env->mmx_status) ? -1 : 0; |
| 1286 | d->MMX_L(1) = float32_eq_quiet(d->MMX_S(1), s->MMX_S(1), |
| 1287 | &env->mmx_status) ? -1 : 0; |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1288 | } |
| 1289 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1290 | void helper_pfcmpge(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1291 | { |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1292 | d->MMX_L(0) = float32_le(s->MMX_S(0), d->MMX_S(0), |
| 1293 | &env->mmx_status) ? -1 : 0; |
| 1294 | d->MMX_L(1) = float32_le(s->MMX_S(1), d->MMX_S(1), |
| 1295 | &env->mmx_status) ? -1 : 0; |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1296 | } |
| 1297 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1298 | void helper_pfcmpgt(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1299 | { |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1300 | d->MMX_L(0) = float32_lt(s->MMX_S(0), d->MMX_S(0), |
| 1301 | &env->mmx_status) ? -1 : 0; |
| 1302 | d->MMX_L(1) = float32_lt(s->MMX_S(1), d->MMX_S(1), |
| 1303 | &env->mmx_status) ? -1 : 0; |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1304 | } |
| 1305 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1306 | void helper_pfmax(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1307 | { |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1308 | if (float32_lt(d->MMX_S(0), s->MMX_S(0), &env->mmx_status)) { |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1309 | d->MMX_S(0) = s->MMX_S(0); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1310 | } |
| 1311 | if (float32_lt(d->MMX_S(1), s->MMX_S(1), &env->mmx_status)) { |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1312 | d->MMX_S(1) = s->MMX_S(1); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1313 | } |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1314 | } |
| 1315 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1316 | void helper_pfmin(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1317 | { |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1318 | if (float32_lt(s->MMX_S(0), d->MMX_S(0), &env->mmx_status)) { |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1319 | d->MMX_S(0) = s->MMX_S(0); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1320 | } |
| 1321 | if (float32_lt(s->MMX_S(1), d->MMX_S(1), &env->mmx_status)) { |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1322 | d->MMX_S(1) = s->MMX_S(1); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1323 | } |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1324 | } |
| 1325 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1326 | void helper_pfmul(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1327 | { |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1328 | d->MMX_S(0) = float32_mul(d->MMX_S(0), s->MMX_S(0), &env->mmx_status); |
| 1329 | d->MMX_S(1) = float32_mul(d->MMX_S(1), s->MMX_S(1), &env->mmx_status); |
| 1330 | } |
| 1331 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1332 | void helper_pfnacc(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1333 | { |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1334 | MMXReg r; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1335 | |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1336 | r.MMX_S(0) = float32_sub(d->MMX_S(0), d->MMX_S(1), &env->mmx_status); |
| 1337 | r.MMX_S(1) = float32_sub(s->MMX_S(0), s->MMX_S(1), &env->mmx_status); |
| 1338 | *d = r; |
| 1339 | } |
| 1340 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1341 | void helper_pfpnacc(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1342 | { |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1343 | MMXReg r; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1344 | |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1345 | r.MMX_S(0) = float32_sub(d->MMX_S(0), d->MMX_S(1), &env->mmx_status); |
| 1346 | r.MMX_S(1) = float32_add(s->MMX_S(0), s->MMX_S(1), &env->mmx_status); |
| 1347 | *d = r; |
| 1348 | } |
| 1349 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1350 | void helper_pfrcp(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1351 | { |
Aurelien Jarno | c2ef9a8 | 2011-04-20 13:04:23 +0200 | [diff] [blame] | 1352 | d->MMX_S(0) = float32_div(float32_one, s->MMX_S(0), &env->mmx_status); |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1353 | d->MMX_S(1) = d->MMX_S(0); |
| 1354 | } |
| 1355 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1356 | void helper_pfrsqrt(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1357 | { |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1358 | d->MMX_L(1) = s->MMX_L(0) & 0x7fffffff; |
Aurelien Jarno | c2ef9a8 | 2011-04-20 13:04:23 +0200 | [diff] [blame] | 1359 | d->MMX_S(1) = float32_div(float32_one, |
| 1360 | float32_sqrt(d->MMX_S(1), &env->mmx_status), |
| 1361 | &env->mmx_status); |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1362 | d->MMX_L(1) |= s->MMX_L(0) & 0x80000000; |
| 1363 | d->MMX_L(0) = d->MMX_L(1); |
| 1364 | } |
| 1365 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1366 | void helper_pfsub(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1367 | { |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1368 | d->MMX_S(0) = float32_sub(d->MMX_S(0), s->MMX_S(0), &env->mmx_status); |
| 1369 | d->MMX_S(1) = float32_sub(d->MMX_S(1), s->MMX_S(1), &env->mmx_status); |
| 1370 | } |
| 1371 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1372 | void helper_pfsubr(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1373 | { |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1374 | d->MMX_S(0) = float32_sub(s->MMX_S(0), d->MMX_S(0), &env->mmx_status); |
| 1375 | d->MMX_S(1) = float32_sub(s->MMX_S(1), d->MMX_S(1), &env->mmx_status); |
| 1376 | } |
| 1377 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1378 | void helper_pswapd(CPUX86State *env, MMXReg *d, MMXReg *s) |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1379 | { |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1380 | MMXReg r; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1381 | |
aurel32 | a35f3ec | 2008-04-08 19:51:29 +0000 | [diff] [blame] | 1382 | r.MMX_L(0) = s->MMX_L(1); |
| 1383 | r.MMX_L(1) = s->MMX_L(0); |
| 1384 | *d = r; |
| 1385 | } |
| 1386 | #endif |
| 1387 | |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1388 | /* SSSE3 op helpers */ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1389 | void glue(helper_pshufb, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1390 | { |
| 1391 | int i; |
| 1392 | Reg r; |
| 1393 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1394 | for (i = 0; i < (8 << SHIFT); i++) { |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1395 | r.B(i) = (s->B(i) & 0x80) ? 0 : (d->B(s->B(i) & ((8 << SHIFT) - 1))); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1396 | } |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1397 | |
| 1398 | *d = r; |
| 1399 | } |
| 1400 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1401 | void glue(helper_phaddw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1402 | { |
| 1403 | d->W(0) = (int16_t)d->W(0) + (int16_t)d->W(1); |
| 1404 | d->W(1) = (int16_t)d->W(2) + (int16_t)d->W(3); |
| 1405 | XMM_ONLY(d->W(2) = (int16_t)d->W(4) + (int16_t)d->W(5)); |
| 1406 | XMM_ONLY(d->W(3) = (int16_t)d->W(6) + (int16_t)d->W(7)); |
| 1407 | d->W((2 << SHIFT) + 0) = (int16_t)s->W(0) + (int16_t)s->W(1); |
| 1408 | d->W((2 << SHIFT) + 1) = (int16_t)s->W(2) + (int16_t)s->W(3); |
| 1409 | XMM_ONLY(d->W(6) = (int16_t)s->W(4) + (int16_t)s->W(5)); |
| 1410 | XMM_ONLY(d->W(7) = (int16_t)s->W(6) + (int16_t)s->W(7)); |
| 1411 | } |
| 1412 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1413 | void glue(helper_phaddd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1414 | { |
| 1415 | d->L(0) = (int32_t)d->L(0) + (int32_t)d->L(1); |
| 1416 | XMM_ONLY(d->L(1) = (int32_t)d->L(2) + (int32_t)d->L(3)); |
| 1417 | d->L((1 << SHIFT) + 0) = (int32_t)s->L(0) + (int32_t)s->L(1); |
| 1418 | XMM_ONLY(d->L(3) = (int32_t)s->L(2) + (int32_t)s->L(3)); |
| 1419 | } |
| 1420 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1421 | void glue(helper_phaddsw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1422 | { |
| 1423 | d->W(0) = satsw((int16_t)d->W(0) + (int16_t)d->W(1)); |
| 1424 | d->W(1) = satsw((int16_t)d->W(2) + (int16_t)d->W(3)); |
| 1425 | XMM_ONLY(d->W(2) = satsw((int16_t)d->W(4) + (int16_t)d->W(5))); |
| 1426 | XMM_ONLY(d->W(3) = satsw((int16_t)d->W(6) + (int16_t)d->W(7))); |
| 1427 | d->W((2 << SHIFT) + 0) = satsw((int16_t)s->W(0) + (int16_t)s->W(1)); |
| 1428 | d->W((2 << SHIFT) + 1) = satsw((int16_t)s->W(2) + (int16_t)s->W(3)); |
| 1429 | XMM_ONLY(d->W(6) = satsw((int16_t)s->W(4) + (int16_t)s->W(5))); |
| 1430 | XMM_ONLY(d->W(7) = satsw((int16_t)s->W(6) + (int16_t)s->W(7))); |
| 1431 | } |
| 1432 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1433 | void glue(helper_pmaddubsw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1434 | { |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1435 | d->W(0) = satsw((int8_t)s->B(0) * (uint8_t)d->B(0) + |
| 1436 | (int8_t)s->B(1) * (uint8_t)d->B(1)); |
| 1437 | d->W(1) = satsw((int8_t)s->B(2) * (uint8_t)d->B(2) + |
| 1438 | (int8_t)s->B(3) * (uint8_t)d->B(3)); |
| 1439 | d->W(2) = satsw((int8_t)s->B(4) * (uint8_t)d->B(4) + |
| 1440 | (int8_t)s->B(5) * (uint8_t)d->B(5)); |
| 1441 | d->W(3) = satsw((int8_t)s->B(6) * (uint8_t)d->B(6) + |
| 1442 | (int8_t)s->B(7) * (uint8_t)d->B(7)); |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1443 | #if SHIFT == 1 |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1444 | d->W(4) = satsw((int8_t)s->B(8) * (uint8_t)d->B(8) + |
| 1445 | (int8_t)s->B(9) * (uint8_t)d->B(9)); |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1446 | d->W(5) = satsw((int8_t)s->B(10) * (uint8_t)d->B(10) + |
| 1447 | (int8_t)s->B(11) * (uint8_t)d->B(11)); |
| 1448 | d->W(6) = satsw((int8_t)s->B(12) * (uint8_t)d->B(12) + |
| 1449 | (int8_t)s->B(13) * (uint8_t)d->B(13)); |
| 1450 | d->W(7) = satsw((int8_t)s->B(14) * (uint8_t)d->B(14) + |
| 1451 | (int8_t)s->B(15) * (uint8_t)d->B(15)); |
| 1452 | #endif |
| 1453 | } |
| 1454 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1455 | void glue(helper_phsubw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1456 | { |
| 1457 | d->W(0) = (int16_t)d->W(0) - (int16_t)d->W(1); |
| 1458 | d->W(1) = (int16_t)d->W(2) - (int16_t)d->W(3); |
| 1459 | XMM_ONLY(d->W(2) = (int16_t)d->W(4) - (int16_t)d->W(5)); |
| 1460 | XMM_ONLY(d->W(3) = (int16_t)d->W(6) - (int16_t)d->W(7)); |
| 1461 | d->W((2 << SHIFT) + 0) = (int16_t)s->W(0) - (int16_t)s->W(1); |
| 1462 | d->W((2 << SHIFT) + 1) = (int16_t)s->W(2) - (int16_t)s->W(3); |
| 1463 | XMM_ONLY(d->W(6) = (int16_t)s->W(4) - (int16_t)s->W(5)); |
| 1464 | XMM_ONLY(d->W(7) = (int16_t)s->W(6) - (int16_t)s->W(7)); |
| 1465 | } |
| 1466 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1467 | void glue(helper_phsubd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1468 | { |
| 1469 | d->L(0) = (int32_t)d->L(0) - (int32_t)d->L(1); |
| 1470 | XMM_ONLY(d->L(1) = (int32_t)d->L(2) - (int32_t)d->L(3)); |
| 1471 | d->L((1 << SHIFT) + 0) = (int32_t)s->L(0) - (int32_t)s->L(1); |
| 1472 | XMM_ONLY(d->L(3) = (int32_t)s->L(2) - (int32_t)s->L(3)); |
| 1473 | } |
| 1474 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1475 | void glue(helper_phsubsw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1476 | { |
| 1477 | d->W(0) = satsw((int16_t)d->W(0) - (int16_t)d->W(1)); |
| 1478 | d->W(1) = satsw((int16_t)d->W(2) - (int16_t)d->W(3)); |
| 1479 | XMM_ONLY(d->W(2) = satsw((int16_t)d->W(4) - (int16_t)d->W(5))); |
| 1480 | XMM_ONLY(d->W(3) = satsw((int16_t)d->W(6) - (int16_t)d->W(7))); |
| 1481 | d->W((2 << SHIFT) + 0) = satsw((int16_t)s->W(0) - (int16_t)s->W(1)); |
| 1482 | d->W((2 << SHIFT) + 1) = satsw((int16_t)s->W(2) - (int16_t)s->W(3)); |
| 1483 | XMM_ONLY(d->W(6) = satsw((int16_t)s->W(4) - (int16_t)s->W(5))); |
| 1484 | XMM_ONLY(d->W(7) = satsw((int16_t)s->W(6) - (int16_t)s->W(7))); |
| 1485 | } |
| 1486 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1487 | #define FABSB(_, x) (x > INT8_MAX ? -(int8_t)x : x) |
| 1488 | #define FABSW(_, x) (x > INT16_MAX ? -(int16_t)x : x) |
| 1489 | #define FABSL(_, x) (x > INT32_MAX ? -(int32_t)x : x) |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1490 | SSE_HELPER_B(helper_pabsb, FABSB) |
| 1491 | SSE_HELPER_W(helper_pabsw, FABSW) |
| 1492 | SSE_HELPER_L(helper_pabsd, FABSL) |
| 1493 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1494 | #define FMULHRSW(d, s) (((int16_t) d * (int16_t)s + 0x4000) >> 15) |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1495 | SSE_HELPER_W(helper_pmulhrsw, FMULHRSW) |
| 1496 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1497 | #define FSIGNB(d, s) (s <= INT8_MAX ? s ? d : 0 : -(int8_t)d) |
| 1498 | #define FSIGNW(d, s) (s <= INT16_MAX ? s ? d : 0 : -(int16_t)d) |
| 1499 | #define FSIGNL(d, s) (s <= INT32_MAX ? s ? d : 0 : -(int32_t)d) |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1500 | SSE_HELPER_B(helper_psignb, FSIGNB) |
| 1501 | SSE_HELPER_W(helper_psignw, FSIGNW) |
| 1502 | SSE_HELPER_L(helper_psignd, FSIGNL) |
| 1503 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1504 | void glue(helper_palignr, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, |
| 1505 | int32_t shift) |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1506 | { |
| 1507 | Reg r; |
| 1508 | |
| 1509 | /* XXX could be checked during translation */ |
| 1510 | if (shift >= (16 << SHIFT)) { |
| 1511 | r.Q(0) = 0; |
| 1512 | XMM_ONLY(r.Q(1) = 0); |
| 1513 | } else { |
| 1514 | shift <<= 3; |
| 1515 | #define SHR(v, i) (i < 64 && i > -64 ? i > 0 ? v >> (i) : (v << -(i)) : 0) |
| 1516 | #if SHIFT == 0 |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1517 | r.Q(0) = SHR(s->Q(0), shift - 0) | |
| 1518 | SHR(d->Q(0), shift - 64); |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1519 | #else |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1520 | r.Q(0) = SHR(s->Q(0), shift - 0) | |
| 1521 | SHR(s->Q(1), shift - 64) | |
| 1522 | SHR(d->Q(0), shift - 128) | |
| 1523 | SHR(d->Q(1), shift - 192); |
| 1524 | r.Q(1) = SHR(s->Q(0), shift + 64) | |
| 1525 | SHR(s->Q(1), shift - 0) | |
| 1526 | SHR(d->Q(0), shift - 64) | |
| 1527 | SHR(d->Q(1), shift - 128); |
balrog | 4242b1b | 2008-09-25 18:01:46 +0000 | [diff] [blame] | 1528 | #endif |
| 1529 | #undef SHR |
| 1530 | } |
| 1531 | |
| 1532 | *d = r; |
| 1533 | } |
| 1534 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1535 | #define XMM0 (env->xmm_regs[0]) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1536 | |
| 1537 | #if SHIFT == 1 |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1538 | #define SSE_HELPER_V(name, elem, num, F) \ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1539 | void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1540 | { \ |
| 1541 | d->elem(0) = F(d->elem(0), s->elem(0), XMM0.elem(0)); \ |
| 1542 | d->elem(1) = F(d->elem(1), s->elem(1), XMM0.elem(1)); \ |
| 1543 | if (num > 2) { \ |
| 1544 | d->elem(2) = F(d->elem(2), s->elem(2), XMM0.elem(2)); \ |
| 1545 | d->elem(3) = F(d->elem(3), s->elem(3), XMM0.elem(3)); \ |
| 1546 | if (num > 4) { \ |
| 1547 | d->elem(4) = F(d->elem(4), s->elem(4), XMM0.elem(4)); \ |
| 1548 | d->elem(5) = F(d->elem(5), s->elem(5), XMM0.elem(5)); \ |
| 1549 | d->elem(6) = F(d->elem(6), s->elem(6), XMM0.elem(6)); \ |
| 1550 | d->elem(7) = F(d->elem(7), s->elem(7), XMM0.elem(7)); \ |
| 1551 | if (num > 8) { \ |
| 1552 | d->elem(8) = F(d->elem(8), s->elem(8), XMM0.elem(8)); \ |
| 1553 | d->elem(9) = F(d->elem(9), s->elem(9), XMM0.elem(9)); \ |
| 1554 | d->elem(10) = F(d->elem(10), s->elem(10), XMM0.elem(10)); \ |
| 1555 | d->elem(11) = F(d->elem(11), s->elem(11), XMM0.elem(11)); \ |
| 1556 | d->elem(12) = F(d->elem(12), s->elem(12), XMM0.elem(12)); \ |
| 1557 | d->elem(13) = F(d->elem(13), s->elem(13), XMM0.elem(13)); \ |
| 1558 | d->elem(14) = F(d->elem(14), s->elem(14), XMM0.elem(14)); \ |
| 1559 | d->elem(15) = F(d->elem(15), s->elem(15), XMM0.elem(15)); \ |
| 1560 | } \ |
| 1561 | } \ |
| 1562 | } \ |
| 1563 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1564 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1565 | #define SSE_HELPER_I(name, elem, num, F) \ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1566 | void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t imm) \ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1567 | { \ |
| 1568 | d->elem(0) = F(d->elem(0), s->elem(0), ((imm >> 0) & 1)); \ |
| 1569 | d->elem(1) = F(d->elem(1), s->elem(1), ((imm >> 1) & 1)); \ |
| 1570 | if (num > 2) { \ |
| 1571 | d->elem(2) = F(d->elem(2), s->elem(2), ((imm >> 2) & 1)); \ |
| 1572 | d->elem(3) = F(d->elem(3), s->elem(3), ((imm >> 3) & 1)); \ |
| 1573 | if (num > 4) { \ |
| 1574 | d->elem(4) = F(d->elem(4), s->elem(4), ((imm >> 4) & 1)); \ |
| 1575 | d->elem(5) = F(d->elem(5), s->elem(5), ((imm >> 5) & 1)); \ |
| 1576 | d->elem(6) = F(d->elem(6), s->elem(6), ((imm >> 6) & 1)); \ |
| 1577 | d->elem(7) = F(d->elem(7), s->elem(7), ((imm >> 7) & 1)); \ |
| 1578 | if (num > 8) { \ |
| 1579 | d->elem(8) = F(d->elem(8), s->elem(8), ((imm >> 8) & 1)); \ |
| 1580 | d->elem(9) = F(d->elem(9), s->elem(9), ((imm >> 9) & 1)); \ |
| 1581 | d->elem(10) = F(d->elem(10), s->elem(10), \ |
| 1582 | ((imm >> 10) & 1)); \ |
| 1583 | d->elem(11) = F(d->elem(11), s->elem(11), \ |
| 1584 | ((imm >> 11) & 1)); \ |
| 1585 | d->elem(12) = F(d->elem(12), s->elem(12), \ |
| 1586 | ((imm >> 12) & 1)); \ |
| 1587 | d->elem(13) = F(d->elem(13), s->elem(13), \ |
| 1588 | ((imm >> 13) & 1)); \ |
| 1589 | d->elem(14) = F(d->elem(14), s->elem(14), \ |
| 1590 | ((imm >> 14) & 1)); \ |
| 1591 | d->elem(15) = F(d->elem(15), s->elem(15), \ |
| 1592 | ((imm >> 15) & 1)); \ |
| 1593 | } \ |
| 1594 | } \ |
| 1595 | } \ |
| 1596 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1597 | |
| 1598 | /* SSE4.1 op helpers */ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1599 | #define FBLENDVB(d, s, m) ((m & 0x80) ? s : d) |
| 1600 | #define FBLENDVPS(d, s, m) ((m & 0x80000000) ? s : d) |
| 1601 | #define FBLENDVPD(d, s, m) ((m & 0x8000000000000000LL) ? s : d) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1602 | SSE_HELPER_V(helper_pblendvb, B, 16, FBLENDVB) |
| 1603 | SSE_HELPER_V(helper_blendvps, L, 4, FBLENDVPS) |
| 1604 | SSE_HELPER_V(helper_blendvpd, Q, 2, FBLENDVPD) |
| 1605 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1606 | void glue(helper_ptest, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1607 | { |
| 1608 | uint64_t zf = (s->Q(0) & d->Q(0)) | (s->Q(1) & d->Q(1)); |
| 1609 | uint64_t cf = (s->Q(0) & ~d->Q(0)) | (s->Q(1) & ~d->Q(1)); |
| 1610 | |
| 1611 | CC_SRC = (zf ? 0 : CC_Z) | (cf ? 0 : CC_C); |
| 1612 | } |
| 1613 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1614 | #define SSE_HELPER_F(name, elem, num, F) \ |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1615 | void glue(name, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) \ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1616 | { \ |
| 1617 | d->elem(0) = F(0); \ |
| 1618 | d->elem(1) = F(1); \ |
| 1619 | if (num > 2) { \ |
| 1620 | d->elem(2) = F(2); \ |
| 1621 | d->elem(3) = F(3); \ |
| 1622 | if (num > 4) { \ |
| 1623 | d->elem(4) = F(4); \ |
| 1624 | d->elem(5) = F(5); \ |
| 1625 | d->elem(6) = F(6); \ |
| 1626 | d->elem(7) = F(7); \ |
| 1627 | } \ |
| 1628 | } \ |
| 1629 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1630 | |
| 1631 | SSE_HELPER_F(helper_pmovsxbw, W, 8, (int8_t) s->B) |
| 1632 | SSE_HELPER_F(helper_pmovsxbd, L, 4, (int8_t) s->B) |
| 1633 | SSE_HELPER_F(helper_pmovsxbq, Q, 2, (int8_t) s->B) |
| 1634 | SSE_HELPER_F(helper_pmovsxwd, L, 4, (int16_t) s->W) |
| 1635 | SSE_HELPER_F(helper_pmovsxwq, Q, 2, (int16_t) s->W) |
| 1636 | SSE_HELPER_F(helper_pmovsxdq, Q, 2, (int32_t) s->L) |
| 1637 | SSE_HELPER_F(helper_pmovzxbw, W, 8, s->B) |
| 1638 | SSE_HELPER_F(helper_pmovzxbd, L, 4, s->B) |
| 1639 | SSE_HELPER_F(helper_pmovzxbq, Q, 2, s->B) |
| 1640 | SSE_HELPER_F(helper_pmovzxwd, L, 4, s->W) |
| 1641 | SSE_HELPER_F(helper_pmovzxwq, Q, 2, s->W) |
| 1642 | SSE_HELPER_F(helper_pmovzxdq, Q, 2, s->L) |
| 1643 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1644 | void glue(helper_pmuldq, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1645 | { |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1646 | d->Q(0) = (int64_t)(int32_t) d->L(0) * (int32_t) s->L(0); |
| 1647 | d->Q(1) = (int64_t)(int32_t) d->L(2) * (int32_t) s->L(2); |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1648 | } |
| 1649 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1650 | #define FCMPEQQ(d, s) (d == s ? -1 : 0) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1651 | SSE_HELPER_Q(helper_pcmpeqq, FCMPEQQ) |
| 1652 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1653 | void glue(helper_packusdw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1654 | { |
| 1655 | d->W(0) = satuw((int32_t) d->L(0)); |
| 1656 | d->W(1) = satuw((int32_t) d->L(1)); |
| 1657 | d->W(2) = satuw((int32_t) d->L(2)); |
| 1658 | d->W(3) = satuw((int32_t) d->L(3)); |
| 1659 | d->W(4) = satuw((int32_t) s->L(0)); |
| 1660 | d->W(5) = satuw((int32_t) s->L(1)); |
| 1661 | d->W(6) = satuw((int32_t) s->L(2)); |
| 1662 | d->W(7) = satuw((int32_t) s->L(3)); |
| 1663 | } |
| 1664 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1665 | #define FMINSB(d, s) MIN((int8_t)d, (int8_t)s) |
| 1666 | #define FMINSD(d, s) MIN((int32_t)d, (int32_t)s) |
| 1667 | #define FMAXSB(d, s) MAX((int8_t)d, (int8_t)s) |
| 1668 | #define FMAXSD(d, s) MAX((int32_t)d, (int32_t)s) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1669 | SSE_HELPER_B(helper_pminsb, FMINSB) |
| 1670 | SSE_HELPER_L(helper_pminsd, FMINSD) |
| 1671 | SSE_HELPER_W(helper_pminuw, MIN) |
| 1672 | SSE_HELPER_L(helper_pminud, MIN) |
| 1673 | SSE_HELPER_B(helper_pmaxsb, FMAXSB) |
| 1674 | SSE_HELPER_L(helper_pmaxsd, FMAXSD) |
| 1675 | SSE_HELPER_W(helper_pmaxuw, MAX) |
| 1676 | SSE_HELPER_L(helper_pmaxud, MAX) |
| 1677 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1678 | #define FMULLD(d, s) ((int32_t)d * (int32_t)s) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1679 | SSE_HELPER_L(helper_pmulld, FMULLD) |
| 1680 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1681 | void glue(helper_phminposuw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1682 | { |
| 1683 | int idx = 0; |
| 1684 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1685 | if (s->W(1) < s->W(idx)) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1686 | idx = 1; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1687 | } |
| 1688 | if (s->W(2) < s->W(idx)) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1689 | idx = 2; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1690 | } |
| 1691 | if (s->W(3) < s->W(idx)) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1692 | idx = 3; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1693 | } |
| 1694 | if (s->W(4) < s->W(idx)) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1695 | idx = 4; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1696 | } |
| 1697 | if (s->W(5) < s->W(idx)) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1698 | idx = 5; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1699 | } |
| 1700 | if (s->W(6) < s->W(idx)) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1701 | idx = 6; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1702 | } |
| 1703 | if (s->W(7) < s->W(idx)) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1704 | idx = 7; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1705 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1706 | |
| 1707 | d->Q(1) = 0; |
| 1708 | d->L(1) = 0; |
| 1709 | d->W(1) = idx; |
| 1710 | d->W(0) = s->W(idx); |
| 1711 | } |
| 1712 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1713 | void glue(helper_roundps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, |
| 1714 | uint32_t mode) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1715 | { |
| 1716 | signed char prev_rounding_mode; |
| 1717 | |
| 1718 | prev_rounding_mode = env->sse_status.float_rounding_mode; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1719 | if (!(mode & (1 << 2))) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1720 | switch (mode & 3) { |
| 1721 | case 0: |
| 1722 | set_float_rounding_mode(float_round_nearest_even, &env->sse_status); |
| 1723 | break; |
| 1724 | case 1: |
| 1725 | set_float_rounding_mode(float_round_down, &env->sse_status); |
| 1726 | break; |
| 1727 | case 2: |
| 1728 | set_float_rounding_mode(float_round_up, &env->sse_status); |
| 1729 | break; |
| 1730 | case 3: |
| 1731 | set_float_rounding_mode(float_round_to_zero, &env->sse_status); |
| 1732 | break; |
| 1733 | } |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1734 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1735 | |
Aurelien Jarno | adc7166 | 2012-01-07 15:20:11 +0100 | [diff] [blame] | 1736 | d->XMM_S(0) = float32_round_to_int(s->XMM_S(0), &env->sse_status); |
| 1737 | d->XMM_S(1) = float32_round_to_int(s->XMM_S(1), &env->sse_status); |
| 1738 | d->XMM_S(2) = float32_round_to_int(s->XMM_S(2), &env->sse_status); |
| 1739 | d->XMM_S(3) = float32_round_to_int(s->XMM_S(3), &env->sse_status); |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1740 | |
| 1741 | #if 0 /* TODO */ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1742 | if (mode & (1 << 3)) { |
| 1743 | set_float_exception_flags(get_float_exception_flags(&env->sse_status) & |
| 1744 | ~float_flag_inexact, |
| 1745 | &env->sse_status); |
| 1746 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1747 | #endif |
| 1748 | env->sse_status.float_rounding_mode = prev_rounding_mode; |
| 1749 | } |
| 1750 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1751 | void glue(helper_roundpd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, |
| 1752 | uint32_t mode) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1753 | { |
| 1754 | signed char prev_rounding_mode; |
| 1755 | |
| 1756 | prev_rounding_mode = env->sse_status.float_rounding_mode; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1757 | if (!(mode & (1 << 2))) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1758 | switch (mode & 3) { |
| 1759 | case 0: |
| 1760 | set_float_rounding_mode(float_round_nearest_even, &env->sse_status); |
| 1761 | break; |
| 1762 | case 1: |
| 1763 | set_float_rounding_mode(float_round_down, &env->sse_status); |
| 1764 | break; |
| 1765 | case 2: |
| 1766 | set_float_rounding_mode(float_round_up, &env->sse_status); |
| 1767 | break; |
| 1768 | case 3: |
| 1769 | set_float_rounding_mode(float_round_to_zero, &env->sse_status); |
| 1770 | break; |
| 1771 | } |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1772 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1773 | |
Aurelien Jarno | adc7166 | 2012-01-07 15:20:11 +0100 | [diff] [blame] | 1774 | d->XMM_D(0) = float64_round_to_int(s->XMM_D(0), &env->sse_status); |
| 1775 | d->XMM_D(1) = float64_round_to_int(s->XMM_D(1), &env->sse_status); |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1776 | |
| 1777 | #if 0 /* TODO */ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1778 | if (mode & (1 << 3)) { |
| 1779 | set_float_exception_flags(get_float_exception_flags(&env->sse_status) & |
| 1780 | ~float_flag_inexact, |
| 1781 | &env->sse_status); |
| 1782 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1783 | #endif |
| 1784 | env->sse_status.float_rounding_mode = prev_rounding_mode; |
| 1785 | } |
| 1786 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1787 | void glue(helper_roundss, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, |
| 1788 | uint32_t mode) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1789 | { |
| 1790 | signed char prev_rounding_mode; |
| 1791 | |
| 1792 | prev_rounding_mode = env->sse_status.float_rounding_mode; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1793 | if (!(mode & (1 << 2))) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1794 | switch (mode & 3) { |
| 1795 | case 0: |
| 1796 | set_float_rounding_mode(float_round_nearest_even, &env->sse_status); |
| 1797 | break; |
| 1798 | case 1: |
| 1799 | set_float_rounding_mode(float_round_down, &env->sse_status); |
| 1800 | break; |
| 1801 | case 2: |
| 1802 | set_float_rounding_mode(float_round_up, &env->sse_status); |
| 1803 | break; |
| 1804 | case 3: |
| 1805 | set_float_rounding_mode(float_round_to_zero, &env->sse_status); |
| 1806 | break; |
| 1807 | } |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1808 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1809 | |
Aurelien Jarno | adc7166 | 2012-01-07 15:20:11 +0100 | [diff] [blame] | 1810 | d->XMM_S(0) = float32_round_to_int(s->XMM_S(0), &env->sse_status); |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1811 | |
| 1812 | #if 0 /* TODO */ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1813 | if (mode & (1 << 3)) { |
| 1814 | set_float_exception_flags(get_float_exception_flags(&env->sse_status) & |
| 1815 | ~float_flag_inexact, |
| 1816 | &env->sse_status); |
| 1817 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1818 | #endif |
| 1819 | env->sse_status.float_rounding_mode = prev_rounding_mode; |
| 1820 | } |
| 1821 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1822 | void glue(helper_roundsd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, |
| 1823 | uint32_t mode) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1824 | { |
| 1825 | signed char prev_rounding_mode; |
| 1826 | |
| 1827 | prev_rounding_mode = env->sse_status.float_rounding_mode; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1828 | if (!(mode & (1 << 2))) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1829 | switch (mode & 3) { |
| 1830 | case 0: |
| 1831 | set_float_rounding_mode(float_round_nearest_even, &env->sse_status); |
| 1832 | break; |
| 1833 | case 1: |
| 1834 | set_float_rounding_mode(float_round_down, &env->sse_status); |
| 1835 | break; |
| 1836 | case 2: |
| 1837 | set_float_rounding_mode(float_round_up, &env->sse_status); |
| 1838 | break; |
| 1839 | case 3: |
| 1840 | set_float_rounding_mode(float_round_to_zero, &env->sse_status); |
| 1841 | break; |
| 1842 | } |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1843 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1844 | |
Aurelien Jarno | adc7166 | 2012-01-07 15:20:11 +0100 | [diff] [blame] | 1845 | d->XMM_D(0) = float64_round_to_int(s->XMM_D(0), &env->sse_status); |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1846 | |
| 1847 | #if 0 /* TODO */ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1848 | if (mode & (1 << 3)) { |
| 1849 | set_float_exception_flags(get_float_exception_flags(&env->sse_status) & |
| 1850 | ~float_flag_inexact, |
| 1851 | &env->sse_status); |
| 1852 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1853 | #endif |
| 1854 | env->sse_status.float_rounding_mode = prev_rounding_mode; |
| 1855 | } |
| 1856 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1857 | #define FBLENDP(d, s, m) (m ? s : d) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1858 | SSE_HELPER_I(helper_blendps, L, 4, FBLENDP) |
| 1859 | SSE_HELPER_I(helper_blendpd, Q, 2, FBLENDP) |
| 1860 | SSE_HELPER_I(helper_pblendw, W, 8, FBLENDP) |
| 1861 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1862 | void glue(helper_dpps, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mask) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1863 | { |
Aurelien Jarno | 170d5b4 | 2012-01-07 15:20:12 +0100 | [diff] [blame] | 1864 | float32 iresult = float32_zero; |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1865 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1866 | if (mask & (1 << 4)) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1867 | iresult = float32_add(iresult, |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1868 | float32_mul(d->XMM_S(0), s->XMM_S(0), |
| 1869 | &env->sse_status), |
| 1870 | &env->sse_status); |
| 1871 | } |
| 1872 | if (mask & (1 << 5)) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1873 | iresult = float32_add(iresult, |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1874 | float32_mul(d->XMM_S(1), s->XMM_S(1), |
| 1875 | &env->sse_status), |
| 1876 | &env->sse_status); |
| 1877 | } |
| 1878 | if (mask & (1 << 6)) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1879 | iresult = float32_add(iresult, |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1880 | float32_mul(d->XMM_S(2), s->XMM_S(2), |
| 1881 | &env->sse_status), |
| 1882 | &env->sse_status); |
| 1883 | } |
| 1884 | if (mask & (1 << 7)) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1885 | iresult = float32_add(iresult, |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1886 | float32_mul(d->XMM_S(3), s->XMM_S(3), |
| 1887 | &env->sse_status), |
| 1888 | &env->sse_status); |
| 1889 | } |
Aurelien Jarno | 170d5b4 | 2012-01-07 15:20:12 +0100 | [diff] [blame] | 1890 | d->XMM_S(0) = (mask & (1 << 0)) ? iresult : float32_zero; |
| 1891 | d->XMM_S(1) = (mask & (1 << 1)) ? iresult : float32_zero; |
| 1892 | d->XMM_S(2) = (mask & (1 << 2)) ? iresult : float32_zero; |
| 1893 | d->XMM_S(3) = (mask & (1 << 3)) ? iresult : float32_zero; |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1894 | } |
| 1895 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1896 | void glue(helper_dppd, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, uint32_t mask) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1897 | { |
Aurelien Jarno | 170d5b4 | 2012-01-07 15:20:12 +0100 | [diff] [blame] | 1898 | float64 iresult = float64_zero; |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1899 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1900 | if (mask & (1 << 4)) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1901 | iresult = float64_add(iresult, |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1902 | float64_mul(d->XMM_D(0), s->XMM_D(0), |
| 1903 | &env->sse_status), |
| 1904 | &env->sse_status); |
| 1905 | } |
| 1906 | if (mask & (1 << 5)) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1907 | iresult = float64_add(iresult, |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1908 | float64_mul(d->XMM_D(1), s->XMM_D(1), |
| 1909 | &env->sse_status), |
| 1910 | &env->sse_status); |
| 1911 | } |
Aurelien Jarno | 170d5b4 | 2012-01-07 15:20:12 +0100 | [diff] [blame] | 1912 | d->XMM_D(0) = (mask & (1 << 0)) ? iresult : float64_zero; |
| 1913 | d->XMM_D(1) = (mask & (1 << 1)) ? iresult : float64_zero; |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1914 | } |
| 1915 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1916 | void glue(helper_mpsadbw, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, |
| 1917 | uint32_t offset) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1918 | { |
| 1919 | int s0 = (offset & 3) << 2; |
| 1920 | int d0 = (offset & 4) << 0; |
| 1921 | int i; |
| 1922 | Reg r; |
| 1923 | |
| 1924 | for (i = 0; i < 8; i++, d0++) { |
| 1925 | r.W(i) = 0; |
| 1926 | r.W(i) += abs1(d->B(d0 + 0) - s->B(s0 + 0)); |
| 1927 | r.W(i) += abs1(d->B(d0 + 1) - s->B(s0 + 1)); |
| 1928 | r.W(i) += abs1(d->B(d0 + 2) - s->B(s0 + 2)); |
| 1929 | r.W(i) += abs1(d->B(d0 + 3) - s->B(s0 + 3)); |
| 1930 | } |
| 1931 | |
| 1932 | *d = r; |
| 1933 | } |
| 1934 | |
| 1935 | /* SSE4.2 op helpers */ |
| 1936 | /* it's unclear whether signed or unsigned */ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1937 | #define FCMPGTQ(d, s) (d > s ? -1 : 0) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1938 | SSE_HELPER_Q(helper_pcmpgtq, FCMPGTQ) |
| 1939 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1940 | static inline int pcmp_elen(CPUX86State *env, int reg, uint32_t ctrl) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1941 | { |
| 1942 | int val; |
| 1943 | |
| 1944 | /* Presence of REX.W is indicated by a bit higher than 7 set */ |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1945 | if (ctrl >> 8) { |
| 1946 | val = abs1((int64_t)env->regs[reg]); |
| 1947 | } else { |
| 1948 | val = abs1((int32_t)env->regs[reg]); |
| 1949 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1950 | |
| 1951 | if (ctrl & 1) { |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1952 | if (val > 8) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1953 | return 8; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1954 | } |
| 1955 | } else { |
| 1956 | if (val > 16) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1957 | return 16; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1958 | } |
| 1959 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1960 | return val; |
| 1961 | } |
| 1962 | |
| 1963 | static inline int pcmp_ilen(Reg *r, uint8_t ctrl) |
| 1964 | { |
| 1965 | int val = 0; |
| 1966 | |
| 1967 | if (ctrl & 1) { |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1968 | while (val < 8 && r->W(val)) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1969 | val++; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1970 | } |
| 1971 | } else { |
| 1972 | while (val < 16 && r->B(val)) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1973 | val++; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1974 | } |
| 1975 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1976 | |
| 1977 | return val; |
| 1978 | } |
| 1979 | |
| 1980 | static inline int pcmp_val(Reg *r, uint8_t ctrl, int i) |
| 1981 | { |
| 1982 | switch ((ctrl >> 0) & 3) { |
| 1983 | case 0: |
| 1984 | return r->B(i); |
| 1985 | case 1: |
| 1986 | return r->W(i); |
| 1987 | case 2: |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1988 | return (int8_t)r->B(i); |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1989 | case 3: |
| 1990 | default: |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1991 | return (int16_t)r->W(i); |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1992 | } |
| 1993 | } |
| 1994 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 1995 | static inline unsigned pcmpxstrx(CPUX86State *env, Reg *d, Reg *s, |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 1996 | int8_t ctrl, int valids, int validd) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 1997 | { |
| 1998 | unsigned int res = 0; |
| 1999 | int v; |
| 2000 | int j, i; |
| 2001 | int upper = (ctrl & 1) ? 7 : 15; |
| 2002 | |
| 2003 | valids--; |
| 2004 | validd--; |
| 2005 | |
| 2006 | CC_SRC = (valids < upper ? CC_Z : 0) | (validd < upper ? CC_S : 0); |
| 2007 | |
| 2008 | switch ((ctrl >> 2) & 3) { |
| 2009 | case 0: |
| 2010 | for (j = valids; j >= 0; j--) { |
| 2011 | res <<= 1; |
| 2012 | v = pcmp_val(s, ctrl, j); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2013 | for (i = validd; i >= 0; i--) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2014 | res |= (v == pcmp_val(d, ctrl, i)); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2015 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2016 | } |
| 2017 | break; |
| 2018 | case 1: |
| 2019 | for (j = valids; j >= 0; j--) { |
| 2020 | res <<= 1; |
| 2021 | v = pcmp_val(s, ctrl, j); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2022 | for (i = ((validd - 1) | 1); i >= 0; i -= 2) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2023 | res |= (pcmp_val(d, ctrl, i - 0) <= v && |
| 2024 | pcmp_val(d, ctrl, i - 1) >= v); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2025 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2026 | } |
| 2027 | break; |
| 2028 | case 2: |
| 2029 | res = (2 << (upper - MAX(valids, validd))) - 1; |
| 2030 | res <<= MAX(valids, validd) - MIN(valids, validd); |
| 2031 | for (i = MIN(valids, validd); i >= 0; i--) { |
| 2032 | res <<= 1; |
| 2033 | v = pcmp_val(s, ctrl, i); |
| 2034 | res |= (v == pcmp_val(d, ctrl, i)); |
| 2035 | } |
| 2036 | break; |
| 2037 | case 3: |
| 2038 | for (j = valids - validd; j >= 0; j--) { |
| 2039 | res <<= 1; |
| 2040 | res |= 1; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2041 | for (i = MIN(upper - j, validd); i >= 0; i--) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2042 | res &= (pcmp_val(s, ctrl, i + j) == pcmp_val(d, ctrl, i)); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2043 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2044 | } |
| 2045 | break; |
| 2046 | } |
| 2047 | |
| 2048 | switch ((ctrl >> 4) & 3) { |
| 2049 | case 1: |
| 2050 | res ^= (2 << upper) - 1; |
| 2051 | break; |
| 2052 | case 3: |
| 2053 | res ^= (2 << valids) - 1; |
| 2054 | break; |
| 2055 | } |
| 2056 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2057 | if (res) { |
| 2058 | CC_SRC |= CC_C; |
| 2059 | } |
| 2060 | if (res & 1) { |
| 2061 | CC_SRC |= CC_O; |
| 2062 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2063 | |
| 2064 | return res; |
| 2065 | } |
| 2066 | |
| 2067 | static inline int rffs1(unsigned int val) |
| 2068 | { |
| 2069 | int ret = 1, hi; |
| 2070 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2071 | for (hi = sizeof(val) * 4; hi; hi /= 2) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2072 | if (val >> hi) { |
| 2073 | val >>= hi; |
| 2074 | ret += hi; |
| 2075 | } |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2076 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2077 | |
| 2078 | return ret; |
| 2079 | } |
| 2080 | |
| 2081 | static inline int ffs1(unsigned int val) |
| 2082 | { |
| 2083 | int ret = 1, hi; |
| 2084 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2085 | for (hi = sizeof(val) * 4; hi; hi /= 2) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2086 | if (val << hi) { |
| 2087 | val <<= hi; |
| 2088 | ret += hi; |
| 2089 | } |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2090 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2091 | |
| 2092 | return ret; |
| 2093 | } |
| 2094 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 2095 | void glue(helper_pcmpestri, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, |
| 2096 | uint32_t ctrl) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2097 | { |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 2098 | unsigned int res = pcmpxstrx(env, d, s, ctrl, |
| 2099 | pcmp_elen(env, R_EDX, ctrl), |
| 2100 | pcmp_elen(env, R_EAX, ctrl)); |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2101 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2102 | if (res) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2103 | env->regs[R_ECX] = ((ctrl & (1 << 6)) ? rffs1 : ffs1)(res) - 1; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2104 | } else { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2105 | env->regs[R_ECX] = 16 >> (ctrl & (1 << 0)); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2106 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2107 | } |
| 2108 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 2109 | void glue(helper_pcmpestrm, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, |
| 2110 | uint32_t ctrl) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2111 | { |
| 2112 | int i; |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 2113 | unsigned int res = pcmpxstrx(env, d, s, ctrl, |
| 2114 | pcmp_elen(env, R_EDX, ctrl), |
| 2115 | pcmp_elen(env, R_EAX, ctrl)); |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2116 | |
| 2117 | if ((ctrl >> 6) & 1) { |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2118 | if (ctrl & 1) { |
Blue Swirl | bc42689 | 2011-11-13 11:11:52 +0000 | [diff] [blame] | 2119 | for (i = 0; i < 8; i++, res >>= 1) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2120 | d->W(i) = (res & 1) ? ~0 : 0; |
Blue Swirl | bc42689 | 2011-11-13 11:11:52 +0000 | [diff] [blame] | 2121 | } |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2122 | } else { |
Blue Swirl | bc42689 | 2011-11-13 11:11:52 +0000 | [diff] [blame] | 2123 | for (i = 0; i < 16; i++, res >>= 1) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2124 | d->B(i) = (res & 1) ? ~0 : 0; |
Blue Swirl | bc42689 | 2011-11-13 11:11:52 +0000 | [diff] [blame] | 2125 | } |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2126 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2127 | } else { |
| 2128 | d->Q(1) = 0; |
| 2129 | d->Q(0) = res; |
| 2130 | } |
| 2131 | } |
| 2132 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 2133 | void glue(helper_pcmpistri, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, |
| 2134 | uint32_t ctrl) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2135 | { |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 2136 | unsigned int res = pcmpxstrx(env, d, s, ctrl, |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2137 | pcmp_ilen(s, ctrl), |
| 2138 | pcmp_ilen(d, ctrl)); |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2139 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2140 | if (res) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2141 | env->regs[R_ECX] = ((ctrl & (1 << 6)) ? rffs1 : ffs1)(res) - 1; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2142 | } else { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2143 | env->regs[R_ECX] = 16 >> (ctrl & (1 << 0)); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2144 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2145 | } |
| 2146 | |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 2147 | void glue(helper_pcmpistrm, SUFFIX)(CPUX86State *env, Reg *d, Reg *s, |
| 2148 | uint32_t ctrl) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2149 | { |
| 2150 | int i; |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 2151 | unsigned int res = pcmpxstrx(env, d, s, ctrl, |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2152 | pcmp_ilen(s, ctrl), |
| 2153 | pcmp_ilen(d, ctrl)); |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2154 | |
| 2155 | if ((ctrl >> 6) & 1) { |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2156 | if (ctrl & 1) { |
Blue Swirl | bc42689 | 2011-11-13 11:11:52 +0000 | [diff] [blame] | 2157 | for (i = 0; i < 8; i++, res >>= 1) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2158 | d->W(i) = (res & 1) ? ~0 : 0; |
Blue Swirl | bc42689 | 2011-11-13 11:11:52 +0000 | [diff] [blame] | 2159 | } |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2160 | } else { |
Blue Swirl | bc42689 | 2011-11-13 11:11:52 +0000 | [diff] [blame] | 2161 | for (i = 0; i < 16; i++, res >>= 1) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2162 | d->B(i) = (res & 1) ? ~0 : 0; |
Blue Swirl | bc42689 | 2011-11-13 11:11:52 +0000 | [diff] [blame] | 2163 | } |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2164 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2165 | } else { |
| 2166 | d->Q(1) = 0; |
| 2167 | d->Q(0) = res; |
| 2168 | } |
| 2169 | } |
| 2170 | |
| 2171 | #define CRCPOLY 0x1edc6f41 |
| 2172 | #define CRCPOLY_BITREV 0x82f63b78 |
| 2173 | target_ulong helper_crc32(uint32_t crc1, target_ulong msg, uint32_t len) |
| 2174 | { |
| 2175 | target_ulong crc = (msg & ((target_ulong) -1 >> |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2176 | (TARGET_LONG_BITS - len))) ^ crc1; |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2177 | |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2178 | while (len--) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2179 | crc = (crc >> 1) ^ ((crc & 1) ? CRCPOLY_BITREV : 0); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2180 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2181 | |
| 2182 | return crc; |
| 2183 | } |
| 2184 | |
| 2185 | #define POPMASK(i) ((target_ulong) -1 / ((1LL << (1 << i)) + 1)) |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2186 | #define POPCOUNT(n, i) ((n & POPMASK(i)) + ((n >> (1 << i)) & POPMASK(i))) |
Blue Swirl | d3eb5ea | 2012-04-28 21:28:09 +0000 | [diff] [blame] | 2187 | target_ulong helper_popcnt(CPUX86State *env, target_ulong n, uint32_t type) |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2188 | { |
| 2189 | CC_SRC = n ? 0 : CC_Z; |
| 2190 | |
| 2191 | n = POPCOUNT(n, 0); |
| 2192 | n = POPCOUNT(n, 1); |
| 2193 | n = POPCOUNT(n, 2); |
| 2194 | n = POPCOUNT(n, 3); |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2195 | if (type == 1) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2196 | return n & 0xff; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2197 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2198 | |
| 2199 | n = POPCOUNT(n, 4); |
| 2200 | #ifndef TARGET_X86_64 |
| 2201 | return n; |
| 2202 | #else |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2203 | if (type == 2) { |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2204 | return n & 0xff; |
Blue Swirl | e01d9d3 | 2012-04-29 08:54:44 +0000 | [diff] [blame] | 2205 | } |
balrog | 222a333 | 2008-10-04 03:27:44 +0000 | [diff] [blame] | 2206 | |
| 2207 | return POPCOUNT(n, 5); |
| 2208 | #endif |
| 2209 | } |
| 2210 | #endif |
| 2211 | |
bellard | 664e0f1 | 2005-01-08 18:58:29 +0000 | [diff] [blame] | 2212 | #undef SHIFT |
| 2213 | #undef XMM_ONLY |
| 2214 | #undef Reg |
| 2215 | #undef B |
| 2216 | #undef W |
| 2217 | #undef L |
| 2218 | #undef Q |
| 2219 | #undef SUFFIX |