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Alexander Graf10ec5112009-12-05 12:44:21 +01001/*
2 * S/390 helpers
3 *
4 * Copyright (c) 2009 Ulrich Hecht
Alexander Grafd5a43962011-03-23 10:58:07 +01005 * Copyright (c) 2011 Alexander Graf
Alexander Graf10ec5112009-12-05 12:44:21 +01006 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
Blue Swirl70539e12010-03-07 15:48:43 +000018 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
Alexander Graf10ec5112009-12-05 12:44:21 +010019 */
20
Alexander Graf10ec5112009-12-05 12:44:21 +010021#include "cpu.h"
Paolo Bonzini022c62c2012-12-17 18:19:49 +010022#include "exec/gdbstub.h"
Paolo Bonzini1de7afc2012-12-17 18:20:00 +010023#include "qemu/timer.h"
Alexander Grafef815222011-10-07 09:51:50 +020024#ifndef CONFIG_USER_ONLY
Paolo Bonzini9c17d612012-12-17 18:20:04 +010025#include "sysemu/sysemu.h"
Alexander Grafef815222011-10-07 09:51:50 +020026#endif
Alexander Graf10ec5112009-12-05 12:44:21 +010027
Alexander Grafd5a43962011-03-23 10:58:07 +010028//#define DEBUG_S390
29//#define DEBUG_S390_PTE
30//#define DEBUG_S390_STDOUT
31
32#ifdef DEBUG_S390
33#ifdef DEBUG_S390_STDOUT
34#define DPRINTF(fmt, ...) \
35 do { fprintf(stderr, fmt, ## __VA_ARGS__); \
36 qemu_log(fmt, ##__VA_ARGS__); } while (0)
37#else
38#define DPRINTF(fmt, ...) \
39 do { qemu_log(fmt, ## __VA_ARGS__); } while (0)
40#endif
41#else
42#define DPRINTF(fmt, ...) \
43 do { } while (0)
44#endif
45
46#ifdef DEBUG_S390_PTE
47#define PTE_DPRINTF DPRINTF
48#else
49#define PTE_DPRINTF(fmt, ...) \
50 do { } while (0)
51#endif
52
53#ifndef CONFIG_USER_ONLY
Andreas Färber8f22e0d2012-04-02 13:56:29 +020054void s390x_tod_timer(void *opaque)
Alexander Grafd5a43962011-03-23 10:58:07 +010055{
Andreas Färberb8ba6792012-04-02 14:00:43 +020056 S390CPU *cpu = opaque;
57 CPUS390XState *env = &cpu->env;
Alexander Grafd5a43962011-03-23 10:58:07 +010058
59 env->pending_int |= INTERRUPT_TOD;
Andreas Färberc3affe52013-01-18 15:03:43 +010060 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
Alexander Grafd5a43962011-03-23 10:58:07 +010061}
62
Andreas Färber8f22e0d2012-04-02 13:56:29 +020063void s390x_cpu_timer(void *opaque)
Alexander Grafd5a43962011-03-23 10:58:07 +010064{
Andreas Färberb8ba6792012-04-02 14:00:43 +020065 S390CPU *cpu = opaque;
66 CPUS390XState *env = &cpu->env;
Alexander Grafd5a43962011-03-23 10:58:07 +010067
68 env->pending_int |= INTERRUPT_CPUTIMER;
Andreas Färberc3affe52013-01-18 15:03:43 +010069 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
Alexander Grafd5a43962011-03-23 10:58:07 +010070}
71#endif
Alexander Graf10c339a2009-12-05 12:44:26 +010072
Andreas Färber564b8632012-05-03 04:13:04 +020073S390CPU *cpu_s390x_init(const char *cpu_model)
Alexander Graf10ec5112009-12-05 12:44:21 +010074{
Andreas Färber29e4bcb2012-04-02 11:39:23 +020075 S390CPU *cpu;
Alexander Graf10ec5112009-12-05 12:44:21 +010076
Andreas Färber29e4bcb2012-04-02 11:39:23 +020077 cpu = S390_CPU(object_new(TYPE_S390_CPU));
Andreas Färber1f136632013-01-16 04:00:41 +010078
79 object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
80
Andreas Färber564b8632012-05-03 04:13:04 +020081 return cpu;
Alexander Graf10ec5112009-12-05 12:44:21 +010082}
83
Alexander Grafd5a43962011-03-23 10:58:07 +010084#if defined(CONFIG_USER_ONLY)
85
Andreas Färber97a8ea52013-02-02 10:57:51 +010086void s390_cpu_do_interrupt(CPUState *cs)
Alexander Grafd5a43962011-03-23 10:58:07 +010087{
Andreas Färber27103422013-08-26 08:31:06 +020088 cs->exception_index = -1;
Alexander Grafd5a43962011-03-23 10:58:07 +010089}
90
Andreas Färber75104542013-08-26 03:01:33 +020091int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
92 int rw, int mmu_idx)
Alexander Grafd5a43962011-03-23 10:58:07 +010093{
Andreas Färber75104542013-08-26 03:01:33 +020094 S390CPU *cpu = S390_CPU(cs);
95
Andreas Färber27103422013-08-26 08:31:06 +020096 cs->exception_index = EXCP_PGM;
Andreas Färber75104542013-08-26 03:01:33 +020097 cpu->env.int_pgm_code = PGM_ADDRESSING;
Richard Hendersond5a103c2012-09-14 19:31:57 -070098 /* On real machines this value is dropped into LowMem. Since this
99 is userland, simply put this someplace that cpu_loop can find it. */
Andreas Färber75104542013-08-26 03:01:33 +0200100 cpu->env.__excp_addr = address;
Alexander Grafd5a43962011-03-23 10:58:07 +0100101 return 1;
102}
103
Andreas Färberb7e516c2012-05-05 15:43:31 +0200104#else /* !CONFIG_USER_ONLY */
Alexander Graf10c339a2009-12-05 12:44:26 +0100105
Alexander Grafd5a43962011-03-23 10:58:07 +0100106/* Ensure to exit the TB after this call! */
Blue Swirl71e47082012-09-02 07:33:30 +0000107static void trigger_pgm_exception(CPUS390XState *env, uint32_t code,
Richard Hendersond5a103c2012-09-14 19:31:57 -0700108 uint32_t ilen)
Alexander Graf10c339a2009-12-05 12:44:26 +0100109{
Andreas Färber27103422013-08-26 08:31:06 +0200110 CPUState *cs = CPU(s390_env_get_cpu(env));
111
112 cs->exception_index = EXCP_PGM;
Alexander Grafd5a43962011-03-23 10:58:07 +0100113 env->int_pgm_code = code;
Richard Hendersond5a103c2012-09-14 19:31:57 -0700114 env->int_pgm_ilen = ilen;
Alexander Grafd5a43962011-03-23 10:58:07 +0100115}
Alexander Graf10c339a2009-12-05 12:44:26 +0100116
Andreas Färbera4e3ad12012-03-14 01:38:22 +0100117static int trans_bits(CPUS390XState *env, uint64_t mode)
Alexander Grafd5a43962011-03-23 10:58:07 +0100118{
Andreas Färbera47dddd2013-09-03 17:38:47 +0200119 S390CPU *cpu = s390_env_get_cpu(env);
Alexander Grafd5a43962011-03-23 10:58:07 +0100120 int bits = 0;
Alexander Graf10c339a2009-12-05 12:44:26 +0100121
Alexander Grafd5a43962011-03-23 10:58:07 +0100122 switch (mode) {
123 case PSW_ASC_PRIMARY:
124 bits = 1;
125 break;
126 case PSW_ASC_SECONDARY:
127 bits = 2;
128 break;
129 case PSW_ASC_HOME:
130 bits = 3;
131 break;
132 default:
Andreas Färbera47dddd2013-09-03 17:38:47 +0200133 cpu_abort(CPU(cpu), "unknown asc mode\n");
Alexander Grafd5a43962011-03-23 10:58:07 +0100134 break;
135 }
Alexander Graf10c339a2009-12-05 12:44:26 +0100136
Alexander Grafd5a43962011-03-23 10:58:07 +0100137 return bits;
138}
139
Blue Swirl71e47082012-09-02 07:33:30 +0000140static void trigger_prot_fault(CPUS390XState *env, target_ulong vaddr,
141 uint64_t mode)
Alexander Grafd5a43962011-03-23 10:58:07 +0100142{
Andreas Färber2efc6be2014-03-09 19:40:08 +0100143 CPUState *cs = CPU(s390_env_get_cpu(env));
Richard Hendersond5a103c2012-09-14 19:31:57 -0700144 int ilen = ILEN_LATER_INC;
Alexander Grafd5a43962011-03-23 10:58:07 +0100145 int bits = trans_bits(env, mode) | 4;
146
Blue Swirl71e47082012-09-02 07:33:30 +0000147 DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
Alexander Grafd5a43962011-03-23 10:58:07 +0100148
Edgar E. Iglesiasf6066042013-11-28 00:11:44 +0100149 stq_phys(cs->as,
150 env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
Richard Hendersond5a103c2012-09-14 19:31:57 -0700151 trigger_pgm_exception(env, PGM_PROTECTION, ilen);
Alexander Grafd5a43962011-03-23 10:58:07 +0100152}
153
Blue Swirl71e47082012-09-02 07:33:30 +0000154static void trigger_page_fault(CPUS390XState *env, target_ulong vaddr,
155 uint32_t type, uint64_t asc, int rw)
Alexander Grafd5a43962011-03-23 10:58:07 +0100156{
Andreas Färber2efc6be2014-03-09 19:40:08 +0100157 CPUState *cs = CPU(s390_env_get_cpu(env));
Richard Hendersond5a103c2012-09-14 19:31:57 -0700158 int ilen = ILEN_LATER;
Alexander Grafd5a43962011-03-23 10:58:07 +0100159 int bits = trans_bits(env, asc);
160
Richard Hendersond5a103c2012-09-14 19:31:57 -0700161 /* Code accesses have an undefined ilc. */
Alexander Grafd5a43962011-03-23 10:58:07 +0100162 if (rw == 2) {
Richard Hendersond5a103c2012-09-14 19:31:57 -0700163 ilen = 2;
Alexander Grafd5a43962011-03-23 10:58:07 +0100164 }
165
Blue Swirl71e47082012-09-02 07:33:30 +0000166 DPRINTF("%s: vaddr=%016" PRIx64 " bits=%d\n", __func__, vaddr, bits);
Alexander Grafd5a43962011-03-23 10:58:07 +0100167
Edgar E. Iglesiasf6066042013-11-28 00:11:44 +0100168 stq_phys(cs->as,
169 env->psa + offsetof(LowCore, trans_exc_code), vaddr | bits);
Richard Hendersond5a103c2012-09-14 19:31:57 -0700170 trigger_pgm_exception(env, type, ilen);
Alexander Grafd5a43962011-03-23 10:58:07 +0100171}
172
Blue Swirl71e47082012-09-02 07:33:30 +0000173static int mmu_translate_asce(CPUS390XState *env, target_ulong vaddr,
174 uint64_t asc, uint64_t asce, int level,
175 target_ulong *raddr, int *flags, int rw)
Alexander Grafd5a43962011-03-23 10:58:07 +0100176{
Andreas Färber2efc6be2014-03-09 19:40:08 +0100177 CPUState *cs = CPU(s390_env_get_cpu(env));
Alexander Grafd5a43962011-03-23 10:58:07 +0100178 uint64_t offs = 0;
179 uint64_t origin;
180 uint64_t new_asce;
181
Blue Swirl71e47082012-09-02 07:33:30 +0000182 PTE_DPRINTF("%s: 0x%" PRIx64 "\n", __func__, asce);
Alexander Grafd5a43962011-03-23 10:58:07 +0100183
184 if (((level != _ASCE_TYPE_SEGMENT) && (asce & _REGION_ENTRY_INV)) ||
185 ((level == _ASCE_TYPE_SEGMENT) && (asce & _SEGMENT_ENTRY_INV))) {
186 /* XXX different regions have different faults */
Blue Swirl71e47082012-09-02 07:33:30 +0000187 DPRINTF("%s: invalid region\n", __func__);
Alexander Grafd5a43962011-03-23 10:58:07 +0100188 trigger_page_fault(env, vaddr, PGM_SEGMENT_TRANS, asc, rw);
189 return -1;
190 }
191
192 if ((level <= _ASCE_TYPE_MASK) && ((asce & _ASCE_TYPE_MASK) != level)) {
193 trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
194 return -1;
195 }
196
197 if (asce & _ASCE_REAL_SPACE) {
198 /* direct mapping */
199
200 *raddr = vaddr;
201 return 0;
202 }
203
204 origin = asce & _ASCE_ORIGIN;
205
206 switch (level) {
207 case _ASCE_TYPE_REGION1 + 4:
208 offs = (vaddr >> 50) & 0x3ff8;
209 break;
210 case _ASCE_TYPE_REGION1:
211 offs = (vaddr >> 39) & 0x3ff8;
212 break;
213 case _ASCE_TYPE_REGION2:
214 offs = (vaddr >> 28) & 0x3ff8;
215 break;
216 case _ASCE_TYPE_REGION3:
217 offs = (vaddr >> 17) & 0x3ff8;
218 break;
219 case _ASCE_TYPE_SEGMENT:
220 offs = (vaddr >> 9) & 0x07f8;
221 origin = asce & _SEGMENT_ENTRY_ORIGIN;
222 break;
223 }
224
225 /* XXX region protection flags */
226 /* *flags &= ~PAGE_WRITE */
227
Edgar E. Iglesias2c174492013-12-17 14:05:40 +1000228 new_asce = ldq_phys(cs->as, origin + offs);
Alexander Grafd5a43962011-03-23 10:58:07 +0100229 PTE_DPRINTF("%s: 0x%" PRIx64 " + 0x%" PRIx64 " => 0x%016" PRIx64 "\n",
Blue Swirl71e47082012-09-02 07:33:30 +0000230 __func__, origin, offs, new_asce);
Alexander Grafd5a43962011-03-23 10:58:07 +0100231
232 if (level != _ASCE_TYPE_SEGMENT) {
233 /* yet another region */
234 return mmu_translate_asce(env, vaddr, asc, new_asce, level - 4, raddr,
235 flags, rw);
236 }
237
238 /* PTE */
239 if (new_asce & _PAGE_INVALID) {
Blue Swirl71e47082012-09-02 07:33:30 +0000240 DPRINTF("%s: PTE=0x%" PRIx64 " invalid\n", __func__, new_asce);
Alexander Grafd5a43962011-03-23 10:58:07 +0100241 trigger_page_fault(env, vaddr, PGM_PAGE_TRANS, asc, rw);
242 return -1;
243 }
244
245 if (new_asce & _PAGE_RO) {
246 *flags &= ~PAGE_WRITE;
247 }
248
249 *raddr = new_asce & _ASCE_ORIGIN;
250
Blue Swirl71e47082012-09-02 07:33:30 +0000251 PTE_DPRINTF("%s: PTE=0x%" PRIx64 "\n", __func__, new_asce);
Alexander Grafd5a43962011-03-23 10:58:07 +0100252
Paul Brookd4c430a2010-03-17 02:14:28 +0000253 return 0;
Alexander Graf10c339a2009-12-05 12:44:26 +0100254}
Alexander Grafd5a43962011-03-23 10:58:07 +0100255
Blue Swirl71e47082012-09-02 07:33:30 +0000256static int mmu_translate_asc(CPUS390XState *env, target_ulong vaddr,
257 uint64_t asc, target_ulong *raddr, int *flags,
258 int rw)
Alexander Grafd5a43962011-03-23 10:58:07 +0100259{
260 uint64_t asce = 0;
261 int level, new_level;
262 int r;
263
264 switch (asc) {
265 case PSW_ASC_PRIMARY:
Blue Swirl71e47082012-09-02 07:33:30 +0000266 PTE_DPRINTF("%s: asc=primary\n", __func__);
Alexander Grafd5a43962011-03-23 10:58:07 +0100267 asce = env->cregs[1];
268 break;
269 case PSW_ASC_SECONDARY:
Blue Swirl71e47082012-09-02 07:33:30 +0000270 PTE_DPRINTF("%s: asc=secondary\n", __func__);
Alexander Grafd5a43962011-03-23 10:58:07 +0100271 asce = env->cregs[7];
272 break;
273 case PSW_ASC_HOME:
Blue Swirl71e47082012-09-02 07:33:30 +0000274 PTE_DPRINTF("%s: asc=home\n", __func__);
Alexander Grafd5a43962011-03-23 10:58:07 +0100275 asce = env->cregs[13];
276 break;
277 }
278
279 switch (asce & _ASCE_TYPE_MASK) {
280 case _ASCE_TYPE_REGION1:
281 break;
282 case _ASCE_TYPE_REGION2:
283 if (vaddr & 0xffe0000000000000ULL) {
284 DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
Blue Swirl71e47082012-09-02 07:33:30 +0000285 " 0xffe0000000000000ULL\n", __func__, vaddr);
Alexander Grafd5a43962011-03-23 10:58:07 +0100286 trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
287 return -1;
288 }
289 break;
290 case _ASCE_TYPE_REGION3:
291 if (vaddr & 0xfffffc0000000000ULL) {
292 DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
Blue Swirl71e47082012-09-02 07:33:30 +0000293 " 0xfffffc0000000000ULL\n", __func__, vaddr);
Alexander Grafd5a43962011-03-23 10:58:07 +0100294 trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
295 return -1;
296 }
297 break;
298 case _ASCE_TYPE_SEGMENT:
299 if (vaddr & 0xffffffff80000000ULL) {
300 DPRINTF("%s: vaddr doesn't fit 0x%16" PRIx64
Blue Swirl71e47082012-09-02 07:33:30 +0000301 " 0xffffffff80000000ULL\n", __func__, vaddr);
Alexander Grafd5a43962011-03-23 10:58:07 +0100302 trigger_page_fault(env, vaddr, PGM_TRANS_SPEC, asc, rw);
303 return -1;
304 }
305 break;
306 }
307
308 /* fake level above current */
309 level = asce & _ASCE_TYPE_MASK;
310 new_level = level + 4;
311 asce = (asce & ~_ASCE_TYPE_MASK) | (new_level & _ASCE_TYPE_MASK);
312
313 r = mmu_translate_asce(env, vaddr, asc, asce, new_level, raddr, flags, rw);
314
315 if ((rw == 1) && !(*flags & PAGE_WRITE)) {
316 trigger_prot_fault(env, vaddr, asc);
317 return -1;
318 }
319
320 return r;
321}
322
Andreas Färbera4e3ad12012-03-14 01:38:22 +0100323int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
Alexander Grafd5a43962011-03-23 10:58:07 +0100324 target_ulong *raddr, int *flags)
325{
326 int r = -1;
Alexander Grafb9959132011-07-14 11:49:08 +0200327 uint8_t *sk;
Alexander Grafd5a43962011-03-23 10:58:07 +0100328
329 *flags = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
330 vaddr &= TARGET_PAGE_MASK;
331
332 if (!(env->psw.mask & PSW_MASK_DAT)) {
333 *raddr = vaddr;
334 r = 0;
335 goto out;
336 }
337
338 switch (asc) {
339 case PSW_ASC_PRIMARY:
340 case PSW_ASC_HOME:
341 r = mmu_translate_asc(env, vaddr, asc, raddr, flags, rw);
342 break;
343 case PSW_ASC_SECONDARY:
344 /*
345 * Instruction: Primary
346 * Data: Secondary
347 */
348 if (rw == 2) {
349 r = mmu_translate_asc(env, vaddr, PSW_ASC_PRIMARY, raddr, flags,
350 rw);
351 *flags &= ~(PAGE_READ | PAGE_WRITE);
352 } else {
353 r = mmu_translate_asc(env, vaddr, PSW_ASC_SECONDARY, raddr, flags,
354 rw);
355 *flags &= ~(PAGE_EXEC);
356 }
357 break;
358 case PSW_ASC_ACCREG:
359 default:
360 hw_error("guest switched to unknown asc mode\n");
361 break;
362 }
363
Blue Swirl71e47082012-09-02 07:33:30 +0000364 out:
Alexander Grafd5a43962011-03-23 10:58:07 +0100365 /* Convert real address -> absolute address */
366 if (*raddr < 0x2000) {
367 *raddr = *raddr + env->psa;
368 }
369
Alexander Grafb9959132011-07-14 11:49:08 +0200370 if (*raddr <= ram_size) {
371 sk = &env->storage_keys[*raddr / TARGET_PAGE_SIZE];
372 if (*flags & PAGE_READ) {
373 *sk |= SK_R;
374 }
375
376 if (*flags & PAGE_WRITE) {
377 *sk |= SK_C;
378 }
379 }
380
Alexander Grafd5a43962011-03-23 10:58:07 +0100381 return r;
382}
383
Andreas Färber75104542013-08-26 03:01:33 +0200384int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr,
385 int rw, int mmu_idx)
Alexander Grafd5a43962011-03-23 10:58:07 +0100386{
Andreas Färber75104542013-08-26 03:01:33 +0200387 S390CPU *cpu = S390_CPU(cs);
388 CPUS390XState *env = &cpu->env;
Alexander Grafd5a43962011-03-23 10:58:07 +0100389 uint64_t asc = env->psw.mask & PSW_MASK_ASC;
390 target_ulong vaddr, raddr;
391 int prot;
392
Andreas Färber75104542013-08-26 03:01:33 +0200393 DPRINTF("%s: address 0x%" VADDR_PRIx " rw %d mmu_idx %d\n",
Andreas Färber07cc7d12013-01-27 03:32:03 +0000394 __func__, orig_vaddr, rw, mmu_idx);
Alexander Grafd5a43962011-03-23 10:58:07 +0100395
Blue Swirl71e47082012-09-02 07:33:30 +0000396 orig_vaddr &= TARGET_PAGE_MASK;
397 vaddr = orig_vaddr;
Alexander Grafd5a43962011-03-23 10:58:07 +0100398
399 /* 31-Bit mode */
400 if (!(env->psw.mask & PSW_MASK_64)) {
401 vaddr &= 0x7fffffff;
402 }
403
404 if (mmu_translate(env, vaddr, rw, asc, &raddr, &prot)) {
405 /* Translation ended in exception */
406 return 1;
407 }
408
409 /* check out of RAM access */
410 if (raddr > (ram_size + virtio_size)) {
Andreas Färbera6f921b2013-01-27 03:32:04 +0000411 DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
412 (uint64_t)raddr, (uint64_t)ram_size);
Richard Hendersond5a103c2012-09-14 19:31:57 -0700413 trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_LATER);
Alexander Grafd5a43962011-03-23 10:58:07 +0100414 return 1;
415 }
416
Blue Swirl71e47082012-09-02 07:33:30 +0000417 DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__,
Alexander Grafd5a43962011-03-23 10:58:07 +0100418 (uint64_t)vaddr, (uint64_t)raddr, prot);
419
Andreas Färber0c591eb2013-09-03 13:59:37 +0200420 tlb_set_page(cs, orig_vaddr, raddr, prot,
Alexander Grafd5a43962011-03-23 10:58:07 +0100421 mmu_idx, TARGET_PAGE_SIZE);
422
423 return 0;
424}
425
Andreas Färber00b941e2013-06-29 18:55:54 +0200426hwaddr s390_cpu_get_phys_page_debug(CPUState *cs, vaddr vaddr)
Alexander Grafd5a43962011-03-23 10:58:07 +0100427{
Andreas Färber00b941e2013-06-29 18:55:54 +0200428 S390CPU *cpu = S390_CPU(cs);
429 CPUS390XState *env = &cpu->env;
Alexander Grafd5a43962011-03-23 10:58:07 +0100430 target_ulong raddr;
431 int prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
Andreas Färber27103422013-08-26 08:31:06 +0200432 int old_exc = cs->exception_index;
Alexander Grafd5a43962011-03-23 10:58:07 +0100433 uint64_t asc = env->psw.mask & PSW_MASK_ASC;
434
435 /* 31-Bit mode */
436 if (!(env->psw.mask & PSW_MASK_64)) {
437 vaddr &= 0x7fffffff;
438 }
439
440 mmu_translate(env, vaddr, 2, asc, &raddr, &prot);
Andreas Färber27103422013-08-26 08:31:06 +0200441 cs->exception_index = old_exc;
Alexander Grafd5a43962011-03-23 10:58:07 +0100442
443 return raddr;
444}
445
Andreas Färbera4e3ad12012-03-14 01:38:22 +0100446void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr)
Alexander Grafd5a43962011-03-23 10:58:07 +0100447{
448 if (mask & PSW_MASK_WAIT) {
Andreas Färber49e15872013-01-30 12:48:25 +0000449 S390CPU *cpu = s390_env_get_cpu(env);
Andreas Färber259186a2013-01-17 18:51:17 +0100450 CPUState *cs = CPU(cpu);
Alexander Grafef815222011-10-07 09:51:50 +0200451 if (!(mask & (PSW_MASK_IO | PSW_MASK_EXT | PSW_MASK_MCHECK))) {
Andreas Färber49e15872013-01-30 12:48:25 +0000452 if (s390_del_running_cpu(cpu) == 0) {
Alexander Grafef815222011-10-07 09:51:50 +0200453#ifndef CONFIG_USER_ONLY
454 qemu_system_shutdown_request();
455#endif
456 }
457 }
Andreas Färber259186a2013-01-17 18:51:17 +0100458 cs->halted = 1;
Andreas Färber27103422013-08-26 08:31:06 +0200459 cs->exception_index = EXCP_HLT;
Alexander Grafd5a43962011-03-23 10:58:07 +0100460 }
461
462 env->psw.addr = addr;
463 env->psw.mask = mask;
Richard Henderson51855ec2012-09-24 12:06:15 -0700464 env->cc_op = (mask >> 44) & 3;
Alexander Grafd5a43962011-03-23 10:58:07 +0100465}
466
Andreas Färbera4e3ad12012-03-14 01:38:22 +0100467static uint64_t get_psw_mask(CPUS390XState *env)
Alexander Grafd5a43962011-03-23 10:58:07 +0100468{
Richard Henderson51855ec2012-09-24 12:06:15 -0700469 uint64_t r;
Alexander Grafd5a43962011-03-23 10:58:07 +0100470
471 env->cc_op = calc_cc(env, env->cc_op, env->cc_src, env->cc_dst, env->cc_vr);
472
Richard Henderson51855ec2012-09-24 12:06:15 -0700473 r = env->psw.mask;
474 r &= ~PSW_MASK_CC;
Alexander Grafd5a43962011-03-23 10:58:07 +0100475 assert(!(env->cc_op & ~3));
Richard Henderson51855ec2012-09-24 12:06:15 -0700476 r |= (uint64_t)env->cc_op << 44;
Alexander Grafd5a43962011-03-23 10:58:07 +0100477
478 return r;
479}
480
Cornelia Huck4782a232013-01-24 02:28:01 +0000481static LowCore *cpu_map_lowcore(CPUS390XState *env)
482{
Andreas Färbera47dddd2013-09-03 17:38:47 +0200483 S390CPU *cpu = s390_env_get_cpu(env);
Cornelia Huck4782a232013-01-24 02:28:01 +0000484 LowCore *lowcore;
485 hwaddr len = sizeof(LowCore);
486
487 lowcore = cpu_physical_memory_map(env->psa, &len, 1);
488
489 if (len < sizeof(LowCore)) {
Andreas Färbera47dddd2013-09-03 17:38:47 +0200490 cpu_abort(CPU(cpu), "Could not map lowcore\n");
Cornelia Huck4782a232013-01-24 02:28:01 +0000491 }
492
493 return lowcore;
494}
495
496static void cpu_unmap_lowcore(LowCore *lowcore)
497{
498 cpu_physical_memory_unmap(lowcore, sizeof(LowCore), 1, sizeof(LowCore));
499}
500
Cornelia Huck38322ed2013-01-24 02:28:02 +0000501void *s390_cpu_physical_memory_map(CPUS390XState *env, hwaddr addr, hwaddr *len,
502 int is_write)
503{
504 hwaddr start = addr;
505
506 /* Mind the prefix area. */
507 if (addr < 8192) {
508 /* Map the lowcore. */
509 start += env->psa;
510 *len = MIN(*len, 8192 - addr);
511 } else if ((addr >= env->psa) && (addr < env->psa + 8192)) {
512 /* Map the 0 page. */
513 start -= env->psa;
514 *len = MIN(*len, 8192 - start);
515 }
516
517 return cpu_physical_memory_map(start, len, is_write);
518}
519
520void s390_cpu_physical_memory_unmap(CPUS390XState *env, void *addr, hwaddr len,
521 int is_write)
522{
523 cpu_physical_memory_unmap(addr, len, is_write, len);
524}
525
Andreas Färbera4e3ad12012-03-14 01:38:22 +0100526static void do_svc_interrupt(CPUS390XState *env)
Alexander Grafd5a43962011-03-23 10:58:07 +0100527{
528 uint64_t mask, addr;
529 LowCore *lowcore;
Alexander Grafd5a43962011-03-23 10:58:07 +0100530
Cornelia Huck4782a232013-01-24 02:28:01 +0000531 lowcore = cpu_map_lowcore(env);
Alexander Grafd5a43962011-03-23 10:58:07 +0100532
533 lowcore->svc_code = cpu_to_be16(env->int_svc_code);
Richard Hendersond5a103c2012-09-14 19:31:57 -0700534 lowcore->svc_ilen = cpu_to_be16(env->int_svc_ilen);
Alexander Grafd5a43962011-03-23 10:58:07 +0100535 lowcore->svc_old_psw.mask = cpu_to_be64(get_psw_mask(env));
Richard Hendersond5a103c2012-09-14 19:31:57 -0700536 lowcore->svc_old_psw.addr = cpu_to_be64(env->psw.addr + env->int_svc_ilen);
Alexander Grafd5a43962011-03-23 10:58:07 +0100537 mask = be64_to_cpu(lowcore->svc_new_psw.mask);
538 addr = be64_to_cpu(lowcore->svc_new_psw.addr);
539
Cornelia Huck4782a232013-01-24 02:28:01 +0000540 cpu_unmap_lowcore(lowcore);
Alexander Grafd5a43962011-03-23 10:58:07 +0100541
542 load_psw(env, mask, addr);
543}
544
Andreas Färbera4e3ad12012-03-14 01:38:22 +0100545static void do_program_interrupt(CPUS390XState *env)
Alexander Grafd5a43962011-03-23 10:58:07 +0100546{
547 uint64_t mask, addr;
548 LowCore *lowcore;
Richard Hendersond5a103c2012-09-14 19:31:57 -0700549 int ilen = env->int_pgm_ilen;
Alexander Grafd5a43962011-03-23 10:58:07 +0100550
Richard Hendersond5a103c2012-09-14 19:31:57 -0700551 switch (ilen) {
552 case ILEN_LATER:
553 ilen = get_ilen(cpu_ldub_code(env, env->psw.addr));
Alexander Grafd5a43962011-03-23 10:58:07 +0100554 break;
Richard Hendersond5a103c2012-09-14 19:31:57 -0700555 case ILEN_LATER_INC:
556 ilen = get_ilen(cpu_ldub_code(env, env->psw.addr));
557 env->psw.addr += ilen;
Alexander Grafd5a43962011-03-23 10:58:07 +0100558 break;
Richard Hendersond5a103c2012-09-14 19:31:57 -0700559 default:
560 assert(ilen == 2 || ilen == 4 || ilen == 6);
Alexander Grafd5a43962011-03-23 10:58:07 +0100561 }
562
Richard Hendersond5a103c2012-09-14 19:31:57 -0700563 qemu_log_mask(CPU_LOG_INT, "%s: code=0x%x ilen=%d\n",
564 __func__, env->int_pgm_code, ilen);
Alexander Grafd5a43962011-03-23 10:58:07 +0100565
Cornelia Huck4782a232013-01-24 02:28:01 +0000566 lowcore = cpu_map_lowcore(env);
Alexander Grafd5a43962011-03-23 10:58:07 +0100567
Richard Hendersond5a103c2012-09-14 19:31:57 -0700568 lowcore->pgm_ilen = cpu_to_be16(ilen);
Alexander Grafd5a43962011-03-23 10:58:07 +0100569 lowcore->pgm_code = cpu_to_be16(env->int_pgm_code);
570 lowcore->program_old_psw.mask = cpu_to_be64(get_psw_mask(env));
571 lowcore->program_old_psw.addr = cpu_to_be64(env->psw.addr);
572 mask = be64_to_cpu(lowcore->program_new_psw.mask);
573 addr = be64_to_cpu(lowcore->program_new_psw.addr);
574
Cornelia Huck4782a232013-01-24 02:28:01 +0000575 cpu_unmap_lowcore(lowcore);
Alexander Grafd5a43962011-03-23 10:58:07 +0100576
Blue Swirl71e47082012-09-02 07:33:30 +0000577 DPRINTF("%s: %x %x %" PRIx64 " %" PRIx64 "\n", __func__,
Richard Hendersond5a103c2012-09-14 19:31:57 -0700578 env->int_pgm_code, ilen, env->psw.mask,
Alexander Grafd5a43962011-03-23 10:58:07 +0100579 env->psw.addr);
580
581 load_psw(env, mask, addr);
582}
583
584#define VIRTIO_SUBCODE_64 0x0D00
585
Andreas Färbera4e3ad12012-03-14 01:38:22 +0100586static void do_ext_interrupt(CPUS390XState *env)
Alexander Grafd5a43962011-03-23 10:58:07 +0100587{
Andreas Färbera47dddd2013-09-03 17:38:47 +0200588 S390CPU *cpu = s390_env_get_cpu(env);
Alexander Grafd5a43962011-03-23 10:58:07 +0100589 uint64_t mask, addr;
590 LowCore *lowcore;
Alexander Grafd5a43962011-03-23 10:58:07 +0100591 ExtQueue *q;
592
593 if (!(env->psw.mask & PSW_MASK_EXT)) {
Andreas Färbera47dddd2013-09-03 17:38:47 +0200594 cpu_abort(CPU(cpu), "Ext int w/o ext mask\n");
Alexander Grafd5a43962011-03-23 10:58:07 +0100595 }
596
597 if (env->ext_index < 0 || env->ext_index > MAX_EXT_QUEUE) {
Andreas Färbera47dddd2013-09-03 17:38:47 +0200598 cpu_abort(CPU(cpu), "Ext queue overrun: %d\n", env->ext_index);
Alexander Grafd5a43962011-03-23 10:58:07 +0100599 }
600
601 q = &env->ext_queue[env->ext_index];
Cornelia Huck4782a232013-01-24 02:28:01 +0000602 lowcore = cpu_map_lowcore(env);
Alexander Grafd5a43962011-03-23 10:58:07 +0100603
604 lowcore->ext_int_code = cpu_to_be16(q->code);
605 lowcore->ext_params = cpu_to_be32(q->param);
606 lowcore->ext_params2 = cpu_to_be64(q->param64);
607 lowcore->external_old_psw.mask = cpu_to_be64(get_psw_mask(env));
608 lowcore->external_old_psw.addr = cpu_to_be64(env->psw.addr);
609 lowcore->cpu_addr = cpu_to_be16(env->cpu_num | VIRTIO_SUBCODE_64);
610 mask = be64_to_cpu(lowcore->external_new_psw.mask);
611 addr = be64_to_cpu(lowcore->external_new_psw.addr);
612
Cornelia Huck4782a232013-01-24 02:28:01 +0000613 cpu_unmap_lowcore(lowcore);
Alexander Grafd5a43962011-03-23 10:58:07 +0100614
615 env->ext_index--;
616 if (env->ext_index == -1) {
617 env->pending_int &= ~INTERRUPT_EXT;
618 }
619
Blue Swirl71e47082012-09-02 07:33:30 +0000620 DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
Alexander Grafd5a43962011-03-23 10:58:07 +0100621 env->psw.mask, env->psw.addr);
622
623 load_psw(env, mask, addr);
624}
Alexander Graf3110e292011-04-15 17:32:48 +0200625
Cornelia Huck5d69c542013-01-24 02:28:04 +0000626static void do_io_interrupt(CPUS390XState *env)
627{
Andreas Färbera47dddd2013-09-03 17:38:47 +0200628 S390CPU *cpu = s390_env_get_cpu(env);
Cornelia Huck5d69c542013-01-24 02:28:04 +0000629 LowCore *lowcore;
630 IOIntQueue *q;
631 uint8_t isc;
632 int disable = 1;
633 int found = 0;
634
635 if (!(env->psw.mask & PSW_MASK_IO)) {
Andreas Färbera47dddd2013-09-03 17:38:47 +0200636 cpu_abort(CPU(cpu), "I/O int w/o I/O mask\n");
Cornelia Huck5d69c542013-01-24 02:28:04 +0000637 }
638
639 for (isc = 0; isc < ARRAY_SIZE(env->io_index); isc++) {
Cornelia Huck91b0a8f2013-02-07 02:20:51 +0000640 uint64_t isc_bits;
641
Cornelia Huck5d69c542013-01-24 02:28:04 +0000642 if (env->io_index[isc] < 0) {
643 continue;
644 }
645 if (env->io_index[isc] > MAX_IO_QUEUE) {
Andreas Färbera47dddd2013-09-03 17:38:47 +0200646 cpu_abort(CPU(cpu), "I/O queue overrun for isc %d: %d\n",
Cornelia Huck5d69c542013-01-24 02:28:04 +0000647 isc, env->io_index[isc]);
648 }
649
650 q = &env->io_queue[env->io_index[isc]][isc];
Cornelia Huck91b0a8f2013-02-07 02:20:51 +0000651 isc_bits = ISC_TO_ISC_BITS(IO_INT_WORD_ISC(q->word));
652 if (!(env->cregs[6] & isc_bits)) {
Cornelia Huck5d69c542013-01-24 02:28:04 +0000653 disable = 0;
654 continue;
655 }
Cornelia Huckbd9a8d82013-02-07 02:20:50 +0000656 if (!found) {
657 uint64_t mask, addr;
Cornelia Huck5d69c542013-01-24 02:28:04 +0000658
Cornelia Huckbd9a8d82013-02-07 02:20:50 +0000659 found = 1;
660 lowcore = cpu_map_lowcore(env);
Cornelia Huck5d69c542013-01-24 02:28:04 +0000661
Cornelia Huckbd9a8d82013-02-07 02:20:50 +0000662 lowcore->subchannel_id = cpu_to_be16(q->id);
663 lowcore->subchannel_nr = cpu_to_be16(q->nr);
664 lowcore->io_int_parm = cpu_to_be32(q->parm);
665 lowcore->io_int_word = cpu_to_be32(q->word);
666 lowcore->io_old_psw.mask = cpu_to_be64(get_psw_mask(env));
667 lowcore->io_old_psw.addr = cpu_to_be64(env->psw.addr);
668 mask = be64_to_cpu(lowcore->io_new_psw.mask);
669 addr = be64_to_cpu(lowcore->io_new_psw.addr);
Cornelia Huck5d69c542013-01-24 02:28:04 +0000670
Cornelia Huckbd9a8d82013-02-07 02:20:50 +0000671 cpu_unmap_lowcore(lowcore);
672
673 env->io_index[isc]--;
674
675 DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
676 env->psw.mask, env->psw.addr);
677 load_psw(env, mask, addr);
678 }
Stefan Weilb22dd122013-02-03 21:33:16 +0100679 if (env->io_index[isc] >= 0) {
Cornelia Huck5d69c542013-01-24 02:28:04 +0000680 disable = 0;
681 }
Cornelia Huckbd9a8d82013-02-07 02:20:50 +0000682 continue;
Cornelia Huck5d69c542013-01-24 02:28:04 +0000683 }
684
685 if (disable) {
686 env->pending_int &= ~INTERRUPT_IO;
687 }
688
Cornelia Huck5d69c542013-01-24 02:28:04 +0000689}
690
691static void do_mchk_interrupt(CPUS390XState *env)
692{
Andreas Färbera47dddd2013-09-03 17:38:47 +0200693 S390CPU *cpu = s390_env_get_cpu(env);
Cornelia Huck5d69c542013-01-24 02:28:04 +0000694 uint64_t mask, addr;
695 LowCore *lowcore;
696 MchkQueue *q;
697 int i;
698
699 if (!(env->psw.mask & PSW_MASK_MCHECK)) {
Andreas Färbera47dddd2013-09-03 17:38:47 +0200700 cpu_abort(CPU(cpu), "Machine check w/o mchk mask\n");
Cornelia Huck5d69c542013-01-24 02:28:04 +0000701 }
702
703 if (env->mchk_index < 0 || env->mchk_index > MAX_MCHK_QUEUE) {
Andreas Färbera47dddd2013-09-03 17:38:47 +0200704 cpu_abort(CPU(cpu), "Mchk queue overrun: %d\n", env->mchk_index);
Cornelia Huck5d69c542013-01-24 02:28:04 +0000705 }
706
707 q = &env->mchk_queue[env->mchk_index];
708
709 if (q->type != 1) {
710 /* Don't know how to handle this... */
Andreas Färbera47dddd2013-09-03 17:38:47 +0200711 cpu_abort(CPU(cpu), "Unknown machine check type %d\n", q->type);
Cornelia Huck5d69c542013-01-24 02:28:04 +0000712 }
713 if (!(env->cregs[14] & (1 << 28))) {
714 /* CRW machine checks disabled */
715 return;
716 }
717
718 lowcore = cpu_map_lowcore(env);
719
720 for (i = 0; i < 16; i++) {
721 lowcore->floating_pt_save_area[i] = cpu_to_be64(env->fregs[i].ll);
722 lowcore->gpregs_save_area[i] = cpu_to_be64(env->regs[i]);
723 lowcore->access_regs_save_area[i] = cpu_to_be32(env->aregs[i]);
724 lowcore->cregs_save_area[i] = cpu_to_be64(env->cregs[i]);
725 }
726 lowcore->prefixreg_save_area = cpu_to_be32(env->psa);
727 lowcore->fpt_creg_save_area = cpu_to_be32(env->fpc);
728 lowcore->tod_progreg_save_area = cpu_to_be32(env->todpr);
729 lowcore->cpu_timer_save_area[0] = cpu_to_be32(env->cputm >> 32);
730 lowcore->cpu_timer_save_area[1] = cpu_to_be32((uint32_t)env->cputm);
731 lowcore->clock_comp_save_area[0] = cpu_to_be32(env->ckc >> 32);
732 lowcore->clock_comp_save_area[1] = cpu_to_be32((uint32_t)env->ckc);
733
734 lowcore->mcck_interruption_code[0] = cpu_to_be32(0x00400f1d);
735 lowcore->mcck_interruption_code[1] = cpu_to_be32(0x40330000);
736 lowcore->mcck_old_psw.mask = cpu_to_be64(get_psw_mask(env));
737 lowcore->mcck_old_psw.addr = cpu_to_be64(env->psw.addr);
738 mask = be64_to_cpu(lowcore->mcck_new_psw.mask);
739 addr = be64_to_cpu(lowcore->mcck_new_psw.addr);
740
741 cpu_unmap_lowcore(lowcore);
742
743 env->mchk_index--;
744 if (env->mchk_index == -1) {
745 env->pending_int &= ~INTERRUPT_MCHK;
746 }
747
748 DPRINTF("%s: %" PRIx64 " %" PRIx64 "\n", __func__,
749 env->psw.mask, env->psw.addr);
750
751 load_psw(env, mask, addr);
752}
753
Andreas Färber97a8ea52013-02-02 10:57:51 +0100754void s390_cpu_do_interrupt(CPUState *cs)
Alexander Graf3110e292011-04-15 17:32:48 +0200755{
Andreas Färber97a8ea52013-02-02 10:57:51 +0100756 S390CPU *cpu = S390_CPU(cs);
757 CPUS390XState *env = &cpu->env;
Andreas Färberf9466732013-01-30 12:48:24 +0000758
Richard Henderson0d404542012-09-24 14:55:51 -0700759 qemu_log_mask(CPU_LOG_INT, "%s: %d at pc=%" PRIx64 "\n",
Andreas Färber27103422013-08-26 08:31:06 +0200760 __func__, cs->exception_index, env->psw.addr);
Alexander Grafd5a43962011-03-23 10:58:07 +0100761
Andreas Färber49e15872013-01-30 12:48:25 +0000762 s390_add_running_cpu(cpu);
Cornelia Huck5d69c542013-01-24 02:28:04 +0000763 /* handle machine checks */
764 if ((env->psw.mask & PSW_MASK_MCHECK) &&
Andreas Färber27103422013-08-26 08:31:06 +0200765 (cs->exception_index == -1)) {
Cornelia Huck5d69c542013-01-24 02:28:04 +0000766 if (env->pending_int & INTERRUPT_MCHK) {
Andreas Färber27103422013-08-26 08:31:06 +0200767 cs->exception_index = EXCP_MCHK;
Cornelia Huck5d69c542013-01-24 02:28:04 +0000768 }
769 }
Alexander Grafd5a43962011-03-23 10:58:07 +0100770 /* handle external interrupts */
771 if ((env->psw.mask & PSW_MASK_EXT) &&
Andreas Färber27103422013-08-26 08:31:06 +0200772 cs->exception_index == -1) {
Alexander Grafd5a43962011-03-23 10:58:07 +0100773 if (env->pending_int & INTERRUPT_EXT) {
774 /* code is already in env */
Andreas Färber27103422013-08-26 08:31:06 +0200775 cs->exception_index = EXCP_EXT;
Alexander Grafd5a43962011-03-23 10:58:07 +0100776 } else if (env->pending_int & INTERRUPT_TOD) {
Andreas Färberf9466732013-01-30 12:48:24 +0000777 cpu_inject_ext(cpu, 0x1004, 0, 0);
Andreas Färber27103422013-08-26 08:31:06 +0200778 cs->exception_index = EXCP_EXT;
Alexander Grafd5a43962011-03-23 10:58:07 +0100779 env->pending_int &= ~INTERRUPT_EXT;
780 env->pending_int &= ~INTERRUPT_TOD;
781 } else if (env->pending_int & INTERRUPT_CPUTIMER) {
Andreas Färberf9466732013-01-30 12:48:24 +0000782 cpu_inject_ext(cpu, 0x1005, 0, 0);
Andreas Färber27103422013-08-26 08:31:06 +0200783 cs->exception_index = EXCP_EXT;
Alexander Grafd5a43962011-03-23 10:58:07 +0100784 env->pending_int &= ~INTERRUPT_EXT;
785 env->pending_int &= ~INTERRUPT_TOD;
786 }
787 }
Cornelia Huck5d69c542013-01-24 02:28:04 +0000788 /* handle I/O interrupts */
789 if ((env->psw.mask & PSW_MASK_IO) &&
Andreas Färber27103422013-08-26 08:31:06 +0200790 (cs->exception_index == -1)) {
Cornelia Huck5d69c542013-01-24 02:28:04 +0000791 if (env->pending_int & INTERRUPT_IO) {
Andreas Färber27103422013-08-26 08:31:06 +0200792 cs->exception_index = EXCP_IO;
Cornelia Huck5d69c542013-01-24 02:28:04 +0000793 }
794 }
Alexander Grafd5a43962011-03-23 10:58:07 +0100795
Andreas Färber27103422013-08-26 08:31:06 +0200796 switch (cs->exception_index) {
Alexander Grafd5a43962011-03-23 10:58:07 +0100797 case EXCP_PGM:
798 do_program_interrupt(env);
799 break;
800 case EXCP_SVC:
801 do_svc_interrupt(env);
802 break;
803 case EXCP_EXT:
804 do_ext_interrupt(env);
805 break;
Cornelia Huck5d69c542013-01-24 02:28:04 +0000806 case EXCP_IO:
807 do_io_interrupt(env);
808 break;
809 case EXCP_MCHK:
810 do_mchk_interrupt(env);
811 break;
Alexander Grafd5a43962011-03-23 10:58:07 +0100812 }
Andreas Färber27103422013-08-26 08:31:06 +0200813 cs->exception_index = -1;
Alexander Grafd5a43962011-03-23 10:58:07 +0100814
815 if (!env->pending_int) {
Andreas Färber259186a2013-01-17 18:51:17 +0100816 cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
Alexander Grafd5a43962011-03-23 10:58:07 +0100817 }
Alexander Graf3110e292011-04-15 17:32:48 +0200818}
Alexander Grafd5a43962011-03-23 10:58:07 +0100819
820#endif /* CONFIG_USER_ONLY */