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ths5fafdf22007-09-16 21:08:06 +00001/*
pbrook502a5392006-05-13 16:11:23 +00002 * ARM Versatile/PB PCI host controller
3 *
Paul Brook0027b062009-05-14 22:35:08 +01004 * Copyright (c) 2006-2009 CodeSourcery.
pbrook502a5392006-05-13 16:11:23 +00005 * Written by Paul Brook
6 *
Matthew Fernandez8e31bf32011-06-26 12:21:35 +10007 * This code is licensed under the LGPL.
pbrook502a5392006-05-13 16:11:23 +00008 */
9
Paul Brook0027b062009-05-14 22:35:08 +010010#include "sysbus.h"
Michael S. Tsirkina2cb15b2012-12-12 14:24:50 +020011#include "pci/pci.h"
12#include "pci/pci_host.h"
Paolo Bonzini022c62c2012-12-17 18:19:49 +010013#include "exec/address-spaces.h"
Paul Brook0027b062009-05-14 22:35:08 +010014
15typedef struct {
16 SysBusDevice busdev;
17 qemu_irq irq[4];
18 int realview;
Avi Kivity45de0942011-08-15 17:17:32 +030019 MemoryRegion mem_config;
20 MemoryRegion mem_config2;
21 MemoryRegion isa;
Paul Brook0027b062009-05-14 22:35:08 +010022} PCIVPBState;
pbrook502a5392006-05-13 16:11:23 +000023
Avi Kivitya8170e52012-10-23 12:30:10 +020024static inline uint32_t vpb_pci_config_addr(hwaddr addr)
pbrook502a5392006-05-13 16:11:23 +000025{
pbrook80b3ada2006-09-24 17:01:44 +000026 return addr & 0xffffff;
pbrook502a5392006-05-13 16:11:23 +000027}
28
Avi Kivitya8170e52012-10-23 12:30:10 +020029static void pci_vpb_config_write(void *opaque, hwaddr addr,
Avi Kivity45de0942011-08-15 17:17:32 +030030 uint64_t val, unsigned size)
pbrook502a5392006-05-13 16:11:23 +000031{
Avi Kivity45de0942011-08-15 17:17:32 +030032 pci_data_write(opaque, vpb_pci_config_addr(addr), val, size);
pbrook502a5392006-05-13 16:11:23 +000033}
34
Avi Kivitya8170e52012-10-23 12:30:10 +020035static uint64_t pci_vpb_config_read(void *opaque, hwaddr addr,
Avi Kivity45de0942011-08-15 17:17:32 +030036 unsigned size)
pbrook502a5392006-05-13 16:11:23 +000037{
38 uint32_t val;
Avi Kivity45de0942011-08-15 17:17:32 +030039 val = pci_data_read(opaque, vpb_pci_config_addr(addr), size);
pbrook502a5392006-05-13 16:11:23 +000040 return val;
41}
42
Avi Kivity45de0942011-08-15 17:17:32 +030043static const MemoryRegionOps pci_vpb_config_ops = {
44 .read = pci_vpb_config_read,
45 .write = pci_vpb_config_write,
46 .endianness = DEVICE_NATIVE_ENDIAN,
pbrook502a5392006-05-13 16:11:23 +000047};
48
pbrookd2b59312006-09-24 00:16:34 +000049static int pci_vpb_map_irq(PCIDevice *d, int irq_num)
50{
51 return irq_num;
52}
53
Juan Quintela5d4e84c2009-08-28 15:28:17 +020054static void pci_vpb_set_irq(void *opaque, int irq_num, int level)
pbrook502a5392006-05-13 16:11:23 +000055{
Juan Quintela5d4e84c2009-08-28 15:28:17 +020056 qemu_irq *pic = opaque;
57
Paul Brook97aff482009-05-14 22:35:07 +010058 qemu_set_irq(pic[irq_num], level);
pbrook502a5392006-05-13 16:11:23 +000059}
60
Gerd Hoffmann81a322d2009-08-14 10:36:05 +020061static int pci_vpb_init(SysBusDevice *dev)
Paul Brook0027b062009-05-14 22:35:08 +010062{
63 PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
64 PCIBus *bus;
65 int i;
66
67 for (i = 0; i < 4; i++) {
68 sysbus_init_irq(dev, &s->irq[i]);
69 }
Paul Brook02e2da42009-05-23 00:05:19 +010070 bus = pci_register_bus(&dev->qdev, "pci",
71 pci_vpb_set_irq, pci_vpb_map_irq, s->irq,
Avi Kivityaee97b82011-08-08 16:09:04 +030072 get_system_memory(), get_system_io(),
Isaku Yamahata520128b2010-06-23 16:15:25 +090073 PCI_DEVFN(11, 0), 4);
Paul Brook0027b062009-05-14 22:35:08 +010074
75 /* ??? Register memory space. */
76
Peter Maydell7d6e7712011-09-01 18:36:53 +010077 /* Our memory regions are:
78 * 0 : PCI self config window
79 * 1 : PCI config window
80 * 2 : PCI IO window (realview_pci only)
81 */
Avi Kivity45de0942011-08-15 17:17:32 +030082 memory_region_init_io(&s->mem_config, &pci_vpb_config_ops, bus,
83 "pci-vpb-selfconfig", 0x1000000);
Avi Kivity750ecd42011-11-27 11:38:10 +020084 sysbus_init_mmio(dev, &s->mem_config);
Avi Kivity45de0942011-08-15 17:17:32 +030085 memory_region_init_io(&s->mem_config2, &pci_vpb_config_ops, bus,
86 "pci-vpb-config", 0x1000000);
Avi Kivity750ecd42011-11-27 11:38:10 +020087 sysbus_init_mmio(dev, &s->mem_config2);
Avi Kivity45de0942011-08-15 17:17:32 +030088 if (s->realview) {
89 isa_mmio_setup(&s->isa, 0x0100000);
Avi Kivity750ecd42011-11-27 11:38:10 +020090 sysbus_init_mmio(dev, &s->isa);
Avi Kivity45de0942011-08-15 17:17:32 +030091 }
92
Paul Brook0027b062009-05-14 22:35:08 +010093 pci_create_simple(bus, -1, "versatile_pci_host");
Gerd Hoffmann81a322d2009-08-14 10:36:05 +020094 return 0;
Paul Brook0027b062009-05-14 22:35:08 +010095}
96
Gerd Hoffmann81a322d2009-08-14 10:36:05 +020097static int pci_realview_init(SysBusDevice *dev)
Paul Brook0027b062009-05-14 22:35:08 +010098{
99 PCIVPBState *s = FROM_SYSBUS(PCIVPBState, dev);
100 s->realview = 1;
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200101 return pci_vpb_init(dev);
Paul Brook0027b062009-05-14 22:35:08 +0100102}
103
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200104static int versatile_pci_host_init(PCIDevice *d)
Paul Brook0027b062009-05-14 22:35:08 +0100105{
Michael S. Tsirkina408b1d2010-02-08 23:36:02 +0200106 pci_set_word(d->config + PCI_STATUS,
107 PCI_STATUS_66MHZ | PCI_STATUS_DEVSEL_MEDIUM);
Michael S. Tsirkin01764fe2010-02-08 23:33:33 +0200108 pci_set_byte(d->config + PCI_LATENCY_TIMER, 0x10);
Gerd Hoffmann81a322d2009-08-14 10:36:05 +0200109 return 0;
pbrook502a5392006-05-13 16:11:23 +0000110}
Paul Brook0027b062009-05-14 22:35:08 +0100111
Anthony Liguori40021f02011-12-04 12:22:06 -0600112static void versatile_pci_host_class_init(ObjectClass *klass, void *data)
113{
114 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
115
116 k->init = versatile_pci_host_init;
117 k->vendor_id = PCI_VENDOR_ID_XILINX;
118 k->device_id = PCI_DEVICE_ID_XILINX_XC2VP30;
119 k->class_id = PCI_CLASS_PROCESSOR_CO;
120}
121
Anthony Liguori39bffca2011-12-07 21:34:16 -0600122static TypeInfo versatile_pci_host_info = {
123 .name = "versatile_pci_host",
124 .parent = TYPE_PCI_DEVICE,
125 .instance_size = sizeof(PCIDevice),
126 .class_init = versatile_pci_host_class_init,
Gerd Hoffmann0aab0d32009-06-30 14:12:07 +0200127};
128
Anthony Liguori999e12b2012-01-24 13:12:29 -0600129static void pci_vpb_class_init(ObjectClass *klass, void *data)
130{
131 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
132
133 sdc->init = pci_vpb_init;
134}
135
Anthony Liguori39bffca2011-12-07 21:34:16 -0600136static TypeInfo pci_vpb_info = {
137 .name = "versatile_pci",
138 .parent = TYPE_SYS_BUS_DEVICE,
139 .instance_size = sizeof(PCIVPBState),
140 .class_init = pci_vpb_class_init,
Anthony Liguori999e12b2012-01-24 13:12:29 -0600141};
142
143static void pci_realview_class_init(ObjectClass *klass, void *data)
144{
145 SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
146
147 sdc->init = pci_realview_init;
148}
149
Anthony Liguori39bffca2011-12-07 21:34:16 -0600150static TypeInfo pci_realview_info = {
151 .name = "realview_pci",
152 .parent = TYPE_SYS_BUS_DEVICE,
153 .instance_size = sizeof(PCIVPBState),
154 .class_init = pci_realview_class_init,
Anthony Liguori999e12b2012-01-24 13:12:29 -0600155};
156
Andreas Färber83f7d432012-02-09 15:20:55 +0100157static void versatile_pci_register_types(void)
Paul Brook0027b062009-05-14 22:35:08 +0100158{
Anthony Liguori39bffca2011-12-07 21:34:16 -0600159 type_register_static(&pci_vpb_info);
160 type_register_static(&pci_realview_info);
161 type_register_static(&versatile_pci_host_info);
Paul Brook0027b062009-05-14 22:35:08 +0100162}
163
Andreas Färber83f7d432012-02-09 15:20:55 +0100164type_init(versatile_pci_register_types)