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ths81700282007-10-08 12:49:08 +00001/*
2 * CRIS emulation for qemu: main translation routines.
3 *
edgar_igl05ba7d52008-03-14 01:11:25 +00004 * Copyright (c) 2008 AXIS Communications AB
ths81700282007-10-08 12:49:08 +00005 * Written by Edgar E. Iglesias.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
20 */
21
edgar_iglb41f7df2008-05-02 22:16:17 +000022/*
23 * FIXME:
24 * The condition code translation is in desperate need of attention. It's slow
25 * and for system simulation it seems buggy. It sucks.
26 */
27
ths81700282007-10-08 12:49:08 +000028#include <stdarg.h>
29#include <stdlib.h>
30#include <stdio.h>
31#include <string.h>
32#include <inttypes.h>
33#include <assert.h>
34
35#include "cpu.h"
36#include "exec-all.h"
37#include "disas.h"
bellard57fec1f2008-02-01 10:50:11 +000038#include "tcg-op.h"
edgar_igl05ba7d52008-03-14 01:11:25 +000039#include "helper.h"
ths81700282007-10-08 12:49:08 +000040#include "crisv32-decode.h"
aurel32ca10f862008-04-11 21:35:42 +000041#include "qemu-common.h"
ths81700282007-10-08 12:49:08 +000042
43#define CRIS_STATS 0
44#if CRIS_STATS
45#define STATS(x) x
46#else
47#define STATS(x)
48#endif
49
50#define DISAS_CRIS 0
51#if DISAS_CRIS
52#define DIS(x) x
53#else
54#define DIS(x)
55#endif
56
edgar_iglb41f7df2008-05-02 22:16:17 +000057#define D(x)
ths81700282007-10-08 12:49:08 +000058#define BUG() (gen_BUG(dc, __FILE__, __LINE__))
59#define BUG_ON(x) ({if (x) BUG();})
60
edgar_igl4f400ab2008-02-28 09:37:58 +000061#define DISAS_SWI 5
62
ths81700282007-10-08 12:49:08 +000063/* Used by the decoder. */
64#define EXTRACT_FIELD(src, start, end) \
65 (((src) >> start) & ((1 << (end - start + 1)) - 1))
66
67#define CC_MASK_NZ 0xc
68#define CC_MASK_NZV 0xe
69#define CC_MASK_NZVC 0xf
70#define CC_MASK_RNZV 0x10e
71
edgar_igla825e702008-03-16 16:51:58 +000072TCGv cpu_env;
73TCGv cpu_T[2];
74TCGv cpu_R[16];
75TCGv cpu_PR[16];
76TCGv cc_src;
77TCGv cc_dest;
78TCGv cc_result;
79TCGv cc_op;
80TCGv cc_size;
81TCGv cc_mask;
edgar_igl05ba7d52008-03-14 01:11:25 +000082
edgar_iglb41f7df2008-05-02 22:16:17 +000083TCGv env_btarget;
84TCGv env_pc;
85
ths81700282007-10-08 12:49:08 +000086/* This is the state at translation time. */
87typedef struct DisasContext {
88 CPUState *env;
edgar_iglb41f7df2008-05-02 22:16:17 +000089 target_ulong pc, ppc;
ths81700282007-10-08 12:49:08 +000090
91 /* Decoder. */
92 uint32_t ir;
93 uint32_t opcode;
94 unsigned int op1;
95 unsigned int op2;
96 unsigned int zsize, zzsize;
97 unsigned int mode;
98 unsigned int postinc;
99
ths81700282007-10-08 12:49:08 +0000100 int update_cc;
101 int cc_op;
102 int cc_size;
103 uint32_t cc_mask;
edgar_iglb41f7df2008-05-02 22:16:17 +0000104 int flags_live; /* Wether or not $ccs is uptodate. */
105 int flagx_live; /* Wether or not flags_x has the x flag known at
106 translation time. */
ths81700282007-10-08 12:49:08 +0000107 int flags_x;
edgar_iglb41f7df2008-05-02 22:16:17 +0000108 int clear_x; /* Clear x after this insn? */
ths81700282007-10-08 12:49:08 +0000109
edgar_iglb41f7df2008-05-02 22:16:17 +0000110 int user; /* user or kernel mode. */
ths81700282007-10-08 12:49:08 +0000111 int is_jmp;
112 int dyn_jmp;
113
114 uint32_t delayed_pc;
115 int delayed_branch;
116 int bcc;
117 uint32_t condlabel;
118
119 struct TranslationBlock *tb;
120 int singlestep_enabled;
121} DisasContext;
122
123void cris_prepare_jmp (DisasContext *dc, uint32_t dst);
124static void gen_BUG(DisasContext *dc, char *file, int line)
125{
126 printf ("BUG: pc=%x %s %d\n", dc->pc, file, line);
127 fprintf (logfile, "BUG: pc=%x %s %d\n", dc->pc, file, line);
128 cpu_dump_state (dc->env, stdout, fprintf, 0);
129 fflush(NULL);
130 cris_prepare_jmp (dc, 0x70000000 + line);
131}
132
edgar_igla825e702008-03-16 16:51:58 +0000133const char *regnames[] =
134{
135 "$r0", "$r1", "$r2", "$r3",
136 "$r4", "$r5", "$r6", "$r7",
137 "$r8", "$r9", "$r10", "$r11",
138 "$r12", "$r13", "$sp", "$acr",
139};
140const char *pregnames[] =
141{
142 "$bz", "$vr", "$pid", "$srs",
143 "$wz", "$exs", "$eda", "$mof",
144 "$dz", "$ebp", "$erp", "$srp",
145 "$nrp", "$ccs", "$usp", "$spc",
146};
147
edgar_igl05ba7d52008-03-14 01:11:25 +0000148/* We need this table to handle preg-moves with implicit width. */
149int preg_sizes[] = {
150 1, /* bz. */
151 1, /* vr. */
152 4, /* pid. */
153 1, /* srs. */
154 2, /* wz. */
155 4, 4, 4,
156 4, 4, 4, 4,
157 4, 4, 4, 4,
158};
159
160#define t_gen_mov_TN_env(tn, member) \
edgar_igl3157a0a2008-03-15 20:45:05 +0000161 _t_gen_mov_TN_env((tn), offsetof(CPUState, member))
edgar_igl05ba7d52008-03-14 01:11:25 +0000162#define t_gen_mov_env_TN(member, tn) \
edgar_igl3157a0a2008-03-15 20:45:05 +0000163 _t_gen_mov_env_TN(offsetof(CPUState, member), (tn))
edgar_igl05ba7d52008-03-14 01:11:25 +0000164
edgar_iglb41f7df2008-05-02 22:16:17 +0000165static inline void t_gen_mov_TN_reg(TCGv tn, int r)
166{
167 if (r < 0 || r > 15)
168 fprintf(stderr, "wrong register read $r%d\n", r);
169 tcg_gen_mov_tl(tn, cpu_R[r]);
170}
171static inline void t_gen_mov_reg_TN(int r, TCGv tn)
172{
173 if (r < 0 || r > 15)
174 fprintf(stderr, "wrong register write $r%d\n", r);
175 tcg_gen_mov_tl(cpu_R[r], tn);
176}
edgar_igl05ba7d52008-03-14 01:11:25 +0000177
178static inline void _t_gen_mov_TN_env(TCGv tn, int offset)
179{
edgar_iglb41f7df2008-05-02 22:16:17 +0000180 if (offset > sizeof (CPUState))
181 fprintf(stderr, "wrong load from env from off=%d\n", offset);
edgar_igl05ba7d52008-03-14 01:11:25 +0000182 tcg_gen_ld_tl(tn, cpu_env, offset);
183}
184static inline void _t_gen_mov_env_TN(int offset, TCGv tn)
185{
edgar_iglb41f7df2008-05-02 22:16:17 +0000186 if (offset > sizeof (CPUState))
187 fprintf(stderr, "wrong store to env at off=%d\n", offset);
edgar_igl05ba7d52008-03-14 01:11:25 +0000188 tcg_gen_st_tl(tn, cpu_env, offset);
189}
190
191static inline void t_gen_mov_TN_preg(TCGv tn, int r)
192{
edgar_iglb41f7df2008-05-02 22:16:17 +0000193 if (r < 0 || r > 15)
194 fprintf(stderr, "wrong register read $p%d\n", r);
edgar_igl05ba7d52008-03-14 01:11:25 +0000195 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
edgar_igl3157a0a2008-03-15 20:45:05 +0000196 tcg_gen_mov_tl(tn, tcg_const_tl(0));
edgar_igl05ba7d52008-03-14 01:11:25 +0000197 else if (r == PR_VR)
edgar_igl3157a0a2008-03-15 20:45:05 +0000198 tcg_gen_mov_tl(tn, tcg_const_tl(32));
edgar_iglb41f7df2008-05-02 22:16:17 +0000199 else if (r == PR_EXS) {
200 printf("read from EXS!\n");
201 tcg_gen_mov_tl(tn, cpu_PR[r]);
202 }
203 else if (r == PR_EDA) {
204 printf("read from EDA!\n");
205 tcg_gen_mov_tl(tn, cpu_PR[r]);
206 }
edgar_igl05ba7d52008-03-14 01:11:25 +0000207 else
edgar_igla825e702008-03-16 16:51:58 +0000208 tcg_gen_mov_tl(tn, cpu_PR[r]);
edgar_igl05ba7d52008-03-14 01:11:25 +0000209}
210static inline void t_gen_mov_preg_TN(int r, TCGv tn)
211{
edgar_iglb41f7df2008-05-02 22:16:17 +0000212 if (r < 0 || r > 15)
213 fprintf(stderr, "wrong register write $p%d\n", r);
edgar_igl05ba7d52008-03-14 01:11:25 +0000214 if (r == PR_BZ || r == PR_WZ || r == PR_DZ)
215 return;
edgar_iglb41f7df2008-05-02 22:16:17 +0000216 else if (r == PR_SRS)
217 tcg_gen_andi_tl(cpu_PR[r], tn, 3);
218 else {
219 if (r == PR_PID) {
220 tcg_gen_helper_0_0(helper_tlb_flush);
221 }
edgar_igla825e702008-03-16 16:51:58 +0000222 tcg_gen_mov_tl(cpu_PR[r], tn);
edgar_iglb41f7df2008-05-02 22:16:17 +0000223 }
edgar_igl05ba7d52008-03-14 01:11:25 +0000224}
225
226static inline void t_gen_mov_TN_im(TCGv tn, int32_t val)
227{
228 tcg_gen_movi_tl(tn, val);
229}
230
231static void t_gen_lsl(TCGv d, TCGv a, TCGv b)
232{
233 int l1;
234
235 l1 = gen_new_label();
236 /* Speculative shift. */
237 tcg_gen_shl_tl(d, a, b);
edgar_igl3157a0a2008-03-15 20:45:05 +0000238 tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
edgar_igl05ba7d52008-03-14 01:11:25 +0000239 /* Clear dst if shift operands were to large. */
240 tcg_gen_movi_tl(d, 0);
241 gen_set_label(l1);
242}
243
244static void t_gen_lsr(TCGv d, TCGv a, TCGv b)
245{
246 int l1;
247
248 l1 = gen_new_label();
249 /* Speculative shift. */
250 tcg_gen_shr_tl(d, a, b);
edgar_igl3157a0a2008-03-15 20:45:05 +0000251 tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
edgar_igl05ba7d52008-03-14 01:11:25 +0000252 /* Clear dst if shift operands were to large. */
253 tcg_gen_movi_tl(d, 0);
254 gen_set_label(l1);
255}
256
257static void t_gen_asr(TCGv d, TCGv a, TCGv b)
258{
259 int l1;
260
261 l1 = gen_new_label();
262 /* Speculative shift. */
263 tcg_gen_sar_tl(d, a, b);
edgar_igl3157a0a2008-03-15 20:45:05 +0000264 tcg_gen_brcond_tl(TCG_COND_LE, b, tcg_const_tl(31), l1);
edgar_igl05ba7d52008-03-14 01:11:25 +0000265 /* Clear dst if shift operands were to large. */
edgar_iglb41f7df2008-05-02 22:16:17 +0000266 tcg_gen_sar_tl(d, a, tcg_const_tl(30));
edgar_igl05ba7d52008-03-14 01:11:25 +0000267 gen_set_label(l1);
268}
269
edgar_igl3157a0a2008-03-15 20:45:05 +0000270/* 64-bit signed mul, lower result in d and upper in d2. */
271static void t_gen_muls(TCGv d, TCGv d2, TCGv a, TCGv b)
272{
273 TCGv t0, t1;
274
275 t0 = tcg_temp_new(TCG_TYPE_I64);
276 t1 = tcg_temp_new(TCG_TYPE_I64);
277
278 tcg_gen_ext32s_i64(t0, a);
279 tcg_gen_ext32s_i64(t1, b);
280 tcg_gen_mul_i64(t0, t0, t1);
281
282 tcg_gen_trunc_i64_i32(d, t0);
283 tcg_gen_shri_i64(t0, t0, 32);
284 tcg_gen_trunc_i64_i32(d2, t0);
edgar_iglb41f7df2008-05-02 22:16:17 +0000285
286 tcg_gen_discard_i64(t0);
287 tcg_gen_discard_i64(t1);
edgar_igl3157a0a2008-03-15 20:45:05 +0000288}
289
290/* 64-bit unsigned muls, lower result in d and upper in d2. */
291static void t_gen_mulu(TCGv d, TCGv d2, TCGv a, TCGv b)
292{
293 TCGv t0, t1;
294
295 t0 = tcg_temp_new(TCG_TYPE_I64);
296 t1 = tcg_temp_new(TCG_TYPE_I64);
297
298 tcg_gen_extu_i32_i64(t0, a);
299 tcg_gen_extu_i32_i64(t1, b);
300 tcg_gen_mul_i64(t0, t0, t1);
301
302 tcg_gen_trunc_i64_i32(d, t0);
303 tcg_gen_shri_i64(t0, t0, 32);
304 tcg_gen_trunc_i64_i32(d2, t0);
edgar_iglb41f7df2008-05-02 22:16:17 +0000305
306 tcg_gen_discard_i64(t0);
307 tcg_gen_discard_i64(t1);
edgar_igl3157a0a2008-03-15 20:45:05 +0000308}
309
310/* Extended arithmetics on CRIS. */
311static inline void t_gen_add_flag(TCGv d, int flag)
312{
313 TCGv c;
314
315 c = tcg_temp_new(TCG_TYPE_TL);
316 t_gen_mov_TN_preg(c, PR_CCS);
317 /* Propagate carry into d. */
318 tcg_gen_andi_tl(c, c, 1 << flag);
319 if (flag)
320 tcg_gen_shri_tl(c, c, flag);
321 tcg_gen_add_tl(d, d, c);
edgar_iglb41f7df2008-05-02 22:16:17 +0000322 tcg_gen_discard_tl(c);
edgar_igl3157a0a2008-03-15 20:45:05 +0000323}
324
325static inline void t_gen_addx_carry(TCGv d)
326{
327 TCGv x, c;
328
329 x = tcg_temp_new(TCG_TYPE_TL);
330 c = tcg_temp_new(TCG_TYPE_TL);
331 t_gen_mov_TN_preg(x, PR_CCS);
332 tcg_gen_mov_tl(c, x);
333
334 /* Propagate carry into d if X is set. Branch free. */
335 tcg_gen_andi_tl(c, c, C_FLAG);
336 tcg_gen_andi_tl(x, x, X_FLAG);
337 tcg_gen_shri_tl(x, x, 4);
338
339 tcg_gen_and_tl(x, x, c);
340 tcg_gen_add_tl(d, d, x);
edgar_iglb41f7df2008-05-02 22:16:17 +0000341 tcg_gen_discard_tl(x);
342 tcg_gen_discard_tl(c);
edgar_igl3157a0a2008-03-15 20:45:05 +0000343}
344
345static inline void t_gen_subx_carry(TCGv d)
346{
347 TCGv x, c;
348
349 x = tcg_temp_new(TCG_TYPE_TL);
350 c = tcg_temp_new(TCG_TYPE_TL);
351 t_gen_mov_TN_preg(x, PR_CCS);
352 tcg_gen_mov_tl(c, x);
353
354 /* Propagate carry into d if X is set. Branch free. */
355 tcg_gen_andi_tl(c, c, C_FLAG);
356 tcg_gen_andi_tl(x, x, X_FLAG);
357 tcg_gen_shri_tl(x, x, 4);
358
359 tcg_gen_and_tl(x, x, c);
360 tcg_gen_sub_tl(d, d, x);
edgar_iglb41f7df2008-05-02 22:16:17 +0000361 tcg_gen_discard_tl(x);
362 tcg_gen_discard_tl(c);
edgar_igl3157a0a2008-03-15 20:45:05 +0000363}
364
365/* Swap the two bytes within each half word of the s operand.
366 T0 = ((T0 << 8) & 0xff00ff00) | ((T0 >> 8) & 0x00ff00ff) */
367static inline void t_gen_swapb(TCGv d, TCGv s)
368{
369 TCGv t, org_s;
370
371 t = tcg_temp_new(TCG_TYPE_TL);
372 org_s = tcg_temp_new(TCG_TYPE_TL);
373
374 /* d and s may refer to the same object. */
375 tcg_gen_mov_tl(org_s, s);
376 tcg_gen_shli_tl(t, org_s, 8);
377 tcg_gen_andi_tl(d, t, 0xff00ff00);
378 tcg_gen_shri_tl(t, org_s, 8);
379 tcg_gen_andi_tl(t, t, 0x00ff00ff);
380 tcg_gen_or_tl(d, d, t);
edgar_iglb41f7df2008-05-02 22:16:17 +0000381 tcg_gen_discard_tl(t);
382 tcg_gen_discard_tl(org_s);
edgar_igl3157a0a2008-03-15 20:45:05 +0000383}
384
385/* Swap the halfwords of the s operand. */
386static inline void t_gen_swapw(TCGv d, TCGv s)
387{
388 TCGv t;
389 /* d and s refer the same object. */
390 t = tcg_temp_new(TCG_TYPE_TL);
391 tcg_gen_mov_tl(t, s);
392 tcg_gen_shli_tl(d, t, 16);
393 tcg_gen_shri_tl(t, t, 16);
394 tcg_gen_or_tl(d, d, t);
edgar_iglb41f7df2008-05-02 22:16:17 +0000395 tcg_gen_discard_tl(t);
edgar_igl3157a0a2008-03-15 20:45:05 +0000396}
397
398/* Reverse the within each byte.
399 T0 = (((T0 << 7) & 0x80808080) |
400 ((T0 << 5) & 0x40404040) |
401 ((T0 << 3) & 0x20202020) |
402 ((T0 << 1) & 0x10101010) |
403 ((T0 >> 1) & 0x08080808) |
404 ((T0 >> 3) & 0x04040404) |
405 ((T0 >> 5) & 0x02020202) |
406 ((T0 >> 7) & 0x01010101));
407 */
408static inline void t_gen_swapr(TCGv d, TCGv s)
409{
410 struct {
411 int shift; /* LSL when positive, LSR when negative. */
412 uint32_t mask;
413 } bitrev [] = {
414 {7, 0x80808080},
415 {5, 0x40404040},
416 {3, 0x20202020},
417 {1, 0x10101010},
418 {-1, 0x08080808},
419 {-3, 0x04040404},
420 {-5, 0x02020202},
421 {-7, 0x01010101}
422 };
423 int i;
424 TCGv t, org_s;
425
426 /* d and s refer the same object. */
427 t = tcg_temp_new(TCG_TYPE_TL);
428 org_s = tcg_temp_new(TCG_TYPE_TL);
429 tcg_gen_mov_tl(org_s, s);
430
431 tcg_gen_shli_tl(t, org_s, bitrev[0].shift);
432 tcg_gen_andi_tl(d, t, bitrev[0].mask);
433 for (i = 1; i < sizeof bitrev / sizeof bitrev[0]; i++) {
434 if (bitrev[i].shift >= 0) {
435 tcg_gen_shli_tl(t, org_s, bitrev[i].shift);
436 } else {
437 tcg_gen_shri_tl(t, org_s, -bitrev[i].shift);
438 }
439 tcg_gen_andi_tl(t, t, bitrev[i].mask);
440 tcg_gen_or_tl(d, d, t);
441 }
edgar_iglb41f7df2008-05-02 22:16:17 +0000442 tcg_gen_discard_tl(t);
443 tcg_gen_discard_tl(org_s);
edgar_igl3157a0a2008-03-15 20:45:05 +0000444}
445
ths81700282007-10-08 12:49:08 +0000446static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
447{
448 TranslationBlock *tb;
449 tb = dc->tb;
450 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK)) {
edgar_igl05ba7d52008-03-14 01:11:25 +0000451 tcg_gen_goto_tb(n);
edgar_igl50cfa952008-05-03 08:36:16 +0000452 tcg_gen_movi_tl(env_pc, dest);
edgar_igl05ba7d52008-03-14 01:11:25 +0000453 tcg_gen_exit_tb((long)tb + n);
ths81700282007-10-08 12:49:08 +0000454 } else {
edgar_igl50cfa952008-05-03 08:36:16 +0000455 tcg_gen_mov_tl(env_pc, cpu_T[0]);
edgar_igl05ba7d52008-03-14 01:11:25 +0000456 tcg_gen_exit_tb(0);
ths81700282007-10-08 12:49:08 +0000457 }
ths81700282007-10-08 12:49:08 +0000458}
459
460/* Sign extend at translation time. */
461static int sign_extend(unsigned int val, unsigned int width)
462{
463 int sval;
464
465 /* LSL. */
466 val <<= 31 - width;
467 sval = val;
468 /* ASR. */
469 sval >>= 31 - width;
470 return sval;
471}
472
edgar_igl05ba7d52008-03-14 01:11:25 +0000473static inline void cris_clear_x_flag(DisasContext *dc)
474{
edgar_iglb41f7df2008-05-02 22:16:17 +0000475 if (!dc->flagx_live
476 || (dc->flagx_live && dc->flags_x)
477 || dc->cc_op != CC_OP_FLAGS)
478 tcg_gen_andi_i32(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~X_FLAG);
479 dc->flagx_live = 1;
480 dc->flags_x = 0;
edgar_igl05ba7d52008-03-14 01:11:25 +0000481}
482
ths81700282007-10-08 12:49:08 +0000483static void cris_evaluate_flags(DisasContext *dc)
484{
485 if (!dc->flags_live) {
edgar_iglb41f7df2008-05-02 22:16:17 +0000486 tcg_gen_movi_tl(cc_op, dc->cc_op);
487 tcg_gen_movi_tl(cc_size, dc->cc_size);
488 tcg_gen_movi_tl(cc_mask, dc->cc_mask);
489
ths81700282007-10-08 12:49:08 +0000490 switch (dc->cc_op)
491 {
492 case CC_OP_MCP:
edgar_iglb41f7df2008-05-02 22:16:17 +0000493 tcg_gen_helper_0_0(helper_evaluate_flags_mcp);
ths81700282007-10-08 12:49:08 +0000494 break;
495 case CC_OP_MULS:
edgar_iglb41f7df2008-05-02 22:16:17 +0000496 tcg_gen_helper_0_0(helper_evaluate_flags_muls);
ths81700282007-10-08 12:49:08 +0000497 break;
498 case CC_OP_MULU:
edgar_iglb41f7df2008-05-02 22:16:17 +0000499 tcg_gen_helper_0_0(helper_evaluate_flags_mulu);
ths81700282007-10-08 12:49:08 +0000500 break;
501 case CC_OP_MOVE:
502 switch (dc->cc_size)
503 {
504 case 4:
edgar_iglb41f7df2008-05-02 22:16:17 +0000505 tcg_gen_helper_0_0(helper_evaluate_flags_move_4);
ths81700282007-10-08 12:49:08 +0000506 break;
507 case 2:
edgar_iglb41f7df2008-05-02 22:16:17 +0000508 tcg_gen_helper_0_0(helper_evaluate_flags_move_2);
ths81700282007-10-08 12:49:08 +0000509 break;
510 default:
edgar_iglb41f7df2008-05-02 22:16:17 +0000511 tcg_gen_helper_0_0(helper_evaluate_flags);
ths81700282007-10-08 12:49:08 +0000512 break;
513 }
514 break;
edgar_iglb41f7df2008-05-02 22:16:17 +0000515 case CC_OP_FLAGS:
516 /* live. */
517 break;
ths81700282007-10-08 12:49:08 +0000518 default:
519 {
520 switch (dc->cc_size)
521 {
522 case 4:
edgar_iglb41f7df2008-05-02 22:16:17 +0000523 tcg_gen_helper_0_0(helper_evaluate_flags_alu_4);
ths81700282007-10-08 12:49:08 +0000524 break;
525 default:
edgar_iglb41f7df2008-05-02 22:16:17 +0000526 tcg_gen_helper_0_0(helper_evaluate_flags);
ths81700282007-10-08 12:49:08 +0000527 break;
528 }
529 }
530 break;
531 }
532 dc->flags_live = 1;
533 }
534}
535
536static void cris_cc_mask(DisasContext *dc, unsigned int mask)
537{
538 uint32_t ovl;
539
balrogfd560592008-01-14 03:18:30 +0000540 /* Check if we need to evaluate the condition codes due to
541 CC overlaying. */
ths81700282007-10-08 12:49:08 +0000542 ovl = (dc->cc_mask ^ mask) & ~mask;
543 if (ovl) {
544 /* TODO: optimize this case. It trigs all the time. */
545 cris_evaluate_flags (dc);
546 }
547 dc->cc_mask = mask;
ths81700282007-10-08 12:49:08 +0000548 dc->update_cc = 1;
edgar_igla825e702008-03-16 16:51:58 +0000549
ths81700282007-10-08 12:49:08 +0000550 if (mask == 0)
551 dc->update_cc = 0;
edgar_igla825e702008-03-16 16:51:58 +0000552 else
ths81700282007-10-08 12:49:08 +0000553 dc->flags_live = 0;
ths81700282007-10-08 12:49:08 +0000554}
555
edgar_iglb41f7df2008-05-02 22:16:17 +0000556static void cris_update_cc_op(DisasContext *dc, int op, int size)
ths81700282007-10-08 12:49:08 +0000557{
558 dc->cc_op = op;
ths81700282007-10-08 12:49:08 +0000559 dc->cc_size = size;
edgar_iglb41f7df2008-05-02 22:16:17 +0000560 dc->flags_live = 0;
ths81700282007-10-08 12:49:08 +0000561}
562
563/* op is the operation.
564 T0, T1 are the operands.
565 dst is the destination reg.
566*/
567static void crisv32_alu_op(DisasContext *dc, int op, int rd, int size)
568{
569 int writeback = 1;
570 if (dc->update_cc) {
edgar_iglb41f7df2008-05-02 22:16:17 +0000571 cris_update_cc_op(dc, op, size);
edgar_igla825e702008-03-16 16:51:58 +0000572 tcg_gen_mov_tl(cc_dest, cpu_T[0]);
edgar_igl3157a0a2008-03-15 20:45:05 +0000573
574 /* FIXME: This shouldn't be needed. But we don't pass the
575 tests without it. Investigate. */
576 t_gen_mov_env_TN(cc_x_live, tcg_const_tl(dc->flagx_live));
577 t_gen_mov_env_TN(cc_x, tcg_const_tl(dc->flags_x));
ths81700282007-10-08 12:49:08 +0000578 }
579
580 /* Emit the ALU insns. */
581 switch (op)
582 {
583 case CC_OP_ADD:
edgar_igl05ba7d52008-03-14 01:11:25 +0000584 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
ths81700282007-10-08 12:49:08 +0000585 /* Extended arithmetics. */
edgar_igl3157a0a2008-03-15 20:45:05 +0000586 t_gen_addx_carry(cpu_T[0]);
ths81700282007-10-08 12:49:08 +0000587 break;
588 case CC_OP_ADDC:
edgar_igl05ba7d52008-03-14 01:11:25 +0000589 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
edgar_igl3157a0a2008-03-15 20:45:05 +0000590 t_gen_add_flag(cpu_T[0], 0); /* C_FLAG. */
ths81700282007-10-08 12:49:08 +0000591 break;
592 case CC_OP_MCP:
edgar_igl05ba7d52008-03-14 01:11:25 +0000593 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
edgar_igl3157a0a2008-03-15 20:45:05 +0000594 t_gen_add_flag(cpu_T[0], 8); /* R_FLAG. */
ths81700282007-10-08 12:49:08 +0000595 break;
596 case CC_OP_SUB:
edgar_igl3157a0a2008-03-15 20:45:05 +0000597 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
edgar_igl05ba7d52008-03-14 01:11:25 +0000598 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
edgar_igl3157a0a2008-03-15 20:45:05 +0000599 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
ths81700282007-10-08 12:49:08 +0000600 /* CRIS flag evaluation needs ~src. */
edgar_igl3157a0a2008-03-15 20:45:05 +0000601 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
ths81700282007-10-08 12:49:08 +0000602
603 /* Extended arithmetics. */
edgar_igl3157a0a2008-03-15 20:45:05 +0000604 t_gen_subx_carry(cpu_T[0]);
ths81700282007-10-08 12:49:08 +0000605 break;
606 case CC_OP_MOVE:
edgar_igl05ba7d52008-03-14 01:11:25 +0000607 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
ths81700282007-10-08 12:49:08 +0000608 break;
609 case CC_OP_OR:
edgar_igl05ba7d52008-03-14 01:11:25 +0000610 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
ths81700282007-10-08 12:49:08 +0000611 break;
612 case CC_OP_AND:
edgar_igl05ba7d52008-03-14 01:11:25 +0000613 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
ths81700282007-10-08 12:49:08 +0000614 break;
615 case CC_OP_XOR:
edgar_igl05ba7d52008-03-14 01:11:25 +0000616 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
ths81700282007-10-08 12:49:08 +0000617 break;
618 case CC_OP_LSL:
edgar_igl05ba7d52008-03-14 01:11:25 +0000619 t_gen_lsl(cpu_T[0], cpu_T[0], cpu_T[1]);
ths81700282007-10-08 12:49:08 +0000620 break;
621 case CC_OP_LSR:
edgar_igl05ba7d52008-03-14 01:11:25 +0000622 t_gen_lsr(cpu_T[0], cpu_T[0], cpu_T[1]);
ths81700282007-10-08 12:49:08 +0000623 break;
624 case CC_OP_ASR:
edgar_igl05ba7d52008-03-14 01:11:25 +0000625 t_gen_asr(cpu_T[0], cpu_T[0], cpu_T[1]);
ths81700282007-10-08 12:49:08 +0000626 break;
627 case CC_OP_NEG:
edgar_igl3157a0a2008-03-15 20:45:05 +0000628 /* Hopefully the TCG backend recognizes this pattern
629 and makes a real neg out of it. */
630 tcg_gen_sub_tl(cpu_T[0], tcg_const_tl(0), cpu_T[1]);
ths81700282007-10-08 12:49:08 +0000631 /* Extended arithmetics. */
edgar_igl3157a0a2008-03-15 20:45:05 +0000632 t_gen_subx_carry(cpu_T[0]);
ths81700282007-10-08 12:49:08 +0000633 break;
634 case CC_OP_LZ:
635 gen_op_lz_T0_T1();
636 break;
637 case CC_OP_BTST:
638 gen_op_btst_T0_T1();
639 writeback = 0;
640 break;
641 case CC_OP_MULS:
edgar_igl3157a0a2008-03-15 20:45:05 +0000642 {
643 TCGv mof;
644 mof = tcg_temp_new(TCG_TYPE_TL);
645 t_gen_muls(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
646 t_gen_mov_preg_TN(PR_MOF, mof);
edgar_iglb41f7df2008-05-02 22:16:17 +0000647 tcg_gen_discard_tl(mof);
edgar_igl3157a0a2008-03-15 20:45:05 +0000648 }
649 break;
ths81700282007-10-08 12:49:08 +0000650 case CC_OP_MULU:
edgar_igl3157a0a2008-03-15 20:45:05 +0000651 {
652 TCGv mof;
653 mof = tcg_temp_new(TCG_TYPE_TL);
654 t_gen_mulu(cpu_T[0], mof, cpu_T[0], cpu_T[1]);
655 t_gen_mov_preg_TN(PR_MOF, mof);
edgar_iglb41f7df2008-05-02 22:16:17 +0000656 tcg_gen_discard_tl(mof);
edgar_igl3157a0a2008-03-15 20:45:05 +0000657 }
658 break;
ths81700282007-10-08 12:49:08 +0000659 case CC_OP_DSTEP:
660 gen_op_dstep_T0_T1();
661 break;
662 case CC_OP_BOUND:
edgar_igl3157a0a2008-03-15 20:45:05 +0000663 {
664 int l1;
665 l1 = gen_new_label();
666 tcg_gen_brcond_tl(TCG_COND_LEU,
667 cpu_T[0], cpu_T[1], l1);
668 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
669 gen_set_label(l1);
670 }
671 break;
ths81700282007-10-08 12:49:08 +0000672 case CC_OP_CMP:
edgar_igl3157a0a2008-03-15 20:45:05 +0000673 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
edgar_igl05ba7d52008-03-14 01:11:25 +0000674 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
ths81700282007-10-08 12:49:08 +0000675 /* CRIS flag evaluation needs ~src. */
edgar_igl3157a0a2008-03-15 20:45:05 +0000676 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
edgar_igl05ba7d52008-03-14 01:11:25 +0000677 /* CRIS flag evaluation needs ~src. */
edgar_igl3157a0a2008-03-15 20:45:05 +0000678 tcg_gen_xori_tl(cpu_T[1], cpu_T[1], -1);
ths81700282007-10-08 12:49:08 +0000679
680 /* Extended arithmetics. */
edgar_igl3157a0a2008-03-15 20:45:05 +0000681 t_gen_subx_carry(cpu_T[0]);
ths81700282007-10-08 12:49:08 +0000682 writeback = 0;
683 break;
684 default:
685 fprintf (logfile, "illegal ALU op.\n");
686 BUG();
687 break;
688 }
689
690 if (dc->update_cc)
edgar_igla825e702008-03-16 16:51:58 +0000691 tcg_gen_mov_tl(cc_src, cpu_T[1]);
ths81700282007-10-08 12:49:08 +0000692
693 if (size == 1)
edgar_igl05ba7d52008-03-14 01:11:25 +0000694 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
ths81700282007-10-08 12:49:08 +0000695 else if (size == 2)
edgar_igl05ba7d52008-03-14 01:11:25 +0000696 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
697
ths81700282007-10-08 12:49:08 +0000698 /* Writeback. */
699 if (writeback) {
700 if (size == 4)
edgar_igl05ba7d52008-03-14 01:11:25 +0000701 t_gen_mov_reg_TN(rd, cpu_T[0]);
ths81700282007-10-08 12:49:08 +0000702 else {
edgar_igl05ba7d52008-03-14 01:11:25 +0000703 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
704 t_gen_mov_TN_reg(cpu_T[0], rd);
ths81700282007-10-08 12:49:08 +0000705 if (size == 1)
edgar_igl05ba7d52008-03-14 01:11:25 +0000706 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xff);
ths81700282007-10-08 12:49:08 +0000707 else
edgar_igl05ba7d52008-03-14 01:11:25 +0000708 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], ~0xffff);
709 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
710 t_gen_mov_reg_TN(rd, cpu_T[0]);
711 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
ths81700282007-10-08 12:49:08 +0000712 }
713 }
714 if (dc->update_cc)
edgar_igla825e702008-03-16 16:51:58 +0000715 tcg_gen_mov_tl(cc_result, cpu_T[0]);
ths81700282007-10-08 12:49:08 +0000716
717 {
718 /* TODO: Optimize this. */
719 if (!dc->flagx_live)
720 cris_evaluate_flags(dc);
721 }
722}
723
724static int arith_cc(DisasContext *dc)
725{
726 if (dc->update_cc) {
727 switch (dc->cc_op) {
728 case CC_OP_ADD: return 1;
729 case CC_OP_SUB: return 1;
730 case CC_OP_LSL: return 1;
731 case CC_OP_LSR: return 1;
732 case CC_OP_ASR: return 1;
733 case CC_OP_CMP: return 1;
734 default:
735 return 0;
736 }
737 }
738 return 0;
739}
740
741static void gen_tst_cc (DisasContext *dc, int cond)
742{
743 int arith_opt;
744
745 /* TODO: optimize more condition codes. */
746 arith_opt = arith_cc(dc) && !dc->flags_live;
747 switch (cond) {
748 case CC_EQ:
749 if (arith_opt)
750 gen_op_tst_cc_eq_fast ();
751 else {
752 cris_evaluate_flags(dc);
753 gen_op_tst_cc_eq ();
754 }
755 break;
756 case CC_NE:
757 if (arith_opt)
758 gen_op_tst_cc_ne_fast ();
759 else {
760 cris_evaluate_flags(dc);
761 gen_op_tst_cc_ne ();
762 }
763 break;
764 case CC_CS:
765 cris_evaluate_flags(dc);
766 gen_op_tst_cc_cs ();
767 break;
768 case CC_CC:
769 cris_evaluate_flags(dc);
770 gen_op_tst_cc_cc ();
771 break;
772 case CC_VS:
773 cris_evaluate_flags(dc);
774 gen_op_tst_cc_vs ();
775 break;
776 case CC_VC:
777 cris_evaluate_flags(dc);
778 gen_op_tst_cc_vc ();
779 break;
780 case CC_PL:
781 if (arith_opt)
782 gen_op_tst_cc_pl_fast ();
783 else {
784 cris_evaluate_flags(dc);
785 gen_op_tst_cc_pl ();
786 }
787 break;
788 case CC_MI:
789 if (arith_opt)
790 gen_op_tst_cc_mi_fast ();
791 else {
792 cris_evaluate_flags(dc);
793 gen_op_tst_cc_mi ();
794 }
795 break;
796 case CC_LS:
797 cris_evaluate_flags(dc);
798 gen_op_tst_cc_ls ();
799 break;
800 case CC_HI:
801 cris_evaluate_flags(dc);
802 gen_op_tst_cc_hi ();
803 break;
804 case CC_GE:
805 cris_evaluate_flags(dc);
806 gen_op_tst_cc_ge ();
807 break;
808 case CC_LT:
809 cris_evaluate_flags(dc);
810 gen_op_tst_cc_lt ();
811 break;
812 case CC_GT:
813 cris_evaluate_flags(dc);
814 gen_op_tst_cc_gt ();
815 break;
816 case CC_LE:
817 cris_evaluate_flags(dc);
818 gen_op_tst_cc_le ();
819 break;
820 case CC_P:
821 cris_evaluate_flags(dc);
822 gen_op_tst_cc_p ();
823 break;
824 case CC_A:
825 cris_evaluate_flags(dc);
826 gen_op_movl_T0_im (1);
827 break;
828 default:
829 BUG();
830 break;
831 };
832}
833
834static void cris_prepare_cc_branch (DisasContext *dc, int offset, int cond)
835{
836 /* This helps us re-schedule the micro-code to insns in delay-slots
837 before the actual jump. */
838 dc->delayed_branch = 2;
839 dc->delayed_pc = dc->pc + offset;
840 dc->bcc = cond;
841 if (cond != CC_A)
842 {
843 gen_tst_cc (dc, cond);
844 gen_op_evaluate_bcc ();
845 }
edgar_iglb41f7df2008-05-02 22:16:17 +0000846 tcg_gen_movi_tl(env_btarget, dc->delayed_pc);
ths81700282007-10-08 12:49:08 +0000847}
848
edgar_iglb41f7df2008-05-02 22:16:17 +0000849
ths81700282007-10-08 12:49:08 +0000850/* Dynamic jumps, when the dest is in a live reg for example. */
851void cris_prepare_dyn_jmp (DisasContext *dc)
852{
853 /* This helps us re-schedule the micro-code to insns in delay-slots
854 before the actual jump. */
855 dc->delayed_branch = 2;
856 dc->dyn_jmp = 1;
857 dc->bcc = CC_A;
858}
859
860void cris_prepare_jmp (DisasContext *dc, uint32_t dst)
861{
862 /* This helps us re-schedule the micro-code to insns in delay-slots
863 before the actual jump. */
864 dc->delayed_branch = 2;
865 dc->delayed_pc = dst;
866 dc->dyn_jmp = 0;
867 dc->bcc = CC_A;
868}
869
edgar_iglb41f7df2008-05-02 22:16:17 +0000870void gen_load(DisasContext *dc, TCGv dst, TCGv addr,
871 unsigned int size, int sign)
ths81700282007-10-08 12:49:08 +0000872{
edgar_iglb41f7df2008-05-02 22:16:17 +0000873 int mem_index = cpu_mmu_index(dc->env);
874
875 /* FIXME: qemu_ld does not act as a barrier? */
876 tcg_gen_helper_0_0(helper_dummy);
877 cris_evaluate_flags(dc);
ths81700282007-10-08 12:49:08 +0000878 if (size == 1) {
879 if (sign)
edgar_iglb41f7df2008-05-02 22:16:17 +0000880 tcg_gen_qemu_ld8s(dst, addr, mem_index);
ths81700282007-10-08 12:49:08 +0000881 else
edgar_iglb41f7df2008-05-02 22:16:17 +0000882 tcg_gen_qemu_ld8u(dst, addr, mem_index);
ths81700282007-10-08 12:49:08 +0000883 }
884 else if (size == 2) {
885 if (sign)
edgar_iglb41f7df2008-05-02 22:16:17 +0000886 tcg_gen_qemu_ld16s(dst, addr, mem_index);
ths81700282007-10-08 12:49:08 +0000887 else
edgar_iglb41f7df2008-05-02 22:16:17 +0000888 tcg_gen_qemu_ld16u(dst, addr, mem_index);
ths81700282007-10-08 12:49:08 +0000889 }
890 else {
edgar_iglb41f7df2008-05-02 22:16:17 +0000891 tcg_gen_qemu_ld32s(dst, addr, mem_index);
ths81700282007-10-08 12:49:08 +0000892 }
893}
894
895void gen_store_T0_T1 (DisasContext *dc, unsigned int size)
896{
edgar_iglb41f7df2008-05-02 22:16:17 +0000897 int mem_index = cpu_mmu_index(dc->env);
898
899 /* FIXME: qemu_st does not act as a barrier? */
900 tcg_gen_helper_0_0(helper_dummy);
901 cris_evaluate_flags(dc);
902
ths81700282007-10-08 12:49:08 +0000903 /* Remember, operands are flipped. CRIS has reversed order. */
edgar_iglb41f7df2008-05-02 22:16:17 +0000904 if (size == 1)
905 tcg_gen_qemu_st8(cpu_T[1], cpu_T[0], mem_index);
906 else if (size == 2)
907 tcg_gen_qemu_st16(cpu_T[1], cpu_T[0], mem_index);
ths81700282007-10-08 12:49:08 +0000908 else
edgar_iglb41f7df2008-05-02 22:16:17 +0000909 tcg_gen_qemu_st32(cpu_T[1], cpu_T[0], mem_index);
ths81700282007-10-08 12:49:08 +0000910}
911
edgar_igl05ba7d52008-03-14 01:11:25 +0000912static inline void t_gen_sext(TCGv d, TCGv s, int size)
ths81700282007-10-08 12:49:08 +0000913{
914 if (size == 1)
edgar_igl05ba7d52008-03-14 01:11:25 +0000915 tcg_gen_ext8s_i32(d, s);
ths81700282007-10-08 12:49:08 +0000916 else if (size == 2)
edgar_igl05ba7d52008-03-14 01:11:25 +0000917 tcg_gen_ext16s_i32(d, s);
edgar_igl50cfa952008-05-03 08:36:16 +0000918 else
919 tcg_gen_mov_tl(d, s);
ths81700282007-10-08 12:49:08 +0000920}
921
edgar_igl05ba7d52008-03-14 01:11:25 +0000922static inline void t_gen_zext(TCGv d, TCGv s, int size)
ths81700282007-10-08 12:49:08 +0000923{
edgar_igl05ba7d52008-03-14 01:11:25 +0000924 /* TCG-FIXME: this is not optimal. Many archs have fast zext insns. */
ths81700282007-10-08 12:49:08 +0000925 if (size == 1)
edgar_igl05ba7d52008-03-14 01:11:25 +0000926 tcg_gen_andi_i32(d, s, 0xff);
ths81700282007-10-08 12:49:08 +0000927 else if (size == 2)
edgar_igl05ba7d52008-03-14 01:11:25 +0000928 tcg_gen_andi_i32(d, s, 0xffff);
edgar_igl50cfa952008-05-03 08:36:16 +0000929 else
930 tcg_gen_mov_tl(d, s);
ths81700282007-10-08 12:49:08 +0000931}
932
933#if DISAS_CRIS
934static char memsize_char(int size)
935{
936 switch (size)
937 {
938 case 1: return 'b'; break;
939 case 2: return 'w'; break;
940 case 4: return 'd'; break;
941 default:
942 return 'x';
943 break;
944 }
945}
946#endif
947
948static unsigned int memsize_z(DisasContext *dc)
949{
950 return dc->zsize + 1;
951}
952
953static unsigned int memsize_zz(DisasContext *dc)
954{
955 switch (dc->zzsize)
956 {
957 case 0: return 1;
958 case 1: return 2;
959 default:
960 return 4;
961 }
962}
963
edgar_iglc7d05692008-05-03 06:54:52 +0000964static inline void do_postinc (DisasContext *dc, int size)
ths81700282007-10-08 12:49:08 +0000965{
edgar_iglc7d05692008-05-03 06:54:52 +0000966 if (dc->postinc)
967 tcg_gen_addi_tl(cpu_R[dc->op1], cpu_R[dc->op1], size);
ths81700282007-10-08 12:49:08 +0000968}
969
970
971static void dec_prep_move_r(DisasContext *dc, int rs, int rd,
972 int size, int s_ext)
973{
ths81700282007-10-08 12:49:08 +0000974 if (s_ext)
edgar_igl50cfa952008-05-03 08:36:16 +0000975 t_gen_sext(cpu_T[1], cpu_R[rs], size);
ths81700282007-10-08 12:49:08 +0000976 else
edgar_igl50cfa952008-05-03 08:36:16 +0000977 t_gen_zext(cpu_T[1], cpu_R[rs], size);
ths81700282007-10-08 12:49:08 +0000978}
979
980/* Prepare T0 and T1 for a register alu operation.
981 s_ext decides if the operand1 should be sign-extended or zero-extended when
982 needed. */
983static void dec_prep_alu_r(DisasContext *dc, int rs, int rd,
984 int size, int s_ext)
985{
986 dec_prep_move_r(dc, rs, rd, size, s_ext);
987
ths81700282007-10-08 12:49:08 +0000988 if (s_ext)
edgar_igl50cfa952008-05-03 08:36:16 +0000989 t_gen_sext(cpu_T[0], cpu_R[rd], size);
ths81700282007-10-08 12:49:08 +0000990 else
edgar_igl50cfa952008-05-03 08:36:16 +0000991 t_gen_zext(cpu_T[0], cpu_R[rd], size);
ths81700282007-10-08 12:49:08 +0000992}
993
994/* Prepare T0 and T1 for a memory + alu operation.
995 s_ext decides if the operand1 should be sign-extended or zero-extended when
996 needed. */
997static int dec_prep_alu_m(DisasContext *dc, int s_ext, int memsize)
998{
999 unsigned int rs, rd;
1000 uint32_t imm;
1001 int is_imm;
1002 int insn_len = 2;
1003
1004 rs = dc->op1;
1005 rd = dc->op2;
1006 is_imm = rs == 15 && dc->postinc;
1007
1008 /* Load [$rs] onto T1. */
1009 if (is_imm) {
1010 insn_len = 2 + memsize;
1011 if (memsize == 1)
1012 insn_len++;
1013
1014 imm = ldl_code(dc->pc + 2);
1015 if (memsize != 4) {
1016 if (s_ext) {
1017 imm = sign_extend(imm, (memsize * 8) - 1);
1018 } else {
1019 if (memsize == 1)
1020 imm &= 0xff;
1021 else
1022 imm &= 0xffff;
1023 }
1024 }
1025 DIS(fprintf (logfile, "imm=%x rd=%d sext=%d ms=%d\n",
1026 imm, rd, s_ext, memsize));
edgar_igl05ba7d52008-03-14 01:11:25 +00001027 tcg_gen_movi_tl(cpu_T[1], imm);
ths81700282007-10-08 12:49:08 +00001028 dc->postinc = 0;
1029 } else {
edgar_iglb41f7df2008-05-02 22:16:17 +00001030 gen_load(dc, cpu_T[1], cpu_R[rs], memsize, 0);
ths81700282007-10-08 12:49:08 +00001031 if (s_ext)
edgar_igl05ba7d52008-03-14 01:11:25 +00001032 t_gen_sext(cpu_T[1], cpu_T[1], memsize);
ths81700282007-10-08 12:49:08 +00001033 else
edgar_igl05ba7d52008-03-14 01:11:25 +00001034 t_gen_zext(cpu_T[1], cpu_T[1], memsize);
ths81700282007-10-08 12:49:08 +00001035 }
1036
1037 /* put dest in T0. */
edgar_igl05ba7d52008-03-14 01:11:25 +00001038 t_gen_mov_TN_reg(cpu_T[0], rd);
ths81700282007-10-08 12:49:08 +00001039 return insn_len;
1040}
1041
1042#if DISAS_CRIS
1043static const char *cc_name(int cc)
1044{
1045 static char *cc_names[16] = {
1046 "cc", "cs", "ne", "eq", "vc", "vs", "pl", "mi",
1047 "ls", "hi", "ge", "lt", "gt", "le", "a", "p"
1048 };
1049 assert(cc < 16);
1050 return cc_names[cc];
1051}
1052#endif
1053
edgar_iglb41f7df2008-05-02 22:16:17 +00001054/* Start of insn decoders. */
1055
ths81700282007-10-08 12:49:08 +00001056static unsigned int dec_bccq(DisasContext *dc)
1057{
1058 int32_t offset;
1059 int sign;
1060 uint32_t cond = dc->op2;
1061 int tmp;
1062
1063 offset = EXTRACT_FIELD (dc->ir, 1, 7);
1064 sign = EXTRACT_FIELD(dc->ir, 0, 0);
1065
1066 offset *= 2;
1067 offset |= sign << 8;
1068 tmp = offset;
1069 offset = sign_extend(offset, 8);
1070
1071 /* op2 holds the condition-code. */
1072 cris_cc_mask(dc, 0);
1073 cris_prepare_cc_branch (dc, offset, cond);
1074 return 2;
1075}
1076static unsigned int dec_addoq(DisasContext *dc)
1077{
edgar_iglb41f7df2008-05-02 22:16:17 +00001078 int32_t imm;
ths81700282007-10-08 12:49:08 +00001079
1080 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 7);
1081 imm = sign_extend(dc->op1, 7);
1082
1083 DIS(fprintf (logfile, "addoq %d, $r%u\n", imm, dc->op2));
1084 cris_cc_mask(dc, 0);
1085 /* Fetch register operand, */
edgar_iglb41f7df2008-05-02 22:16:17 +00001086 tcg_gen_addi_tl(cpu_R[R_ACR], cpu_R[dc->op2], imm);
ths81700282007-10-08 12:49:08 +00001087 return 2;
1088}
1089static unsigned int dec_addq(DisasContext *dc)
1090{
1091 DIS(fprintf (logfile, "addq %u, $r%u\n", dc->op1, dc->op2));
1092
1093 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1094
1095 cris_cc_mask(dc, CC_MASK_NZVC);
1096 /* Fetch register operand, */
edgar_igl05ba7d52008-03-14 01:11:25 +00001097 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1098 tcg_gen_movi_tl(cpu_T[1], dc->op1);
ths81700282007-10-08 12:49:08 +00001099 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1100 return 2;
1101}
1102static unsigned int dec_moveq(DisasContext *dc)
1103{
1104 uint32_t imm;
1105
1106 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1107 imm = sign_extend(dc->op1, 5);
1108 DIS(fprintf (logfile, "moveq %d, $r%u\n", imm, dc->op2));
1109
edgar_igl3157a0a2008-03-15 20:45:05 +00001110 t_gen_mov_reg_TN(dc->op2, tcg_const_tl(imm));
ths81700282007-10-08 12:49:08 +00001111 return 2;
1112}
1113static unsigned int dec_subq(DisasContext *dc)
1114{
1115 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1116
1117 DIS(fprintf (logfile, "subq %u, $r%u\n", dc->op1, dc->op2));
1118
1119 cris_cc_mask(dc, CC_MASK_NZVC);
1120 /* Fetch register operand, */
edgar_igl05ba7d52008-03-14 01:11:25 +00001121 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1122 t_gen_mov_TN_im(cpu_T[1], dc->op1);
ths81700282007-10-08 12:49:08 +00001123 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1124 return 2;
1125}
1126static unsigned int dec_cmpq(DisasContext *dc)
1127{
1128 uint32_t imm;
1129 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1130 imm = sign_extend(dc->op1, 5);
1131
1132 DIS(fprintf (logfile, "cmpq %d, $r%d\n", imm, dc->op2));
1133 cris_cc_mask(dc, CC_MASK_NZVC);
edgar_igl05ba7d52008-03-14 01:11:25 +00001134 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1135 t_gen_mov_TN_im(cpu_T[1], imm);
ths81700282007-10-08 12:49:08 +00001136 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
1137 return 2;
1138}
1139static unsigned int dec_andq(DisasContext *dc)
1140{
1141 uint32_t imm;
1142 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1143 imm = sign_extend(dc->op1, 5);
1144
1145 DIS(fprintf (logfile, "andq %d, $r%d\n", imm, dc->op2));
1146 cris_cc_mask(dc, CC_MASK_NZ);
edgar_igl05ba7d52008-03-14 01:11:25 +00001147 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1148 t_gen_mov_TN_im(cpu_T[1], imm);
ths81700282007-10-08 12:49:08 +00001149 crisv32_alu_op(dc, CC_OP_AND, dc->op2, 4);
1150 return 2;
1151}
1152static unsigned int dec_orq(DisasContext *dc)
1153{
1154 uint32_t imm;
1155 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5);
1156 imm = sign_extend(dc->op1, 5);
1157 DIS(fprintf (logfile, "orq %d, $r%d\n", imm, dc->op2));
1158 cris_cc_mask(dc, CC_MASK_NZ);
edgar_igl05ba7d52008-03-14 01:11:25 +00001159 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1160 t_gen_mov_TN_im(cpu_T[1], imm);
ths81700282007-10-08 12:49:08 +00001161 crisv32_alu_op(dc, CC_OP_OR, dc->op2, 4);
1162 return 2;
1163}
1164static unsigned int dec_btstq(DisasContext *dc)
1165{
1166 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1167 DIS(fprintf (logfile, "btstq %u, $r%d\n", dc->op1, dc->op2));
ths81700282007-10-08 12:49:08 +00001168 cris_cc_mask(dc, CC_MASK_NZ);
edgar_igl05ba7d52008-03-14 01:11:25 +00001169 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1170 t_gen_mov_TN_im(cpu_T[1], dc->op1);
ths81700282007-10-08 12:49:08 +00001171 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1172
edgar_iglb41f7df2008-05-02 22:16:17 +00001173 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
edgar_igl3157a0a2008-03-15 20:45:05 +00001174 t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
ths81700282007-10-08 12:49:08 +00001175 dc->flags_live = 1;
1176 return 2;
1177}
1178static unsigned int dec_asrq(DisasContext *dc)
1179{
1180 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1181 DIS(fprintf (logfile, "asrq %u, $r%d\n", dc->op1, dc->op2));
1182 cris_cc_mask(dc, CC_MASK_NZ);
edgar_igl05ba7d52008-03-14 01:11:25 +00001183 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1184 t_gen_mov_TN_im(cpu_T[1], dc->op1);
ths81700282007-10-08 12:49:08 +00001185 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, 4);
1186 return 2;
1187}
1188static unsigned int dec_lslq(DisasContext *dc)
1189{
1190 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1191 DIS(fprintf (logfile, "lslq %u, $r%d\n", dc->op1, dc->op2));
1192
1193 cris_cc_mask(dc, CC_MASK_NZ);
edgar_igl05ba7d52008-03-14 01:11:25 +00001194 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1195 t_gen_mov_TN_im(cpu_T[1], dc->op1);
ths81700282007-10-08 12:49:08 +00001196 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, 4);
1197 return 2;
1198}
1199static unsigned int dec_lsrq(DisasContext *dc)
1200{
1201 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4);
1202 DIS(fprintf (logfile, "lsrq %u, $r%d\n", dc->op1, dc->op2));
1203
1204 cris_cc_mask(dc, CC_MASK_NZ);
edgar_igl05ba7d52008-03-14 01:11:25 +00001205 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1206 t_gen_mov_TN_im(cpu_T[1], dc->op1);
ths81700282007-10-08 12:49:08 +00001207 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, 4);
1208 return 2;
1209}
1210
1211static unsigned int dec_move_r(DisasContext *dc)
1212{
1213 int size = memsize_zz(dc);
1214
1215 DIS(fprintf (logfile, "move.%c $r%u, $r%u\n",
1216 memsize_char(size), dc->op1, dc->op2));
1217
1218 cris_cc_mask(dc, CC_MASK_NZ);
1219 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1220 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, size);
1221 return 2;
1222}
1223
1224static unsigned int dec_scc_r(DisasContext *dc)
1225{
1226 int cond = dc->op2;
1227
1228 DIS(fprintf (logfile, "s%s $r%u\n",
1229 cc_name(cond), dc->op1));
1230
1231 if (cond != CC_A)
1232 {
1233 gen_tst_cc (dc, cond);
edgar_igl3157a0a2008-03-15 20:45:05 +00001234 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
ths81700282007-10-08 12:49:08 +00001235 }
1236 else
edgar_igl3157a0a2008-03-15 20:45:05 +00001237 tcg_gen_movi_tl(cpu_T[1], 1);
ths81700282007-10-08 12:49:08 +00001238
1239 cris_cc_mask(dc, 0);
1240 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1241 return 2;
1242}
1243
1244static unsigned int dec_and_r(DisasContext *dc)
1245{
1246 int size = memsize_zz(dc);
1247
1248 DIS(fprintf (logfile, "and.%c $r%u, $r%u\n",
1249 memsize_char(size), dc->op1, dc->op2));
1250 cris_cc_mask(dc, CC_MASK_NZ);
1251 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1252 crisv32_alu_op(dc, CC_OP_AND, dc->op2, size);
1253 return 2;
1254}
1255
1256static unsigned int dec_lz_r(DisasContext *dc)
1257{
1258 DIS(fprintf (logfile, "lz $r%u, $r%u\n",
1259 dc->op1, dc->op2));
1260 cris_cc_mask(dc, CC_MASK_NZ);
1261 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1262 crisv32_alu_op(dc, CC_OP_LZ, dc->op2, 4);
1263 return 2;
1264}
1265
1266static unsigned int dec_lsl_r(DisasContext *dc)
1267{
1268 int size = memsize_zz(dc);
1269
1270 DIS(fprintf (logfile, "lsl.%c $r%u, $r%u\n",
1271 memsize_char(size), dc->op1, dc->op2));
1272 cris_cc_mask(dc, CC_MASK_NZ);
1273 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
edgar_igl05ba7d52008-03-14 01:11:25 +00001274 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
ths81700282007-10-08 12:49:08 +00001275 crisv32_alu_op(dc, CC_OP_LSL, dc->op2, size);
1276 return 2;
1277}
1278
1279static unsigned int dec_lsr_r(DisasContext *dc)
1280{
1281 int size = memsize_zz(dc);
1282
1283 DIS(fprintf (logfile, "lsr.%c $r%u, $r%u\n",
1284 memsize_char(size), dc->op1, dc->op2));
1285 cris_cc_mask(dc, CC_MASK_NZ);
1286 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
edgar_igl05ba7d52008-03-14 01:11:25 +00001287 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
ths81700282007-10-08 12:49:08 +00001288 crisv32_alu_op(dc, CC_OP_LSR, dc->op2, size);
1289 return 2;
1290}
1291
1292static unsigned int dec_asr_r(DisasContext *dc)
1293{
1294 int size = memsize_zz(dc);
1295
1296 DIS(fprintf (logfile, "asr.%c $r%u, $r%u\n",
1297 memsize_char(size), dc->op1, dc->op2));
1298 cris_cc_mask(dc, CC_MASK_NZ);
1299 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
edgar_igl05ba7d52008-03-14 01:11:25 +00001300 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 63);
ths81700282007-10-08 12:49:08 +00001301 crisv32_alu_op(dc, CC_OP_ASR, dc->op2, size);
1302 return 2;
1303}
1304
1305static unsigned int dec_muls_r(DisasContext *dc)
1306{
1307 int size = memsize_zz(dc);
1308
1309 DIS(fprintf (logfile, "muls.%c $r%u, $r%u\n",
1310 memsize_char(size), dc->op1, dc->op2));
1311 cris_cc_mask(dc, CC_MASK_NZV);
1312 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 1);
edgar_igl05ba7d52008-03-14 01:11:25 +00001313 t_gen_sext(cpu_T[0], cpu_T[0], size);
ths81700282007-10-08 12:49:08 +00001314 crisv32_alu_op(dc, CC_OP_MULS, dc->op2, 4);
1315 return 2;
1316}
1317
1318static unsigned int dec_mulu_r(DisasContext *dc)
1319{
1320 int size = memsize_zz(dc);
1321
1322 DIS(fprintf (logfile, "mulu.%c $r%u, $r%u\n",
1323 memsize_char(size), dc->op1, dc->op2));
1324 cris_cc_mask(dc, CC_MASK_NZV);
1325 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
edgar_igl05ba7d52008-03-14 01:11:25 +00001326 t_gen_zext(cpu_T[0], cpu_T[0], size);
ths81700282007-10-08 12:49:08 +00001327 crisv32_alu_op(dc, CC_OP_MULU, dc->op2, 4);
1328 return 2;
1329}
1330
1331
1332static unsigned int dec_dstep_r(DisasContext *dc)
1333{
1334 DIS(fprintf (logfile, "dstep $r%u, $r%u\n", dc->op1, dc->op2));
1335 cris_cc_mask(dc, CC_MASK_NZ);
edgar_igl05ba7d52008-03-14 01:11:25 +00001336 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
1337 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
ths81700282007-10-08 12:49:08 +00001338 crisv32_alu_op(dc, CC_OP_DSTEP, dc->op2, 4);
1339 return 2;
1340}
1341
1342static unsigned int dec_xor_r(DisasContext *dc)
1343{
1344 int size = memsize_zz(dc);
1345 DIS(fprintf (logfile, "xor.%c $r%u, $r%u\n",
1346 memsize_char(size), dc->op1, dc->op2));
1347 BUG_ON(size != 4); /* xor is dword. */
1348 cris_cc_mask(dc, CC_MASK_NZ);
1349 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1350 crisv32_alu_op(dc, CC_OP_XOR, dc->op2, 4);
1351 return 2;
1352}
1353
1354static unsigned int dec_bound_r(DisasContext *dc)
1355{
1356 int size = memsize_zz(dc);
1357 DIS(fprintf (logfile, "bound.%c $r%u, $r%u\n",
1358 memsize_char(size), dc->op1, dc->op2));
1359 cris_cc_mask(dc, CC_MASK_NZ);
1360 /* TODO: needs optmimization. */
1361 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1362 /* rd should be 4. */
edgar_igl05ba7d52008-03-14 01:11:25 +00001363 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
ths81700282007-10-08 12:49:08 +00001364 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
1365 return 2;
1366}
1367
1368static unsigned int dec_cmp_r(DisasContext *dc)
1369{
1370 int size = memsize_zz(dc);
1371 DIS(fprintf (logfile, "cmp.%c $r%u, $r%u\n",
1372 memsize_char(size), dc->op1, dc->op2));
1373 cris_cc_mask(dc, CC_MASK_NZVC);
1374 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1375 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, size);
1376 return 2;
1377}
1378
1379static unsigned int dec_abs_r(DisasContext *dc)
1380{
edgar_igl3157a0a2008-03-15 20:45:05 +00001381 int l1;
1382
ths81700282007-10-08 12:49:08 +00001383 DIS(fprintf (logfile, "abs $r%u, $r%u\n",
1384 dc->op1, dc->op2));
1385 cris_cc_mask(dc, CC_MASK_NZ);
1386 dec_prep_move_r(dc, dc->op1, dc->op2, 4, 0);
edgar_igl3157a0a2008-03-15 20:45:05 +00001387
1388 /* TODO: consider a branch free approach. */
1389 l1 = gen_new_label();
1390 tcg_gen_brcond_tl(TCG_COND_GE, cpu_T[1], tcg_const_tl(0), l1);
1391 tcg_gen_sub_tl(cpu_T[1], tcg_const_tl(0), cpu_T[1]);
1392 gen_set_label(l1);
ths81700282007-10-08 12:49:08 +00001393 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1394 return 2;
1395}
1396
1397static unsigned int dec_add_r(DisasContext *dc)
1398{
1399 int size = memsize_zz(dc);
1400 DIS(fprintf (logfile, "add.%c $r%u, $r%u\n",
1401 memsize_char(size), dc->op1, dc->op2));
1402 cris_cc_mask(dc, CC_MASK_NZVC);
1403 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1404 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, size);
1405 return 2;
1406}
1407
1408static unsigned int dec_addc_r(DisasContext *dc)
1409{
1410 DIS(fprintf (logfile, "addc $r%u, $r%u\n",
1411 dc->op1, dc->op2));
1412 cris_evaluate_flags(dc);
1413 cris_cc_mask(dc, CC_MASK_NZVC);
1414 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1415 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
1416 return 2;
1417}
1418
1419static unsigned int dec_mcp_r(DisasContext *dc)
1420{
1421 DIS(fprintf (logfile, "mcp $p%u, $r%u\n",
1422 dc->op2, dc->op1));
1423 cris_evaluate_flags(dc);
1424 cris_cc_mask(dc, CC_MASK_RNZV);
edgar_igl05ba7d52008-03-14 01:11:25 +00001425 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1426 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
ths81700282007-10-08 12:49:08 +00001427 crisv32_alu_op(dc, CC_OP_MCP, dc->op1, 4);
1428 return 2;
1429}
1430
1431#if DISAS_CRIS
1432static char * swapmode_name(int mode, char *modename) {
1433 int i = 0;
1434 if (mode & 8)
1435 modename[i++] = 'n';
1436 if (mode & 4)
1437 modename[i++] = 'w';
1438 if (mode & 2)
1439 modename[i++] = 'b';
1440 if (mode & 1)
1441 modename[i++] = 'r';
1442 modename[i++] = 0;
1443 return modename;
1444}
1445#endif
1446
1447static unsigned int dec_swap_r(DisasContext *dc)
1448{
1449 DIS(char modename[4]);
1450 DIS(fprintf (logfile, "swap%s $r%u\n",
1451 swapmode_name(dc->op2, modename), dc->op1));
1452
1453 cris_cc_mask(dc, CC_MASK_NZ);
edgar_igl05ba7d52008-03-14 01:11:25 +00001454 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
ths81700282007-10-08 12:49:08 +00001455 if (dc->op2 & 8)
edgar_igl3157a0a2008-03-15 20:45:05 +00001456 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], -1);
ths81700282007-10-08 12:49:08 +00001457 if (dc->op2 & 4)
edgar_igl3157a0a2008-03-15 20:45:05 +00001458 t_gen_swapw(cpu_T[0], cpu_T[0]);
ths81700282007-10-08 12:49:08 +00001459 if (dc->op2 & 2)
edgar_igl3157a0a2008-03-15 20:45:05 +00001460 t_gen_swapb(cpu_T[0], cpu_T[0]);
ths81700282007-10-08 12:49:08 +00001461 if (dc->op2 & 1)
edgar_igl3157a0a2008-03-15 20:45:05 +00001462 t_gen_swapr(cpu_T[0], cpu_T[0]);
1463 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
ths81700282007-10-08 12:49:08 +00001464 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
1465 return 2;
1466}
1467
1468static unsigned int dec_or_r(DisasContext *dc)
1469{
1470 int size = memsize_zz(dc);
1471 DIS(fprintf (logfile, "or.%c $r%u, $r%u\n",
1472 memsize_char(size), dc->op1, dc->op2));
1473 cris_cc_mask(dc, CC_MASK_NZ);
1474 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1475 crisv32_alu_op(dc, CC_OP_OR, dc->op2, size);
1476 return 2;
1477}
1478
1479static unsigned int dec_addi_r(DisasContext *dc)
1480{
1481 DIS(fprintf (logfile, "addi.%c $r%u, $r%u\n",
1482 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
1483 cris_cc_mask(dc, 0);
1484 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
edgar_igl3157a0a2008-03-15 20:45:05 +00001485 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
edgar_igl05ba7d52008-03-14 01:11:25 +00001486 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1487 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
ths81700282007-10-08 12:49:08 +00001488 return 2;
1489}
1490
1491static unsigned int dec_addi_acr(DisasContext *dc)
1492{
1493 DIS(fprintf (logfile, "addi.%c $r%u, $r%u, $acr\n",
edgar_iglb41f7df2008-05-02 22:16:17 +00001494 memsize_char(memsize_zz(dc)), dc->op2, dc->op1));
ths81700282007-10-08 12:49:08 +00001495 cris_cc_mask(dc, 0);
1496 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
edgar_igl3157a0a2008-03-15 20:45:05 +00001497 t_gen_lsl(cpu_T[0], cpu_T[0], tcg_const_tl(dc->zzsize));
edgar_iglb41f7df2008-05-02 22:16:17 +00001498
edgar_igl05ba7d52008-03-14 01:11:25 +00001499 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1500 t_gen_mov_reg_TN(R_ACR, cpu_T[0]);
ths81700282007-10-08 12:49:08 +00001501 return 2;
1502}
1503
1504static unsigned int dec_neg_r(DisasContext *dc)
1505{
1506 int size = memsize_zz(dc);
1507 DIS(fprintf (logfile, "neg.%c $r%u, $r%u\n",
1508 memsize_char(size), dc->op1, dc->op2));
1509 cris_cc_mask(dc, CC_MASK_NZVC);
1510 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1511 crisv32_alu_op(dc, CC_OP_NEG, dc->op2, size);
1512 return 2;
1513}
1514
1515static unsigned int dec_btst_r(DisasContext *dc)
1516{
1517 DIS(fprintf (logfile, "btst $r%u, $r%u\n",
1518 dc->op1, dc->op2));
ths81700282007-10-08 12:49:08 +00001519 cris_cc_mask(dc, CC_MASK_NZ);
1520 dec_prep_alu_r(dc, dc->op1, dc->op2, 4, 0);
1521 crisv32_alu_op(dc, CC_OP_BTST, dc->op2, 4);
1522
edgar_iglb41f7df2008-05-02 22:16:17 +00001523 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
edgar_igl3157a0a2008-03-15 20:45:05 +00001524 t_gen_mov_preg_TN(PR_CCS, cpu_T[0]);
ths81700282007-10-08 12:49:08 +00001525 dc->flags_live = 1;
1526 return 2;
1527}
1528
1529static unsigned int dec_sub_r(DisasContext *dc)
1530{
1531 int size = memsize_zz(dc);
1532 DIS(fprintf (logfile, "sub.%c $r%u, $r%u\n",
1533 memsize_char(size), dc->op1, dc->op2));
1534 cris_cc_mask(dc, CC_MASK_NZVC);
1535 dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0);
1536 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, size);
1537 return 2;
1538}
1539
1540/* Zero extension. From size to dword. */
1541static unsigned int dec_movu_r(DisasContext *dc)
1542{
1543 int size = memsize_z(dc);
1544 DIS(fprintf (logfile, "movu.%c $r%u, $r%u\n",
1545 memsize_char(size),
1546 dc->op1, dc->op2));
1547
1548 cris_cc_mask(dc, CC_MASK_NZ);
1549 dec_prep_move_r(dc, dc->op1, dc->op2, size, 0);
1550 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1551 return 2;
1552}
1553
1554/* Sign extension. From size to dword. */
1555static unsigned int dec_movs_r(DisasContext *dc)
1556{
1557 int size = memsize_z(dc);
1558 DIS(fprintf (logfile, "movs.%c $r%u, $r%u\n",
1559 memsize_char(size),
1560 dc->op1, dc->op2));
1561
1562 cris_cc_mask(dc, CC_MASK_NZ);
edgar_igl05ba7d52008-03-14 01:11:25 +00001563 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
ths81700282007-10-08 12:49:08 +00001564 /* Size can only be qi or hi. */
edgar_igl05ba7d52008-03-14 01:11:25 +00001565 t_gen_sext(cpu_T[1], cpu_T[0], size);
ths81700282007-10-08 12:49:08 +00001566 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1567 return 2;
1568}
1569
1570/* zero extension. From size to dword. */
1571static unsigned int dec_addu_r(DisasContext *dc)
1572{
1573 int size = memsize_z(dc);
1574 DIS(fprintf (logfile, "addu.%c $r%u, $r%u\n",
1575 memsize_char(size),
1576 dc->op1, dc->op2));
1577
1578 cris_cc_mask(dc, CC_MASK_NZVC);
edgar_igl05ba7d52008-03-14 01:11:25 +00001579 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
ths81700282007-10-08 12:49:08 +00001580 /* Size can only be qi or hi. */
edgar_igl05ba7d52008-03-14 01:11:25 +00001581 t_gen_zext(cpu_T[1], cpu_T[1], size);
1582 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
ths81700282007-10-08 12:49:08 +00001583 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1584 return 2;
1585}
edgar_igl05ba7d52008-03-14 01:11:25 +00001586
ths81700282007-10-08 12:49:08 +00001587/* Sign extension. From size to dword. */
1588static unsigned int dec_adds_r(DisasContext *dc)
1589{
1590 int size = memsize_z(dc);
1591 DIS(fprintf (logfile, "adds.%c $r%u, $r%u\n",
1592 memsize_char(size),
1593 dc->op1, dc->op2));
1594
1595 cris_cc_mask(dc, CC_MASK_NZVC);
edgar_igl05ba7d52008-03-14 01:11:25 +00001596 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
ths81700282007-10-08 12:49:08 +00001597 /* Size can only be qi or hi. */
edgar_igl05ba7d52008-03-14 01:11:25 +00001598 t_gen_sext(cpu_T[1], cpu_T[1], size);
1599 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
1600
ths81700282007-10-08 12:49:08 +00001601 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1602 return 2;
1603}
1604
1605/* Zero extension. From size to dword. */
1606static unsigned int dec_subu_r(DisasContext *dc)
1607{
1608 int size = memsize_z(dc);
1609 DIS(fprintf (logfile, "subu.%c $r%u, $r%u\n",
1610 memsize_char(size),
1611 dc->op1, dc->op2));
1612
1613 cris_cc_mask(dc, CC_MASK_NZVC);
edgar_igl05ba7d52008-03-14 01:11:25 +00001614 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
ths81700282007-10-08 12:49:08 +00001615 /* Size can only be qi or hi. */
edgar_igl05ba7d52008-03-14 01:11:25 +00001616 t_gen_zext(cpu_T[1], cpu_T[1], size);
1617 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
ths81700282007-10-08 12:49:08 +00001618 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1619 return 2;
1620}
1621
1622/* Sign extension. From size to dword. */
1623static unsigned int dec_subs_r(DisasContext *dc)
1624{
1625 int size = memsize_z(dc);
1626 DIS(fprintf (logfile, "subs.%c $r%u, $r%u\n",
1627 memsize_char(size),
1628 dc->op1, dc->op2));
1629
1630 cris_cc_mask(dc, CC_MASK_NZVC);
edgar_igl05ba7d52008-03-14 01:11:25 +00001631 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
ths81700282007-10-08 12:49:08 +00001632 /* Size can only be qi or hi. */
edgar_igl05ba7d52008-03-14 01:11:25 +00001633 t_gen_sext(cpu_T[1], cpu_T[1], size);
1634 t_gen_mov_TN_reg(cpu_T[0], dc->op2);
ths81700282007-10-08 12:49:08 +00001635 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1636 return 2;
1637}
1638
1639static unsigned int dec_setclrf(DisasContext *dc)
1640{
1641 uint32_t flags;
1642 int set = (~dc->opcode >> 2) & 1;
1643
1644 flags = (EXTRACT_FIELD(dc->ir, 12, 15) << 4)
1645 | EXTRACT_FIELD(dc->ir, 0, 3);
1646 DIS(fprintf (logfile, "set=%d flags=%x\n", set, flags));
1647 if (set && flags == 0)
1648 DIS(fprintf (logfile, "nop\n"));
1649 else if (!set && (flags & 0x20))
1650 DIS(fprintf (logfile, "di\n"));
1651 else
1652 DIS(fprintf (logfile, "%sf %x\n",
1653 set ? "set" : "clr",
1654 flags));
1655
1656 if (set && (flags & X_FLAG)) {
1657 dc->flagx_live = 1;
1658 dc->flags_x = 1;
1659 }
1660
1661 /* Simply decode the flags. */
1662 cris_evaluate_flags (dc);
edgar_iglb41f7df2008-05-02 22:16:17 +00001663 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1664 tcg_gen_movi_tl(cc_op, dc->cc_op);
1665
ths81700282007-10-08 12:49:08 +00001666 if (set)
edgar_igla825e702008-03-16 16:51:58 +00001667 gen_op_setf(flags);
ths81700282007-10-08 12:49:08 +00001668 else
edgar_igla825e702008-03-16 16:51:58 +00001669 gen_op_clrf(flags);
ths81700282007-10-08 12:49:08 +00001670 dc->flags_live = 1;
edgar_iglb41f7df2008-05-02 22:16:17 +00001671 dc->clear_x = 0;
ths81700282007-10-08 12:49:08 +00001672 return 2;
1673}
1674
1675static unsigned int dec_move_rs(DisasContext *dc)
1676{
1677 DIS(fprintf (logfile, "move $r%u, $s%u\n", dc->op1, dc->op2));
1678 cris_cc_mask(dc, 0);
edgar_igl05ba7d52008-03-14 01:11:25 +00001679 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
ths81700282007-10-08 12:49:08 +00001680 gen_op_movl_sreg_T0(dc->op2);
1681
edgar_igl05ba7d52008-03-14 01:11:25 +00001682#if !defined(CONFIG_USER_ONLY)
1683 if (dc->op2 == 6)
1684 gen_op_movl_tlb_hi_T0();
1685 else if (dc->op2 == 5) { /* srs is checked at runtime. */
1686 tcg_gen_helper_0_1(helper_tlb_update, cpu_T[0]);
ths81700282007-10-08 12:49:08 +00001687 gen_op_movl_tlb_lo_T0();
edgar_igl05ba7d52008-03-14 01:11:25 +00001688 }
1689#endif
ths81700282007-10-08 12:49:08 +00001690 return 2;
1691}
1692static unsigned int dec_move_sr(DisasContext *dc)
1693{
edgar_igl05ba7d52008-03-14 01:11:25 +00001694 DIS(fprintf (logfile, "move $s%u, $r%u\n", dc->op2, dc->op1));
ths81700282007-10-08 12:49:08 +00001695 cris_cc_mask(dc, 0);
edgar_igl05ba7d52008-03-14 01:11:25 +00001696 gen_op_movl_T0_sreg(dc->op2);
1697 tcg_gen_mov_tl(cpu_T[1], cpu_T[0]);
1698 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, 4);
ths81700282007-10-08 12:49:08 +00001699 return 2;
1700}
1701static unsigned int dec_move_rp(DisasContext *dc)
1702{
1703 DIS(fprintf (logfile, "move $r%u, $p%u\n", dc->op1, dc->op2));
1704 cris_cc_mask(dc, 0);
edgar_iglb41f7df2008-05-02 22:16:17 +00001705
1706 if (dc->op2 == PR_CCS) {
1707 cris_evaluate_flags(dc);
1708 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1709 if (dc->user) {
1710 /* User space is not allowed to touch all flags. */
1711 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0x39f);
1712 tcg_gen_andi_tl(cpu_T[1], cpu_PR[PR_CCS], ~0x39f);
1713 tcg_gen_or_tl(cpu_T[0], cpu_T[1], cpu_T[0]);
1714 }
1715 }
1716 else
1717 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
1718
edgar_igl05ba7d52008-03-14 01:11:25 +00001719 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
edgar_iglb41f7df2008-05-02 22:16:17 +00001720 if (dc->op2 == PR_CCS) {
1721 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
1722 dc->flags_live = 1;
1723 }
ths81700282007-10-08 12:49:08 +00001724 return 2;
1725}
1726static unsigned int dec_move_pr(DisasContext *dc)
1727{
1728 DIS(fprintf (logfile, "move $p%u, $r%u\n", dc->op1, dc->op2));
1729 cris_cc_mask(dc, 0);
balrogfd560592008-01-14 03:18:30 +00001730 /* Support register 0 is hardwired to zero.
1731 Treat it specially. */
1732 if (dc->op2 == 0)
edgar_igl05ba7d52008-03-14 01:11:25 +00001733 tcg_gen_movi_tl(cpu_T[1], 0);
edgar_iglb41f7df2008-05-02 22:16:17 +00001734 else if (dc->op2 == PR_CCS) {
1735 cris_evaluate_flags(dc);
1736 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
1737 } else
edgar_igl05ba7d52008-03-14 01:11:25 +00001738 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
ths81700282007-10-08 12:49:08 +00001739 crisv32_alu_op(dc, CC_OP_MOVE, dc->op1, preg_sizes[dc->op2]);
1740 return 2;
1741}
1742
1743static unsigned int dec_move_mr(DisasContext *dc)
1744{
1745 int memsize = memsize_zz(dc);
1746 int insn_len;
1747 DIS(fprintf (logfile, "move.%c [$r%u%s, $r%u\n",
1748 memsize_char(memsize),
1749 dc->op1, dc->postinc ? "+]" : "]",
1750 dc->op2));
1751
ths81700282007-10-08 12:49:08 +00001752 insn_len = dec_prep_alu_m(dc, 0, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00001753 cris_cc_mask(dc, CC_MASK_NZ);
ths81700282007-10-08 12:49:08 +00001754 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, memsize);
1755 do_postinc(dc, memsize);
1756 return insn_len;
1757}
1758
1759static unsigned int dec_movs_m(DisasContext *dc)
1760{
1761 int memsize = memsize_z(dc);
1762 int insn_len;
1763 DIS(fprintf (logfile, "movs.%c [$r%u%s, $r%u\n",
1764 memsize_char(memsize),
1765 dc->op1, dc->postinc ? "+]" : "]",
1766 dc->op2));
1767
1768 /* sign extend. */
ths81700282007-10-08 12:49:08 +00001769 insn_len = dec_prep_alu_m(dc, 1, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00001770 cris_cc_mask(dc, CC_MASK_NZ);
ths81700282007-10-08 12:49:08 +00001771 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1772 do_postinc(dc, memsize);
1773 return insn_len;
1774}
1775
1776static unsigned int dec_addu_m(DisasContext *dc)
1777{
1778 int memsize = memsize_z(dc);
1779 int insn_len;
1780 DIS(fprintf (logfile, "addu.%c [$r%u%s, $r%u\n",
1781 memsize_char(memsize),
1782 dc->op1, dc->postinc ? "+]" : "]",
1783 dc->op2));
1784
1785 /* sign extend. */
ths81700282007-10-08 12:49:08 +00001786 insn_len = dec_prep_alu_m(dc, 0, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00001787 cris_cc_mask(dc, CC_MASK_NZVC);
ths81700282007-10-08 12:49:08 +00001788 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1789 do_postinc(dc, memsize);
1790 return insn_len;
1791}
1792
1793static unsigned int dec_adds_m(DisasContext *dc)
1794{
1795 int memsize = memsize_z(dc);
1796 int insn_len;
1797 DIS(fprintf (logfile, "adds.%c [$r%u%s, $r%u\n",
1798 memsize_char(memsize),
1799 dc->op1, dc->postinc ? "+]" : "]",
1800 dc->op2));
1801
1802 /* sign extend. */
ths81700282007-10-08 12:49:08 +00001803 insn_len = dec_prep_alu_m(dc, 1, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00001804 cris_cc_mask(dc, CC_MASK_NZVC);
ths81700282007-10-08 12:49:08 +00001805 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, 4);
1806 do_postinc(dc, memsize);
1807 return insn_len;
1808}
1809
1810static unsigned int dec_subu_m(DisasContext *dc)
1811{
1812 int memsize = memsize_z(dc);
1813 int insn_len;
1814 DIS(fprintf (logfile, "subu.%c [$r%u%s, $r%u\n",
1815 memsize_char(memsize),
1816 dc->op1, dc->postinc ? "+]" : "]",
1817 dc->op2));
1818
1819 /* sign extend. */
ths81700282007-10-08 12:49:08 +00001820 insn_len = dec_prep_alu_m(dc, 0, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00001821 cris_cc_mask(dc, CC_MASK_NZVC);
ths81700282007-10-08 12:49:08 +00001822 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1823 do_postinc(dc, memsize);
1824 return insn_len;
1825}
1826
1827static unsigned int dec_subs_m(DisasContext *dc)
1828{
1829 int memsize = memsize_z(dc);
1830 int insn_len;
1831 DIS(fprintf (logfile, "subs.%c [$r%u%s, $r%u\n",
1832 memsize_char(memsize),
1833 dc->op1, dc->postinc ? "+]" : "]",
1834 dc->op2));
1835
1836 /* sign extend. */
ths81700282007-10-08 12:49:08 +00001837 insn_len = dec_prep_alu_m(dc, 1, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00001838 cris_cc_mask(dc, CC_MASK_NZVC);
ths81700282007-10-08 12:49:08 +00001839 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, 4);
1840 do_postinc(dc, memsize);
1841 return insn_len;
1842}
1843
1844static unsigned int dec_movu_m(DisasContext *dc)
1845{
1846 int memsize = memsize_z(dc);
1847 int insn_len;
1848
1849 DIS(fprintf (logfile, "movu.%c [$r%u%s, $r%u\n",
1850 memsize_char(memsize),
1851 dc->op1, dc->postinc ? "+]" : "]",
1852 dc->op2));
1853
ths81700282007-10-08 12:49:08 +00001854 insn_len = dec_prep_alu_m(dc, 0, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00001855 cris_cc_mask(dc, CC_MASK_NZ);
ths81700282007-10-08 12:49:08 +00001856 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
1857 do_postinc(dc, memsize);
1858 return insn_len;
1859}
1860
1861static unsigned int dec_cmpu_m(DisasContext *dc)
1862{
1863 int memsize = memsize_z(dc);
1864 int insn_len;
1865 DIS(fprintf (logfile, "cmpu.%c [$r%u%s, $r%u\n",
1866 memsize_char(memsize),
1867 dc->op1, dc->postinc ? "+]" : "]",
1868 dc->op2));
1869
ths81700282007-10-08 12:49:08 +00001870 insn_len = dec_prep_alu_m(dc, 0, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00001871 cris_cc_mask(dc, CC_MASK_NZVC);
ths81700282007-10-08 12:49:08 +00001872 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, 4);
1873 do_postinc(dc, memsize);
1874 return insn_len;
1875}
1876
1877static unsigned int dec_cmps_m(DisasContext *dc)
1878{
1879 int memsize = memsize_z(dc);
1880 int insn_len;
1881 DIS(fprintf (logfile, "cmps.%c [$r%u%s, $r%u\n",
1882 memsize_char(memsize),
1883 dc->op1, dc->postinc ? "+]" : "]",
1884 dc->op2));
1885
ths81700282007-10-08 12:49:08 +00001886 insn_len = dec_prep_alu_m(dc, 1, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00001887 cris_cc_mask(dc, CC_MASK_NZVC);
ths81700282007-10-08 12:49:08 +00001888 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
1889 do_postinc(dc, memsize);
1890 return insn_len;
1891}
1892
1893static unsigned int dec_cmp_m(DisasContext *dc)
1894{
1895 int memsize = memsize_zz(dc);
1896 int insn_len;
1897 DIS(fprintf (logfile, "cmp.%c [$r%u%s, $r%u\n",
1898 memsize_char(memsize),
1899 dc->op1, dc->postinc ? "+]" : "]",
1900 dc->op2));
1901
ths81700282007-10-08 12:49:08 +00001902 insn_len = dec_prep_alu_m(dc, 0, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00001903 cris_cc_mask(dc, CC_MASK_NZVC);
ths81700282007-10-08 12:49:08 +00001904 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
1905 do_postinc(dc, memsize);
1906 return insn_len;
1907}
1908
1909static unsigned int dec_test_m(DisasContext *dc)
1910{
1911 int memsize = memsize_zz(dc);
1912 int insn_len;
1913 DIS(fprintf (logfile, "test.%d [$r%u%s] op2=%x\n",
1914 memsize_char(memsize),
1915 dc->op1, dc->postinc ? "+]" : "]",
1916 dc->op2));
1917
edgar_iglb41f7df2008-05-02 22:16:17 +00001918 insn_len = dec_prep_alu_m(dc, 0, memsize);
ths81700282007-10-08 12:49:08 +00001919 cris_cc_mask(dc, CC_MASK_NZ);
1920 gen_op_clrf(3);
edgar_iglb41f7df2008-05-02 22:16:17 +00001921
edgar_igl05ba7d52008-03-14 01:11:25 +00001922 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
1923 tcg_gen_movi_tl(cpu_T[1], 0);
ths81700282007-10-08 12:49:08 +00001924 crisv32_alu_op(dc, CC_OP_CMP, dc->op2, memsize_zz(dc));
1925 do_postinc(dc, memsize);
1926 return insn_len;
1927}
1928
1929static unsigned int dec_and_m(DisasContext *dc)
1930{
1931 int memsize = memsize_zz(dc);
1932 int insn_len;
1933 DIS(fprintf (logfile, "and.%d [$r%u%s, $r%u\n",
1934 memsize_char(memsize),
1935 dc->op1, dc->postinc ? "+]" : "]",
1936 dc->op2));
1937
ths81700282007-10-08 12:49:08 +00001938 insn_len = dec_prep_alu_m(dc, 0, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00001939 cris_cc_mask(dc, CC_MASK_NZ);
ths81700282007-10-08 12:49:08 +00001940 crisv32_alu_op(dc, CC_OP_AND, dc->op2, memsize_zz(dc));
1941 do_postinc(dc, memsize);
1942 return insn_len;
1943}
1944
1945static unsigned int dec_add_m(DisasContext *dc)
1946{
1947 int memsize = memsize_zz(dc);
1948 int insn_len;
1949 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
1950 memsize_char(memsize),
1951 dc->op1, dc->postinc ? "+]" : "]",
1952 dc->op2));
1953
ths81700282007-10-08 12:49:08 +00001954 insn_len = dec_prep_alu_m(dc, 0, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00001955 cris_cc_mask(dc, CC_MASK_NZVC);
ths81700282007-10-08 12:49:08 +00001956 crisv32_alu_op(dc, CC_OP_ADD, dc->op2, memsize_zz(dc));
1957 do_postinc(dc, memsize);
1958 return insn_len;
1959}
1960
1961static unsigned int dec_addo_m(DisasContext *dc)
1962{
1963 int memsize = memsize_zz(dc);
1964 int insn_len;
1965 DIS(fprintf (logfile, "add.%d [$r%u%s, $r%u\n",
1966 memsize_char(memsize),
1967 dc->op1, dc->postinc ? "+]" : "]",
1968 dc->op2));
1969
ths81700282007-10-08 12:49:08 +00001970 insn_len = dec_prep_alu_m(dc, 1, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00001971 cris_cc_mask(dc, 0);
edgar_igl90046272008-02-28 08:28:32 +00001972 crisv32_alu_op(dc, CC_OP_ADD, R_ACR, 4);
ths81700282007-10-08 12:49:08 +00001973 do_postinc(dc, memsize);
1974 return insn_len;
1975}
1976
1977static unsigned int dec_bound_m(DisasContext *dc)
1978{
1979 int memsize = memsize_zz(dc);
1980 int insn_len;
1981 DIS(fprintf (logfile, "bound.%d [$r%u%s, $r%u\n",
1982 memsize_char(memsize),
1983 dc->op1, dc->postinc ? "+]" : "]",
1984 dc->op2));
1985
ths81700282007-10-08 12:49:08 +00001986 insn_len = dec_prep_alu_m(dc, 0, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00001987 cris_cc_mask(dc, CC_MASK_NZ);
ths81700282007-10-08 12:49:08 +00001988 crisv32_alu_op(dc, CC_OP_BOUND, dc->op2, 4);
1989 do_postinc(dc, memsize);
1990 return insn_len;
1991}
1992
1993static unsigned int dec_addc_mr(DisasContext *dc)
1994{
1995 int insn_len = 2;
1996 DIS(fprintf (logfile, "addc [$r%u%s, $r%u\n",
1997 dc->op1, dc->postinc ? "+]" : "]",
1998 dc->op2));
1999
2000 cris_evaluate_flags(dc);
ths81700282007-10-08 12:49:08 +00002001 insn_len = dec_prep_alu_m(dc, 0, 4);
edgar_iglb41f7df2008-05-02 22:16:17 +00002002 cris_cc_mask(dc, CC_MASK_NZVC);
ths81700282007-10-08 12:49:08 +00002003 crisv32_alu_op(dc, CC_OP_ADDC, dc->op2, 4);
2004 do_postinc(dc, 4);
2005 return insn_len;
2006}
2007
2008static unsigned int dec_sub_m(DisasContext *dc)
2009{
2010 int memsize = memsize_zz(dc);
2011 int insn_len;
2012 DIS(fprintf (logfile, "sub.%c [$r%u%s, $r%u ir=%x zz=%x\n",
2013 memsize_char(memsize),
2014 dc->op1, dc->postinc ? "+]" : "]",
2015 dc->op2, dc->ir, dc->zzsize));
2016
ths81700282007-10-08 12:49:08 +00002017 insn_len = dec_prep_alu_m(dc, 0, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00002018 cris_cc_mask(dc, CC_MASK_NZVC);
ths81700282007-10-08 12:49:08 +00002019 crisv32_alu_op(dc, CC_OP_SUB, dc->op2, memsize);
2020 do_postinc(dc, memsize);
2021 return insn_len;
2022}
2023
2024static unsigned int dec_or_m(DisasContext *dc)
2025{
2026 int memsize = memsize_zz(dc);
2027 int insn_len;
2028 DIS(fprintf (logfile, "or.%d [$r%u%s, $r%u pc=%x\n",
2029 memsize_char(memsize),
2030 dc->op1, dc->postinc ? "+]" : "]",
2031 dc->op2, dc->pc));
2032
ths81700282007-10-08 12:49:08 +00002033 insn_len = dec_prep_alu_m(dc, 0, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00002034 cris_cc_mask(dc, CC_MASK_NZ);
ths81700282007-10-08 12:49:08 +00002035 crisv32_alu_op(dc, CC_OP_OR, dc->op2, memsize_zz(dc));
2036 do_postinc(dc, memsize);
2037 return insn_len;
2038}
2039
2040static unsigned int dec_move_mp(DisasContext *dc)
2041{
2042 int memsize = memsize_zz(dc);
2043 int insn_len = 2;
2044
2045 DIS(fprintf (logfile, "move.%c [$r%u%s, $p%u\n",
2046 memsize_char(memsize),
2047 dc->op1,
2048 dc->postinc ? "+]" : "]",
2049 dc->op2));
2050
ths81700282007-10-08 12:49:08 +00002051 insn_len = dec_prep_alu_m(dc, 0, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00002052 cris_cc_mask(dc, 0);
2053 if (dc->op2 == PR_CCS) {
2054 cris_evaluate_flags(dc);
2055 if (dc->user) {
2056 /* User space is not allowed to touch all flags. */
2057 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], 0x39f);
2058 tcg_gen_andi_tl(cpu_T[0], cpu_PR[PR_CCS], ~0x39f);
2059 tcg_gen_or_tl(cpu_T[1], cpu_T[0], cpu_T[1]);
2060 }
2061 }
2062
edgar_igl05ba7d52008-03-14 01:11:25 +00002063 t_gen_mov_preg_TN(dc->op2, cpu_T[1]);
ths81700282007-10-08 12:49:08 +00002064
2065 do_postinc(dc, memsize);
2066 return insn_len;
2067}
2068
2069static unsigned int dec_move_pm(DisasContext *dc)
2070{
2071 int memsize;
2072
2073 memsize = preg_sizes[dc->op2];
2074
balrogfd560592008-01-14 03:18:30 +00002075 DIS(fprintf (logfile, "move.%c $p%u, [$r%u%s\n",
2076 memsize_char(memsize),
2077 dc->op2, dc->op1, dc->postinc ? "+]" : "]"));
ths81700282007-10-08 12:49:08 +00002078
balrogfd560592008-01-14 03:18:30 +00002079 /* prepare store. Address in T0, value in T1. */
edgar_igl05ba7d52008-03-14 01:11:25 +00002080 t_gen_mov_TN_preg(cpu_T[1], dc->op2);
2081 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
ths81700282007-10-08 12:49:08 +00002082 gen_store_T0_T1(dc, memsize);
edgar_iglb41f7df2008-05-02 22:16:17 +00002083 cris_cc_mask(dc, 0);
ths81700282007-10-08 12:49:08 +00002084 if (dc->postinc)
2085 {
edgar_igl05ba7d52008-03-14 01:11:25 +00002086 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], memsize);
2087 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
ths81700282007-10-08 12:49:08 +00002088 }
2089 return 2;
2090}
2091
2092static unsigned int dec_movem_mr(DisasContext *dc)
2093{
2094 int i;
2095
2096 DIS(fprintf (logfile, "movem [$r%u%s, $r%u\n", dc->op1,
2097 dc->postinc ? "+]" : "]", dc->op2));
2098
edgar_igl05ba7d52008-03-14 01:11:25 +00002099 /* fetch the address into T0 and T1. */
2100 t_gen_mov_TN_reg(cpu_T[1], dc->op1);
ths81700282007-10-08 12:49:08 +00002101 for (i = 0; i <= dc->op2; i++) {
2102 /* Perform the load onto regnum i. Always dword wide. */
edgar_igl05ba7d52008-03-14 01:11:25 +00002103 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
edgar_iglb41f7df2008-05-02 22:16:17 +00002104 gen_load(dc, cpu_R[i], cpu_T[1], 4, 0);
edgar_igl05ba7d52008-03-14 01:11:25 +00002105 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 4);
ths81700282007-10-08 12:49:08 +00002106 }
edgar_igl05ba7d52008-03-14 01:11:25 +00002107 /* writeback the updated pointer value. */
2108 if (dc->postinc)
2109 t_gen_mov_reg_TN(dc->op1, cpu_T[1]);
edgar_iglb41f7df2008-05-02 22:16:17 +00002110
2111 /* gen_load might want to evaluate the previous insns flags. */
2112 cris_cc_mask(dc, 0);
ths81700282007-10-08 12:49:08 +00002113 return 2;
2114}
2115
2116static unsigned int dec_movem_rm(DisasContext *dc)
2117{
2118 int i;
2119
2120 DIS(fprintf (logfile, "movem $r%u, [$r%u%s\n", dc->op2, dc->op1,
2121 dc->postinc ? "+]" : "]"));
2122
ths81700282007-10-08 12:49:08 +00002123 for (i = 0; i <= dc->op2; i++) {
2124 /* Fetch register i into T1. */
edgar_igl05ba7d52008-03-14 01:11:25 +00002125 t_gen_mov_TN_reg(cpu_T[1], i);
ths81700282007-10-08 12:49:08 +00002126 /* Fetch the address into T0. */
edgar_igl05ba7d52008-03-14 01:11:25 +00002127 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
ths81700282007-10-08 12:49:08 +00002128 /* Displace it. */
edgar_igl05ba7d52008-03-14 01:11:25 +00002129 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], i * 4);
ths81700282007-10-08 12:49:08 +00002130 /* Perform the store. */
2131 gen_store_T0_T1(dc, 4);
2132 }
2133 if (dc->postinc) {
edgar_igl05ba7d52008-03-14 01:11:25 +00002134 /* T0 should point to the last written addr, advance one more
2135 step. */
2136 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 4);
ths81700282007-10-08 12:49:08 +00002137 /* writeback the updated pointer value. */
edgar_igl05ba7d52008-03-14 01:11:25 +00002138 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
ths81700282007-10-08 12:49:08 +00002139 }
edgar_iglb41f7df2008-05-02 22:16:17 +00002140 cris_cc_mask(dc, 0);
ths81700282007-10-08 12:49:08 +00002141 return 2;
2142}
2143
2144static unsigned int dec_move_rm(DisasContext *dc)
2145{
2146 int memsize;
2147
2148 memsize = memsize_zz(dc);
2149
2150 DIS(fprintf (logfile, "move.%d $r%u, [$r%u]\n",
2151 memsize, dc->op2, dc->op1));
2152
ths81700282007-10-08 12:49:08 +00002153 /* prepare store. */
edgar_igl05ba7d52008-03-14 01:11:25 +00002154 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
2155 t_gen_mov_TN_reg(cpu_T[1], dc->op2);
ths81700282007-10-08 12:49:08 +00002156 gen_store_T0_T1(dc, memsize);
2157 if (dc->postinc)
2158 {
edgar_igl05ba7d52008-03-14 01:11:25 +00002159 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], memsize);
2160 t_gen_mov_reg_TN(dc->op1, cpu_T[0]);
ths81700282007-10-08 12:49:08 +00002161 }
edgar_iglb41f7df2008-05-02 22:16:17 +00002162 cris_cc_mask(dc, 0);
ths81700282007-10-08 12:49:08 +00002163 return 2;
2164}
2165
ths81700282007-10-08 12:49:08 +00002166static unsigned int dec_lapcq(DisasContext *dc)
2167{
2168 DIS(fprintf (logfile, "lapcq %x, $r%u\n",
2169 dc->pc + dc->op1*2, dc->op2));
2170 cris_cc_mask(dc, 0);
edgar_igl05ba7d52008-03-14 01:11:25 +00002171 tcg_gen_movi_tl(cpu_T[1], dc->pc + dc->op1 * 2);
ths81700282007-10-08 12:49:08 +00002172 crisv32_alu_op(dc, CC_OP_MOVE, dc->op2, 4);
2173 return 2;
2174}
2175
2176static unsigned int dec_lapc_im(DisasContext *dc)
2177{
2178 unsigned int rd;
2179 int32_t imm;
edgar_iglb41f7df2008-05-02 22:16:17 +00002180 int32_t pc;
ths81700282007-10-08 12:49:08 +00002181
2182 rd = dc->op2;
2183
2184 cris_cc_mask(dc, 0);
2185 imm = ldl_code(dc->pc + 2);
2186 DIS(fprintf (logfile, "lapc 0x%x, $r%u\n", imm + dc->pc, dc->op2));
edgar_iglb41f7df2008-05-02 22:16:17 +00002187
2188 pc = dc->pc;
2189 pc += imm;
2190 t_gen_mov_reg_TN(rd, tcg_const_tl(pc));
edgar_igl05ba7d52008-03-14 01:11:25 +00002191 return 6;
ths81700282007-10-08 12:49:08 +00002192}
2193
2194/* Jump to special reg. */
2195static unsigned int dec_jump_p(DisasContext *dc)
2196{
2197 DIS(fprintf (logfile, "jump $p%u\n", dc->op2));
2198 cris_cc_mask(dc, 0);
edgar_iglb41f7df2008-05-02 22:16:17 +00002199
edgar_igl05ba7d52008-03-14 01:11:25 +00002200 t_gen_mov_TN_preg(cpu_T[0], dc->op2);
edgar_iglb41f7df2008-05-02 22:16:17 +00002201 /* rete will often have low bit set to indicate delayslot. */
2202 tcg_gen_andi_tl(env_btarget, cpu_T[0], ~1);
ths81700282007-10-08 12:49:08 +00002203 cris_prepare_dyn_jmp(dc);
2204 return 2;
2205}
2206
2207/* Jump and save. */
2208static unsigned int dec_jas_r(DisasContext *dc)
2209{
2210 DIS(fprintf (logfile, "jas $r%u, $p%u\n", dc->op1, dc->op2));
2211 cris_cc_mask(dc, 0);
edgar_iglb41f7df2008-05-02 22:16:17 +00002212 /* Store the return address in Pd. */
2213 tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]);
2214 if (dc->op2 > 15)
2215 abort();
2216 tcg_gen_movi_tl(cpu_PR[dc->op2], dc->pc + 4);
2217
ths81700282007-10-08 12:49:08 +00002218 cris_prepare_dyn_jmp(dc);
2219 return 2;
2220}
2221
2222static unsigned int dec_jas_im(DisasContext *dc)
2223{
2224 uint32_t imm;
2225
2226 imm = ldl_code(dc->pc + 2);
2227
2228 DIS(fprintf (logfile, "jas 0x%x\n", imm));
2229 cris_cc_mask(dc, 0);
2230 /* Stor the return address in Pd. */
edgar_iglb41f7df2008-05-02 22:16:17 +00002231 tcg_gen_movi_tl(env_btarget, imm);
edgar_igla825e702008-03-16 16:51:58 +00002232 t_gen_mov_preg_TN(dc->op2, tcg_const_tl(dc->pc + 8));
ths81700282007-10-08 12:49:08 +00002233 cris_prepare_dyn_jmp(dc);
2234 return 6;
2235}
2236
2237static unsigned int dec_jasc_im(DisasContext *dc)
2238{
2239 uint32_t imm;
2240
2241 imm = ldl_code(dc->pc + 2);
2242
2243 DIS(fprintf (logfile, "jasc 0x%x\n", imm));
2244 cris_cc_mask(dc, 0);
2245 /* Stor the return address in Pd. */
edgar_igl05ba7d52008-03-14 01:11:25 +00002246 tcg_gen_movi_tl(cpu_T[0], imm);
edgar_igl3157a0a2008-03-15 20:45:05 +00002247 t_gen_mov_env_TN(btarget, cpu_T[0]);
edgar_igl05ba7d52008-03-14 01:11:25 +00002248 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8 + 4);
2249 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
ths81700282007-10-08 12:49:08 +00002250 cris_prepare_dyn_jmp(dc);
2251 return 6;
2252}
2253
2254static unsigned int dec_jasc_r(DisasContext *dc)
2255{
2256 DIS(fprintf (logfile, "jasc_r $r%u, $p%u\n", dc->op1, dc->op2));
2257 cris_cc_mask(dc, 0);
2258 /* Stor the return address in Pd. */
edgar_igl05ba7d52008-03-14 01:11:25 +00002259 t_gen_mov_TN_reg(cpu_T[0], dc->op1);
edgar_igl3157a0a2008-03-15 20:45:05 +00002260 t_gen_mov_env_TN(btarget, cpu_T[0]);
edgar_igl05ba7d52008-03-14 01:11:25 +00002261 tcg_gen_movi_tl(cpu_T[0], dc->pc + 4 + 4);
2262 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
ths81700282007-10-08 12:49:08 +00002263 cris_prepare_dyn_jmp(dc);
2264 return 2;
2265}
2266
2267static unsigned int dec_bcc_im(DisasContext *dc)
2268{
2269 int32_t offset;
2270 uint32_t cond = dc->op2;
2271
2272 offset = ldl_code(dc->pc + 2);
2273 offset = sign_extend(offset, 15);
2274
2275 DIS(fprintf (logfile, "b%s %d pc=%x dst=%x\n",
2276 cc_name(cond), offset,
2277 dc->pc, dc->pc + offset));
2278
2279 cris_cc_mask(dc, 0);
2280 /* op2 holds the condition-code. */
2281 cris_prepare_cc_branch (dc, offset, cond);
2282 return 4;
2283}
2284
2285static unsigned int dec_bas_im(DisasContext *dc)
2286{
2287 int32_t simm;
2288
2289
2290 simm = ldl_code(dc->pc + 2);
2291
2292 DIS(fprintf (logfile, "bas 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2293 cris_cc_mask(dc, 0);
2294 /* Stor the return address in Pd. */
edgar_igl05ba7d52008-03-14 01:11:25 +00002295 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
edgar_igl3157a0a2008-03-15 20:45:05 +00002296 t_gen_mov_env_TN(btarget, cpu_T[0]);
edgar_igl05ba7d52008-03-14 01:11:25 +00002297 tcg_gen_movi_tl(cpu_T[0], dc->pc + 8);
2298 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
ths81700282007-10-08 12:49:08 +00002299 cris_prepare_dyn_jmp(dc);
2300 return 6;
2301}
2302
2303static unsigned int dec_basc_im(DisasContext *dc)
2304{
2305 int32_t simm;
2306 simm = ldl_code(dc->pc + 2);
2307
2308 DIS(fprintf (logfile, "basc 0x%x, $p%u\n", dc->pc + simm, dc->op2));
2309 cris_cc_mask(dc, 0);
2310 /* Stor the return address in Pd. */
edgar_igl05ba7d52008-03-14 01:11:25 +00002311 tcg_gen_movi_tl(cpu_T[0], dc->pc + simm);
edgar_igl3157a0a2008-03-15 20:45:05 +00002312 t_gen_mov_env_TN(btarget, cpu_T[0]);
edgar_igl05ba7d52008-03-14 01:11:25 +00002313 tcg_gen_movi_tl(cpu_T[0], dc->pc + 12);
2314 t_gen_mov_preg_TN(dc->op2, cpu_T[0]);
ths81700282007-10-08 12:49:08 +00002315 cris_prepare_dyn_jmp(dc);
2316 return 6;
2317}
2318
2319static unsigned int dec_rfe_etc(DisasContext *dc)
2320{
2321 DIS(fprintf (logfile, "rfe_etc opc=%x pc=0x%x op1=%d op2=%d\n",
2322 dc->opcode, dc->pc, dc->op1, dc->op2));
2323
2324 cris_cc_mask(dc, 0);
2325
2326 if (dc->op2 == 15) /* ignore halt. */
edgar_igl05ba7d52008-03-14 01:11:25 +00002327 return 2;
ths81700282007-10-08 12:49:08 +00002328
2329 switch (dc->op2 & 7) {
2330 case 2:
2331 /* rfe. */
2332 cris_evaluate_flags(dc);
2333 gen_op_ccs_rshift();
edgar_iglb41f7df2008-05-02 22:16:17 +00002334 /* FIXME: don't set the P-FLAG if R is set. */
2335 tcg_gen_ori_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], P_FLAG);
2336 /* Debug helper. */
2337 tcg_gen_helper_0_0(helper_rfe);
2338 dc->is_jmp = DISAS_UPDATE;
ths81700282007-10-08 12:49:08 +00002339 break;
2340 case 5:
2341 /* rfn. */
2342 BUG();
2343 break;
2344 case 6:
2345 /* break. */
edgar_igl05ba7d52008-03-14 01:11:25 +00002346 tcg_gen_movi_tl(cpu_T[0], dc->pc);
edgar_igl3157a0a2008-03-15 20:45:05 +00002347 t_gen_mov_env_TN(pc, cpu_T[0]);
ths81700282007-10-08 12:49:08 +00002348 /* Breaks start at 16 in the exception vector. */
2349 gen_op_break_im(dc->op1 + 16);
edgar_iglb41f7df2008-05-02 22:16:17 +00002350 dc->is_jmp = DISAS_UPDATE;
ths81700282007-10-08 12:49:08 +00002351 break;
2352 default:
2353 printf ("op2=%x\n", dc->op2);
2354 BUG();
2355 break;
2356
2357 }
ths81700282007-10-08 12:49:08 +00002358 return 2;
2359}
2360
edgar_igl5d4a5342008-02-25 09:58:22 +00002361static unsigned int dec_ftag_fidx_d_m(DisasContext *dc)
2362{
2363 /* Ignore D-cache flushes. */
2364 return 2;
2365}
2366
2367static unsigned int dec_ftag_fidx_i_m(DisasContext *dc)
2368{
2369 /* Ignore I-cache flushes. */
2370 return 2;
2371}
2372
ths81700282007-10-08 12:49:08 +00002373static unsigned int dec_null(DisasContext *dc)
2374{
2375 printf ("unknown insn pc=%x opc=%x op1=%x op2=%x\n",
2376 dc->pc, dc->opcode, dc->op1, dc->op2);
2377 fflush(NULL);
2378 BUG();
2379 return 2;
2380}
2381
2382struct decoder_info {
2383 struct {
2384 uint32_t bits;
2385 uint32_t mask;
2386 };
2387 unsigned int (*dec)(DisasContext *dc);
2388} decinfo[] = {
2389 /* Order matters here. */
2390 {DEC_MOVEQ, dec_moveq},
2391 {DEC_BTSTQ, dec_btstq},
2392 {DEC_CMPQ, dec_cmpq},
2393 {DEC_ADDOQ, dec_addoq},
2394 {DEC_ADDQ, dec_addq},
2395 {DEC_SUBQ, dec_subq},
2396 {DEC_ANDQ, dec_andq},
2397 {DEC_ORQ, dec_orq},
2398 {DEC_ASRQ, dec_asrq},
2399 {DEC_LSLQ, dec_lslq},
2400 {DEC_LSRQ, dec_lsrq},
2401 {DEC_BCCQ, dec_bccq},
2402
2403 {DEC_BCC_IM, dec_bcc_im},
2404 {DEC_JAS_IM, dec_jas_im},
2405 {DEC_JAS_R, dec_jas_r},
2406 {DEC_JASC_IM, dec_jasc_im},
2407 {DEC_JASC_R, dec_jasc_r},
2408 {DEC_BAS_IM, dec_bas_im},
2409 {DEC_BASC_IM, dec_basc_im},
2410 {DEC_JUMP_P, dec_jump_p},
2411 {DEC_LAPC_IM, dec_lapc_im},
2412 {DEC_LAPCQ, dec_lapcq},
2413
2414 {DEC_RFE_ETC, dec_rfe_etc},
2415 {DEC_ADDC_MR, dec_addc_mr},
2416
2417 {DEC_MOVE_MP, dec_move_mp},
2418 {DEC_MOVE_PM, dec_move_pm},
2419 {DEC_MOVEM_MR, dec_movem_mr},
2420 {DEC_MOVEM_RM, dec_movem_rm},
2421 {DEC_MOVE_PR, dec_move_pr},
2422 {DEC_SCC_R, dec_scc_r},
2423 {DEC_SETF, dec_setclrf},
2424 {DEC_CLEARF, dec_setclrf},
2425
2426 {DEC_MOVE_SR, dec_move_sr},
2427 {DEC_MOVE_RP, dec_move_rp},
2428 {DEC_SWAP_R, dec_swap_r},
2429 {DEC_ABS_R, dec_abs_r},
2430 {DEC_LZ_R, dec_lz_r},
2431 {DEC_MOVE_RS, dec_move_rs},
2432 {DEC_BTST_R, dec_btst_r},
2433 {DEC_ADDC_R, dec_addc_r},
2434
2435 {DEC_DSTEP_R, dec_dstep_r},
2436 {DEC_XOR_R, dec_xor_r},
2437 {DEC_MCP_R, dec_mcp_r},
2438 {DEC_CMP_R, dec_cmp_r},
2439
2440 {DEC_ADDI_R, dec_addi_r},
2441 {DEC_ADDI_ACR, dec_addi_acr},
2442
2443 {DEC_ADD_R, dec_add_r},
2444 {DEC_SUB_R, dec_sub_r},
2445
2446 {DEC_ADDU_R, dec_addu_r},
2447 {DEC_ADDS_R, dec_adds_r},
2448 {DEC_SUBU_R, dec_subu_r},
2449 {DEC_SUBS_R, dec_subs_r},
2450 {DEC_LSL_R, dec_lsl_r},
2451
2452 {DEC_AND_R, dec_and_r},
2453 {DEC_OR_R, dec_or_r},
2454 {DEC_BOUND_R, dec_bound_r},
2455 {DEC_ASR_R, dec_asr_r},
2456 {DEC_LSR_R, dec_lsr_r},
2457
2458 {DEC_MOVU_R, dec_movu_r},
2459 {DEC_MOVS_R, dec_movs_r},
2460 {DEC_NEG_R, dec_neg_r},
2461 {DEC_MOVE_R, dec_move_r},
2462
edgar_igl5d4a5342008-02-25 09:58:22 +00002463 {DEC_FTAG_FIDX_I_M, dec_ftag_fidx_i_m},
2464 {DEC_FTAG_FIDX_D_M, dec_ftag_fidx_d_m},
ths81700282007-10-08 12:49:08 +00002465
2466 {DEC_MULS_R, dec_muls_r},
2467 {DEC_MULU_R, dec_mulu_r},
2468
2469 {DEC_ADDU_M, dec_addu_m},
2470 {DEC_ADDS_M, dec_adds_m},
2471 {DEC_SUBU_M, dec_subu_m},
2472 {DEC_SUBS_M, dec_subs_m},
2473
2474 {DEC_CMPU_M, dec_cmpu_m},
2475 {DEC_CMPS_M, dec_cmps_m},
2476 {DEC_MOVU_M, dec_movu_m},
2477 {DEC_MOVS_M, dec_movs_m},
2478
2479 {DEC_CMP_M, dec_cmp_m},
2480 {DEC_ADDO_M, dec_addo_m},
2481 {DEC_BOUND_M, dec_bound_m},
2482 {DEC_ADD_M, dec_add_m},
2483 {DEC_SUB_M, dec_sub_m},
2484 {DEC_AND_M, dec_and_m},
2485 {DEC_OR_M, dec_or_m},
2486 {DEC_MOVE_RM, dec_move_rm},
2487 {DEC_TEST_M, dec_test_m},
2488 {DEC_MOVE_MR, dec_move_mr},
2489
2490 {{0, 0}, dec_null}
2491};
2492
2493static inline unsigned int
2494cris_decoder(DisasContext *dc)
2495{
2496 unsigned int insn_len = 2;
2497 uint32_t tmp;
2498 int i;
2499
2500 /* Load a halfword onto the instruction register. */
2501 tmp = ldl_code(dc->pc);
2502 dc->ir = tmp & 0xffff;
2503
2504 /* Now decode it. */
2505 dc->opcode = EXTRACT_FIELD(dc->ir, 4, 11);
2506 dc->op1 = EXTRACT_FIELD(dc->ir, 0, 3);
2507 dc->op2 = EXTRACT_FIELD(dc->ir, 12, 15);
2508 dc->zsize = EXTRACT_FIELD(dc->ir, 4, 4);
2509 dc->zzsize = EXTRACT_FIELD(dc->ir, 4, 5);
2510 dc->postinc = EXTRACT_FIELD(dc->ir, 10, 10);
2511
2512 /* Large switch for all insns. */
2513 for (i = 0; i < sizeof decinfo / sizeof decinfo[0]; i++) {
2514 if ((dc->opcode & decinfo[i].mask) == decinfo[i].bits)
2515 {
2516 insn_len = decinfo[i].dec(dc);
2517 break;
2518 }
2519 }
2520
2521 return insn_len;
2522}
2523
2524static void check_breakpoint(CPUState *env, DisasContext *dc)
2525{
2526 int j;
2527 if (env->nb_breakpoints > 0) {
2528 for(j = 0; j < env->nb_breakpoints; j++) {
2529 if (env->breakpoints[j] == dc->pc) {
2530 cris_evaluate_flags (dc);
edgar_igl05ba7d52008-03-14 01:11:25 +00002531 tcg_gen_movi_tl(cpu_T[0], dc->pc);
edgar_igl3157a0a2008-03-15 20:45:05 +00002532 t_gen_mov_env_TN(pc, cpu_T[0]);
ths81700282007-10-08 12:49:08 +00002533 gen_op_debug();
2534 dc->is_jmp = DISAS_UPDATE;
2535 }
2536 }
2537 }
2538}
2539
ths81700282007-10-08 12:49:08 +00002540/* generate intermediate code for basic block 'tb'. */
2541struct DisasContext ctx;
2542static int
2543gen_intermediate_code_internal(CPUState *env, TranslationBlock *tb,
2544 int search_pc)
2545{
2546 uint16_t *gen_opc_end;
2547 uint32_t pc_start;
2548 unsigned int insn_len;
2549 int j, lj;
2550 struct DisasContext *dc = &ctx;
2551 uint32_t next_page_start;
2552
edgar_igla825e702008-03-16 16:51:58 +00002553 if (!logfile)
2554 logfile = stderr;
2555
edgar_iglb41f7df2008-05-02 22:16:17 +00002556 if (tb->pc & 1)
2557 cpu_abort(env, "unaligned pc=%x erp=%x\n",
2558 env->pc, env->pregs[PR_ERP]);
ths81700282007-10-08 12:49:08 +00002559 pc_start = tb->pc;
2560 dc->env = env;
2561 dc->tb = tb;
2562
ths81700282007-10-08 12:49:08 +00002563 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
ths81700282007-10-08 12:49:08 +00002564
2565 dc->is_jmp = DISAS_NEXT;
edgar_iglb41f7df2008-05-02 22:16:17 +00002566 dc->ppc = pc_start;
ths81700282007-10-08 12:49:08 +00002567 dc->pc = pc_start;
2568 dc->singlestep_enabled = env->singlestep_enabled;
edgar_iglb41f7df2008-05-02 22:16:17 +00002569 dc->flags_live = 1;
ths81700282007-10-08 12:49:08 +00002570 dc->flagx_live = 0;
2571 dc->flags_x = 0;
edgar_iglb41f7df2008-05-02 22:16:17 +00002572 dc->cc_mask = 0;
2573 cris_update_cc_op(dc, CC_OP_FLAGS, 4);
2574
2575 dc->user = env->pregs[PR_CCS] & U_FLAG;
2576 dc->delayed_branch = 0;
2577
2578 if (loglevel & CPU_LOG_TB_IN_ASM) {
2579 fprintf(logfile,
2580 "search=%d pc=%x ccs=%x pid=%x usp=%x\n"
2581 "%x.%x.%x.%x\n"
2582 "%x.%x.%x.%x\n"
2583 "%x.%x.%x.%x\n"
2584 "%x.%x.%x.%x\n",
2585 search_pc, env->pc, env->pregs[PR_CCS],
2586 env->pregs[PR_PID], env->pregs[PR_USP],
2587 env->regs[0], env->regs[1], env->regs[2], env->regs[3],
2588 env->regs[4], env->regs[5], env->regs[6], env->regs[7],
2589 env->regs[8], env->regs[9],
2590 env->regs[10], env->regs[11],
2591 env->regs[12], env->regs[13],
2592 env->regs[14], env->regs[15]);
2593
2594 }
edgar_igl3157a0a2008-03-15 20:45:05 +00002595
ths81700282007-10-08 12:49:08 +00002596 next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
2597 lj = -1;
2598 do
2599 {
2600 check_breakpoint(env, dc);
edgar_igl4f400ab2008-02-28 09:37:58 +00002601 if (dc->is_jmp == DISAS_JUMP
2602 || dc->is_jmp == DISAS_SWI)
ths81700282007-10-08 12:49:08 +00002603 goto done;
2604
2605 if (search_pc) {
2606 j = gen_opc_ptr - gen_opc_buf;
2607 if (lj < j) {
2608 lj++;
2609 while (lj < j)
2610 gen_opc_instr_start[lj++] = 0;
2611 }
edgar_iglb41f7df2008-05-02 22:16:17 +00002612 if (dc->delayed_branch == 1) {
2613 gen_opc_pc[lj] = dc->ppc | 1;
2614 gen_opc_instr_start[lj] = 0;
2615 }
2616 else {
2617 gen_opc_pc[lj] = dc->pc;
2618 gen_opc_instr_start[lj] = 1;
2619 }
ths81700282007-10-08 12:49:08 +00002620 }
2621
edgar_iglb41f7df2008-05-02 22:16:17 +00002622 dc->clear_x = 1;
ths81700282007-10-08 12:49:08 +00002623 insn_len = cris_decoder(dc);
2624 STATS(gen_op_exec_insn());
edgar_iglb41f7df2008-05-02 22:16:17 +00002625 dc->ppc = dc->pc;
ths81700282007-10-08 12:49:08 +00002626 dc->pc += insn_len;
edgar_iglb41f7df2008-05-02 22:16:17 +00002627 if (dc->clear_x)
2628 cris_clear_x_flag(dc);
ths81700282007-10-08 12:49:08 +00002629
2630 /* Check for delayed branches here. If we do it before
2631 actually genereating any host code, the simulator will just
2632 loop doing nothing for on this program location. */
2633 if (dc->delayed_branch) {
2634 dc->delayed_branch--;
2635 if (dc->delayed_branch == 0)
2636 {
2637 if (dc->bcc == CC_A) {
bellard57fec1f2008-02-01 10:50:11 +00002638 gen_op_jmp1 ();
edgar_iglb41f7df2008-05-02 22:16:17 +00002639 dc->is_jmp = DISAS_JUMP;
ths81700282007-10-08 12:49:08 +00002640 }
2641 else {
2642 /* Conditional jmp. */
2643 gen_op_cc_jmp (dc->delayed_pc, dc->pc);
edgar_iglb41f7df2008-05-02 22:16:17 +00002644 dc->is_jmp = DISAS_JUMP;
ths81700282007-10-08 12:49:08 +00002645 }
2646 }
2647 }
2648
2649 if (env->singlestep_enabled)
2650 break;
2651 } while (!dc->is_jmp && gen_opc_ptr < gen_opc_end
edgar_iglb41f7df2008-05-02 22:16:17 +00002652 && ((dc->pc < next_page_start) || dc->delayed_branch));
2653
2654 if (dc->delayed_branch == 1) {
2655 /* Reexecute the last insn. */
2656 dc->pc = dc->ppc;
2657 }
ths81700282007-10-08 12:49:08 +00002658
2659 if (!dc->is_jmp) {
edgar_iglb41f7df2008-05-02 22:16:17 +00002660 D(printf("!jmp pc=%x jmp=%d db=%d\n", dc->pc,
2661 dc->is_jmp, dc->delayed_branch));
2662 /* T0 and env_pc should hold the new pc. */
edgar_igl3157a0a2008-03-15 20:45:05 +00002663 tcg_gen_movi_tl(cpu_T[0], dc->pc);
edgar_iglb41f7df2008-05-02 22:16:17 +00002664 tcg_gen_mov_tl(env_pc, cpu_T[0]);
ths81700282007-10-08 12:49:08 +00002665 }
2666
2667 cris_evaluate_flags (dc);
2668 done:
2669 if (__builtin_expect(env->singlestep_enabled, 0)) {
2670 gen_op_debug();
2671 } else {
2672 switch(dc->is_jmp) {
2673 case DISAS_NEXT:
2674 gen_goto_tb(dc, 1, dc->pc);
2675 break;
2676 default:
2677 case DISAS_JUMP:
2678 case DISAS_UPDATE:
2679 /* indicate that the hash table must be used
2680 to find the next TB */
bellard57fec1f2008-02-01 10:50:11 +00002681 tcg_gen_exit_tb(0);
ths81700282007-10-08 12:49:08 +00002682 break;
edgar_igl4f400ab2008-02-28 09:37:58 +00002683 case DISAS_SWI:
ths81700282007-10-08 12:49:08 +00002684 case DISAS_TB_JUMP:
2685 /* nothing more to generate */
2686 break;
2687 }
2688 }
2689 *gen_opc_ptr = INDEX_op_end;
2690 if (search_pc) {
2691 j = gen_opc_ptr - gen_opc_buf;
2692 lj++;
2693 while (lj <= j)
2694 gen_opc_instr_start[lj++] = 0;
2695 } else {
2696 tb->size = dc->pc - pc_start;
2697 }
2698
2699#ifdef DEBUG_DISAS
2700 if (loglevel & CPU_LOG_TB_IN_ASM) {
2701 fprintf(logfile, "--------------\n");
2702 fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2703 target_disas(logfile, pc_start, dc->pc + 4 - pc_start, 0);
edgar_iglb41f7df2008-05-02 22:16:17 +00002704 fprintf(logfile, "\nisize=%d osize=%d\n",
2705 dc->pc - pc_start, gen_opc_ptr - gen_opc_buf);
ths81700282007-10-08 12:49:08 +00002706 }
2707#endif
2708 return 0;
2709}
2710
2711int gen_intermediate_code (CPUState *env, struct TranslationBlock *tb)
2712{
2713 return gen_intermediate_code_internal(env, tb, 0);
2714}
2715
2716int gen_intermediate_code_pc (CPUState *env, struct TranslationBlock *tb)
2717{
2718 return gen_intermediate_code_internal(env, tb, 1);
2719}
2720
2721void cpu_dump_state (CPUState *env, FILE *f,
2722 int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2723 int flags)
2724{
2725 int i;
2726 uint32_t srs;
2727
2728 if (!env || !f)
2729 return;
2730
2731 cpu_fprintf(f, "PC=%x CCS=%x btaken=%d btarget=%x\n"
2732 "cc_op=%d cc_src=%d cc_dest=%d cc_result=%x cc_mask=%x\n"
2733 "debug=%x %x %x\n",
edgar_igl90046272008-02-28 08:28:32 +00002734 env->pc, env->pregs[PR_CCS], env->btaken, env->btarget,
ths81700282007-10-08 12:49:08 +00002735 env->cc_op,
2736 env->cc_src, env->cc_dest, env->cc_result, env->cc_mask,
2737 env->debug1, env->debug2, env->debug3);
2738
2739 for (i = 0; i < 16; i++) {
2740 cpu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
2741 if ((i + 1) % 4 == 0)
2742 cpu_fprintf(f, "\n");
2743 }
2744 cpu_fprintf(f, "\nspecial regs:\n");
2745 for (i = 0; i < 16; i++) {
2746 cpu_fprintf(f, "p%2.2d=%8.8x ", i, env->pregs[i]);
2747 if ((i + 1) % 4 == 0)
2748 cpu_fprintf(f, "\n");
2749 }
edgar_igl90046272008-02-28 08:28:32 +00002750 srs = env->pregs[PR_SRS];
edgar_iglb41f7df2008-05-02 22:16:17 +00002751 cpu_fprintf(f, "\nsupport function regs bank %x:\n", srs);
ths81700282007-10-08 12:49:08 +00002752 if (srs < 256) {
2753 for (i = 0; i < 16; i++) {
2754 cpu_fprintf(f, "s%2.2d=%8.8x ",
2755 i, env->sregs[srs][i]);
2756 if ((i + 1) % 4 == 0)
2757 cpu_fprintf(f, "\n");
2758 }
2759 }
2760 cpu_fprintf(f, "\n\n");
2761
2762}
2763
edgar_igl05ba7d52008-03-14 01:11:25 +00002764static void tcg_macro_func(TCGContext *s, int macro_id, const int *dead_args)
2765{
2766}
2767
bellardaaed9092007-11-10 15:15:54 +00002768CPUCRISState *cpu_cris_init (const char *cpu_model)
ths81700282007-10-08 12:49:08 +00002769{
2770 CPUCRISState *env;
edgar_igla825e702008-03-16 16:51:58 +00002771 int i;
ths81700282007-10-08 12:49:08 +00002772
2773 env = qemu_mallocz(sizeof(CPUCRISState));
2774 if (!env)
2775 return NULL;
2776 cpu_exec_init(env);
edgar_igl05ba7d52008-03-14 01:11:25 +00002777
2778 tcg_set_macro_func(&tcg_ctx, tcg_macro_func);
2779 cpu_env = tcg_global_reg_new(TCG_TYPE_PTR, TCG_AREG0, "env");
2780#if TARGET_LONG_BITS > HOST_LONG_BITS
2781 cpu_T[0] = tcg_global_mem_new(TCG_TYPE_TL,
2782 TCG_AREG0, offsetof(CPUState, t0), "T0");
2783 cpu_T[1] = tcg_global_mem_new(TCG_TYPE_TL,
2784 TCG_AREG0, offsetof(CPUState, t1), "T1");
2785#else
2786 cpu_T[0] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG1, "T0");
2787 cpu_T[1] = tcg_global_reg_new(TCG_TYPE_TL, TCG_AREG2, "T1");
2788#endif
2789
edgar_igla825e702008-03-16 16:51:58 +00002790 cc_src = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2791 offsetof(CPUState, cc_src), "cc_src");
2792 cc_dest = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2793 offsetof(CPUState, cc_dest),
2794 "cc_dest");
2795 cc_result = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2796 offsetof(CPUState, cc_result),
2797 "cc_result");
2798 cc_op = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2799 offsetof(CPUState, cc_op), "cc_op");
2800 cc_size = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2801 offsetof(CPUState, cc_size),
2802 "cc_size");
2803 cc_mask = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2804 offsetof(CPUState, cc_mask),
2805 "cc_mask");
2806
edgar_iglb41f7df2008-05-02 22:16:17 +00002807 env_pc = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2808 offsetof(CPUState, pc),
2809 "pc");
2810 env_btarget = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2811 offsetof(CPUState, btarget),
2812 "btarget");
2813
edgar_igla825e702008-03-16 16:51:58 +00002814 for (i = 0; i < 16; i++) {
2815 cpu_R[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2816 offsetof(CPUState, regs[i]),
2817 regnames[i]);
2818 }
2819 for (i = 0; i < 16; i++) {
2820 cpu_PR[i] = tcg_global_mem_new(TCG_TYPE_PTR, TCG_AREG0,
2821 offsetof(CPUState, pregs[i]),
2822 pregnames[i]);
2823 }
2824
edgar_iglb41f7df2008-05-02 22:16:17 +00002825 TCG_HELPER(helper_tlb_update);
2826 TCG_HELPER(helper_tlb_flush);
2827 TCG_HELPER(helper_rfe);
2828 TCG_HELPER(helper_store);
2829 TCG_HELPER(helper_dump);
2830 TCG_HELPER(helper_dummy);
2831
2832 TCG_HELPER(helper_evaluate_flags_muls);
2833 TCG_HELPER(helper_evaluate_flags_mulu);
2834 TCG_HELPER(helper_evaluate_flags_mcp);
2835 TCG_HELPER(helper_evaluate_flags_alu_4);
2836 TCG_HELPER(helper_evaluate_flags_move_4);
2837 TCG_HELPER(helper_evaluate_flags_move_2);
2838 TCG_HELPER(helper_evaluate_flags);
2839
ths81700282007-10-08 12:49:08 +00002840 cpu_reset(env);
2841 return env;
2842}
2843
2844void cpu_reset (CPUCRISState *env)
2845{
2846 memset(env, 0, offsetof(CPUCRISState, breakpoints));
2847 tlb_flush(env, 1);
edgar_iglb41f7df2008-05-02 22:16:17 +00002848
2849#if defined(CONFIG_USER_ONLY)
2850 /* start in user mode with interrupts enabled. */
2851 env->pregs[PR_CCS] |= U_FLAG | I_FLAG;
2852#else
2853 env->pregs[PR_CCS] = 0;
2854#endif
ths81700282007-10-08 12:49:08 +00002855}
aurel32d2856f12008-04-28 00:32:32 +00002856
2857void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
2858 unsigned long searched_pc, int pc_pos, void *puc)
2859{
edgar_iglb41f7df2008-05-02 22:16:17 +00002860 env->pc = gen_opc_pc[pc_pos];
aurel32d2856f12008-04-28 00:32:32 +00002861}